- d3d2483 arch, cpu, dev, gpu, mem, sim, python: start using getPort. by Gabe Black · 6 years ago
- 96cc03f mem-cache: alias to mem::getMasterPort in TLB class by Andrea Mondelli · 6 years ago
- cb7fe24 x86: Call the base class's regStats in X86ISA::TLB by Bagus Hanindhito · 6 years ago
- b859a70 x86: Stop using/defining some ISA specific register types. by Gabe Black · 6 years ago
- f54020e misc: Using smart pointers for memory Requests by Giacomo Travaglini · 7 years ago
- a4e7227 tarch, mem: Abstract the data stored in the SE page tables. by Gabe Black · 7 years ago
- 2a15bfd arch, mem: Make the page table lookup function return a pointer. by Gabe Black · 7 years ago
- b7618c6 arch,cpu: "virtualize" the TLB interface. by Gabe Black · 7 years ago
- c305e15 x86: Add stats to X86 TLB by Swapnil Haria · 8 years ago
- 748b87f x86: remove redundant condition check in tlb code by Brandon Potter · 8 years ago
- a928a43 style: [patch 3/22] reduce include dependencies in some headers by Brandon Potter · 8 years ago
- 7a8dda4 style: [patch 1/22] use /r/3648/ to reorganize includes by Brandon Potter · 8 years ago
- 2c43a21 x86: Force strict ordering for memory mapped m5ops by Michael LeBeane · 8 years ago
- 698767e cpu, arch: fix the type used for the request flags by Nikos Nikoleris · 8 years ago
- 76cd439 sim: Refactor the serialization base class by Andreas Sandberg · 10 years ago
- 4828137 mem, cpu: Add a separate flag for strictly ordered memory by Andreas Sandberg · 10 years ago
- adbaa4d kvm, x86: Adding support for SE mode execution by Alexandru Dutu · 10 years ago
- a2d246b arch: Use shared_ptr for all Faults by Andreas Hansson · 10 years ago
- 5e77384 mem: Use a flag instead of address bit 63 for generic IPRs by Andreas Sandberg · 11 years ago
- fec2dea x86: Add support for m5ops through a memory mapped interface by Andreas Sandberg · 11 years ago
- e038741 x86: add tlb checkpointing by Nilay Vaish · 11 years ago
- 7846f59 arch: Create a method to finalize physical addresses in the TLB by Andreas Sandberg · 12 years ago
- 94561dd arch: Add support for invalidating TLBs when draining by Andreas Sandberg · 12 years ago
- 2a740aa Port: Add protocol-agnostic ports in the port hierarchy by Andreas Hansson · 12 years ago
- d660979 X86 TLB: Add a missing = sign by Nilay Vaish · 13 years ago
- 7183c3f X86 TLB: Fix for gcc 4.4.3 by Jayneel Gandhi · 13 years ago
- d9988de X86: Use the HandyM5Reg to avoid a register read and some logic in the TLB. by Gabe Black · 13 years ago
- 1d96135 X86: Truncate addresses to 32 bits except in 64 bit mode, not long mode. by Gabe Black · 13 years ago
- 64bf90d X86: Clear out duplicate TLB entries when adding a new one. by Gabe Black · 13 years ago
- aacb676 X86: Use the AddrTrie class to implement the TLB. by Gabe Black · 13 years ago
- a7859f7 X86: Fix address size handling so real mode works properly. by Gabe Black · 13 years ago
- f9d403a MEM: Introduce the master/slave port sub-classes in C++ by William Wang · 13 years ago
- 7253829 gcc: Clean-up of non-C++0x compliant code, first steps by Andreas Hansson · 13 years ago
- 98cf57f CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPU by Geoffrey Blake · 13 years ago
- 4b32c9f x86: Fix x86 TLB and Walker by Nilay Vaish · 13 years ago
- 241cc0c Another merge with the main repository. by Gabe Black · 13 years ago
- bd23a37 X86 TLB: Move a DPRINTF to its correct place by Nilay Vaish · 13 years ago
- 1d8822a X86: Get rid of more uses of FULL_SYSTEM. by Gabe Black · 13 years ago
- facb40f SE/FS: Make getProcessPtr available in both modes, and get rid of FULL_SYSTEMs. by Gabe Black · 13 years ago
- 8adc678 X86: Turn on the page table walker in SE mode. by Gabe Black · 13 years ago
- 40b6c9c X86: Move the MSR lookup table out of the TLB and into its own file. by Gabe Black · 13 years ago
- a1ad9e6 Stack: Tidy up some comments, a warning, and make stack extension consistent. by Gabe Black · 13 years ago
- 3bd0b96 X86,TLB: Make sure the "delayedResponse" variable is always set. by Gabe Black · 13 years ago
- 3659663 TLB: comments and a helpful warning. by Lisa Hsu · 13 years ago
- eddac53 trace: reimplement the DTRACE function so it doesn't use a vector by Nathan Binkert · 14 years ago
- 39a0556 includes: sort all includes by Nathan Binkert · 14 years ago
- 579c5f0 Spelling: Fix the a spelling error by changing mmaped to mmapped. by Gabe Black · 14 years ago
- d3214c5 X86: If PCI config space is disabled, pass through to regular IO addresses. by Gabe Black · 14 years ago
- 44e5e7e X86: Obey the wp bit of CR0. by Tim Harris · 14 years ago
- 3a2d222 x86: Timing support for pagetable walker by Joel Hestness · 14 years ago
- c69d48f Make commenting on close namespace brackets consistent. by Steve Reinhardt · 14 years ago
- 3cd349f X86: Obey the PCD (cache disable) bit in the page tables. by Gabe Black · 14 years ago
- c8c921b X86: Mark IO space accesses as uncachable. by Gabe Black · 14 years ago
- 6f4bd2c ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. by Gabe Black · 14 years ago
- 25ffa8e X86: Create a directory for files that define register indexes. by Gabe Black · 14 years ago
- f6182f9 X86: Make the TLB fault instead of panic when something is unmapped in SE mode. by Gabe Black · 14 years ago
- 13d6490 copyright: Change HP copyright on x86 code to be more friendly by Nathan Binkert · 15 years ago
- bbbfdee X86: Don't panic on faults on prefetches in SE mode. by Gabe Black · 15 years ago
- 44e912c X86: Explain what really didn't work with unmapped addresses in SE mode. by Gabe Black · 15 years ago
- 1c28004 Clean up some inconsistencies with Request flags. by Steve Reinhardt · 15 years ago
- 0cb180e Registers: Eliminate the ISA defined floating point register file. by Gabe Black · 16 years ago
- 32daf6f Registers: Add an ISA object which replaces the MiscRegFile. by Gabe Black · 16 years ago
- b6bfe8a X86: Split out the internal memory space from the regular translate() and precompute mode. by Gabe Black · 16 years ago
- ee7055c X86: Put the StoreCheck flag with the others, and don't collide with other flags. by Gabe Black · 16 years ago
- 6910baa X86: Fix how the TLB handles the storecheck flag. by Gabe Black · 16 years ago
- 3b1b21c X86: Some segment selectors can be used when "NULL". by Gabe Black · 16 years ago
- e0de2c3 tlb: More fixing of unified TLB by Nathan Binkert · 16 years ago
- 7b5a96f tlb: Don't separate the TLB classes into an instruction TLB and a data TLB by Gabe Black · 16 years ago
- 4523741 quell gcc 4.3 warning by Nathan Binkert · 16 years ago
- 9dfa3f7 X86: Fix segment limit checks. by Gabe Black · 16 years ago
- c849ef5 X86: Actually check page protections. by Gabe Black · 16 years ago
- dc53ca8 X86: Add a flag to force memory accesses to happen at CPL 0. by Gabe Black · 16 years ago
- 40fdba2 X86: Make the X86 TLB take advantage of delayed translations, and get rid of the fake TLB miss faults. by Gabe Black · 16 years ago
- 6ed47e9 CPU: Implement translateTiming which defers to translateAtomic, and convert the timing simple CPU to use it. by Gabe Black · 16 years ago
- 5605079 ISA: Replace the translate functions in the TLBs with translateAtomic. by Gabe Black · 16 years ago
- e8c1c3e X86: Pass whether an access was a read/write/fetch so faults can behave accordingly. by Gabe Black · 16 years ago
- 06cdbe5 X86: Compute PCI config addresses correctly. by Gabe Black · 16 years ago
- 9c49bc7 mem: update stuff for changes to Packet and Request by Nathan Binkert · 16 years ago
- d857faf Add in Context IDs to the simulator. From now on, cpuId is almost never used, by Lisa Hsu · 16 years ago
- c55a467 make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered by Lisa Hsu · 16 years ago
- 42ebebf X86: Make the local APIC accessible through the memory system directly, and make the timer work. by Gabe Black · 16 years ago
- d9f9c96 Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object. by Gabe Black · 16 years ago
- 6b8d036 X86: Rename the divide count register to divide configuration. by Gabe Black · 17 years ago
- 66f54a6 X86: Change how segment loading is performed. by Gabe Black · 17 years ago
- b052992 X86: In non 64bit mode, throw a fault when a NULL segment is accessed. by Gabe Black · 17 years ago
- 8688ef3 X86: Have all 8 machine check registers since the kernel assumes they're there. by Gabe Black · 17 years ago
- a8e3001 X86: Bypass unaligned access support for register addressed MSRs. by Gabe Black · 17 years ago
- b3e5533 X86: Remove enforcement of APIC register access alignment. Panic if more than one register is accessed at a time. by Gabe Black · 17 years ago
- 66aaabf X86: Don't map the local APIC into the physical address space in SE mode. by Gabe Black · 17 years ago
- 43ecce5 X86: Put in initial implementation of the local APIC. by Gabe Black · 17 years ago
- 98d2ca4 X86: Implement the INVLPG instruction and the TIA microop. by Gabe Black · 17 years ago
- 8b4796a TLB: Make a TLB base class and put a virtual demapPage function in it. by Gabe Black · 17 years ago
- 7bde028 X86: Get PCI config space to work, and adjust address space prefix numbering scheme. by Gabe Black · 17 years ago
- 223e48e X86: Make the IO ports work using extra physical address lines. Add a serial port. by Gabe Black · 17 years ago
- dc6f960 X86: Reorganize segmentation and implement segment selector movs. by Gabe Black · 17 years ago
- 1048b54 X86: Separate out the page table walker into it's own cc and hh. by Gabe Black · 17 years ago
- 917ae9e X86: Fix a stupid typo where WRMSR and RDMSR were switched, and add a debug statement. by Gabe Black · 17 years ago
- 4950798 X86: Implement tlb invalidation and make it happen some of the times it should. by Gabe Black · 17 years ago
- fce45ba X86: Work on the page table walker, TLB, and related faults. by Gabe Black · 17 years ago
- f17f3d2 X86: Implement a page table walker. by Gabe Black · 17 years ago