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gem5 / testing / jenkins-gem5-prod / f9d403a7b95c50a8b75f8442101eb87ca465f967
  1. f9d403a MEM: Introduce the master/slave port sub-classes in C++ by William Wang · 13 years ago
  2. a14013a CPU: Unify initMemProxies across CPUs and simulation modes by Andreas Hansson · 13 years ago
  3. 390cfc7 Config: Change the way options are added by Nilay Vaish · 13 years ago
  4. 6ca3af8 Config: Move setWorkCountOptions() to Simulation.py by Nilay Vaish · 13 years ago
  5. 9d7c715 range_map: Enable const find and iteration by Andreas Hansson · 13 years ago
  6. 312efd7 Power: Change bitfield name to avoid conflicts with range_map by Andreas Hansson · 13 years ago
  7. ca9790a Ruby: Fix Set::print for 32-bit hosts by Andreas Hansson · 13 years ago
  8. 9727b1b MEM: Unify bus access methods and prepare for master/slave split by Andreas Hansson · 13 years ago
  9. c2d2ea9 MEM: Split SimpleTimingPort into PacketQueue and ports by Andreas Hansson · 13 years ago
  10. fb395b5 Scons: Remove Werror=False in SConscript files by Andreas Hansson · 13 years ago
  11. 1274283 Python: Fix a conditional expression that requires Python 2.5 by Andreas Hansson · 13 years ago
  12. 3c66608 ARM: Update stats for IT and conditional branch changes by Ali Saidi · 13 years ago
  13. 8e2a8fb ARM: Fix case where cond/uncond control is mis-specified by Nathanael Premillieu · 13 years ago
  14. ed8ed6e ARM: Clean up condCodes in IT blocks. by Ali Saidi · 13 years ago
  15. a64319f ARM: IT doesn't need to be serializing. by Geoffrey Blake · 13 years ago
  16. b4e5be7 O3: Fix sizing of decode to rename skid buffer. by Andrew Lukefahr · 13 years ago
  17. 0376422 ARM: Add RTC to PBX System by Koan-Sin Tan · 13 years ago
  18. 565c1de O3: Fix size of skid buffer between fetch and decode when widths are different by Brian Grayson · 13 years ago
  19. 1981ba2 ARM: Fix uninitialized value in ARM RTC model. by Ali Saidi · 13 years ago
  20. c9e4bca Garnet: Stats at vnet granularity + code cleanup by Tushar Krishna · 13 years ago
  21. 7253829 gcc: Clean-up of non-C++0x compliant code, first steps by Andreas Hansson · 13 years ago
  22. adb8621 clang: Fix recently introduced clang compilation errors by Andreas Hansson · 13 years ago
  23. a444a6f scripts: Fix to ensure that port connection count is always set by Andreas Hansson · 13 years ago
  24. f02eec9 ruby_fs.py: Add call to createInterruptController() by Nilay Vaish · 13 years ago
  25. 13a5e9b FSConfig.py: fix a typo makeLinuxAlphaRubySystem by Nilay Vaish · 13 years ago
  26. 24fe7cd build: remove implicit-cache setting of scons from recent build faster patch by Marc Orr · 13 years ago
  27. bb7be54 se.py: Changes to ruby portion due to SE/FS merge by Nilay Vaish · 13 years ago
  28. 9818565 O3: Add fatal when fetchWidth > Impl::MaxWidth. by Brian Grayson · 13 years ago
  29. d2a0db7 ARM: Fix memory starting at non-zero address and exceeding max mem for a system. by Ali Saidi · 13 years ago
  30. 4700513 ARM: Update stats for CBNZ fix. by Ali Saidi · 13 years ago
  31. 9a9a4a0 ARM: Fix branch prediction issue with CB(N)Z instruction by Brian Grayson · 13 years ago
  32. 927bba9 ARM: Update stats for valgrind fix and replace config.inis which are out of date. by Ali Saidi · 13 years ago
  33. 69d229c O3/Ozone: Eliminate dead code counting software prefetch insts by Geoffrey Blake · 13 years ago
  34. da0d67c CheckerCPU: Make some basic regression tests for CheckerCPU by Geoffrey Blake · 13 years ago
  35. 98cf57f CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPU by Geoffrey Blake · 13 years ago
  36. 043709f CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable by Geoffrey Blake · 13 years ago
  37. df05ffa ARM: Don't reset CPUs that are going to be switched in. by Ali Saidi · 13 years ago
  38. 3ce2d0f System: Move code in initState() back into constructor whenever possible. by Ali Saidi · 13 years ago
  39. ec1ef24 ARM: Fix valgrind reported error on O3 that was causing minor stats changes. by Ali Saidi · 13 years ago
  40. eaa994e cache: Allow main memory to be at disjoint address ranges. by Ali Saidi · 13 years ago
  41. cda4c2d Fix the SPARC fs regression by adding a call to createInterruptController. by Gabe Black · 13 years ago
  42. eb43883 build scripts: Made minor modifications to reduce build overhead time. by Marc Orr · 13 years ago
  43. 75681d3 Stats: Update stats for changeset 8868 by Andreas Hansson · 13 years ago
  44. 3418ebb SConstruct: rename and document AddM5Option by Steve Reinhardt · 13 years ago
  45. f71a5c5 SConstruct: update comments & doc strings by Steve Reinhardt · 13 years ago
  46. fd2d5ae DynInst: get rid of dead MyHash code. by Steve Reinhardt · 13 years ago
  47. 32eae80 CPU: Check that the interrupt controller is created when needed by Andreas Hansson · 13 years ago
  48. c0b9f32 Stats: Fix the realview regression stats after nvmem move by Andreas Hansson · 13 years ago
  49. adc419a Ruby: Rename RubyPort::sendTiming to avoid overriding base class by Andreas Hansson · 13 years ago
  50. b129d7c ARM: FIx a bug preventing multiple cores booting a VExpress_EMM machine. by Ali Saidi · 13 years ago
  51. 96e37eb ARM: FIx missing cf controller connection. by Ali Saidi · 13 years ago
  52. 357fb0a VNC: spacing by Chander Sudanthi · 13 years ago
  53. 91b737e ARM: Add support for Versatile Express extended memory map by Ali Saidi · 13 years ago
  54. 3876105 ARM: Add RTC device for ARM platforms. by Ali Saidi · 13 years ago
  55. 08187e3 ARM: Add limited CP14 support. by Matt Horsnell · 13 years ago
  56. d907d0e Cache: Fix an issue with LRU when bonus block is used to complete transaction. by Ali Saidi · 13 years ago
  57. 86d1042 ARM: move kernel func event to correct location. by Dam Sunwoo · 13 years ago
  58. d51478d ARM: fix bits-to-fp conversion function declarations. by Giacomo Gabrielli · 13 years ago
  59. 4b32c9f x86: Fix x86 TLB and Walker by Nilay Vaish · 13 years ago
  60. c80af04 x86: Fix switching of CPUs by Nilay Vaish · 13 years ago
  61. e11847b Config: make option ruby available always by Nilay Vaish · 13 years ago
  62. e5ac647 MEM: Make all the port proxy members const by Andreas Hansson · 13 years ago
  63. 88abdc0 SWIG: Ensure ptrdiff_t is a known type in gcc >= 4.6.1 by Andreas Hansson · 13 years ago
  64. 13e14ba EIO: update stats (mostly order change, some renames) by Steve Reinhardt · 13 years ago
  65. 5917fb3 Make the IO bridge accept address headed to all the local APICs. by Gabe Black · 13 years ago
  66. 559b43a X86: Use the M5PanicFault fault in execute methods instead of calling panic. by Gabe Black · 13 years ago
  67. 0cd0a8f MEM: Simplify cache ports preparing for master/slave split by Andreas Hansson · 13 years ago
  68. 77878d0 MEM: Prepare mport for master/slave split by Andreas Hansson · 13 years ago
  69. 86c2aad Ruby: Simplify tester ports by not using SimpleTimingPort by Andreas Hansson · 13 years ago
  70. 485d103 MEM: Move all read/write blob functions from Port to PortProxy by Andreas Hansson · 13 years ago
  71. 9e3c8de MEM: Make port proxies use references rather than pointers by Andreas Hansson · 13 years ago
  72. 1031b82 MEM: Move port creation to the memory object(s) construction by Andreas Hansson · 13 years ago
  73. 9f07d2c CPU: Round-two unifying instr/data CPU ports across models by Andreas Hansson · 13 years ago
  74. ef4af8c MEM: Fatal when no port can be found for an address by Andreas Hansson · 13 years ago
  75. e121708 SimObject: make get_config_as_dict() tolerate undefined params by Steve Reinhardt · 13 years ago
  76. 6cf9f18 MEM: Fix residual bus ports and make them master/slave by Andreas Hansson · 13 years ago
  77. ac91f90 Script: Fix the scripts that use the num_cpus cache parameter by Andreas Hansson · 13 years ago
  78. 0097817 MEM: Fix master/slave ports in Ruby and non-regression scripts by Andreas Hansson · 13 years ago
  79. 0d46708 bp: fix up stats for changes to branch predictor by Ali Saidi · 13 years ago
  80. 9b05e96 BPred: Fix RAS to handle predicated call/return instructions. by Mrinmoy Ghosh · 13 years ago
  81. fd90c36 BP: Fix several Branch Predictor issues. by Mrinmoy Ghosh · 13 years ago
  82. abc2124 MEM: Explicit ports and Python binding on CopyEngine by Andreas Hansson · 13 years ago
  83. 63777fb MEM: Pass the ports from Python to C++ using the Swig params by Andreas Hansson · 13 years ago
  84. 5a9a743 MEM: Introduce the master/slave port roles in the Python classes by Andreas Hansson · 13 years ago
  85. 8cb4a22 tests: fix diff-out script for op/inst stat changes. by Ali Saidi · 13 years ago
  86. eada426 X86: open flags: Another patch from Vince Weaver by Gabe Black · 13 years ago
  87. 67f16a4 configs: fix minor config bugs posted on the mailing list by Ali Saidi · 13 years ago
  88. 4f8d1a4 stats: update stats for insts/ops and master id changes by Ali Saidi · 13 years ago
  89. 542d0ce cpu: add separate stats for insts/ops both globally and per cpu model by Anthony Gutierrez · 13 years ago
  90. 230540e mem: fix cache stats to use request ids correctly by Dam Sunwoo · 13 years ago
  91. 8aaa39e mem: Add a master ID to each request object. by Ali Saidi · 13 years ago
  92. 7e104a1 prefetcher: Make prefetcher a sim object instead of it being a parameter on cache by Mrinmoy Ghosh · 13 years ago
  93. b7cf643 Regressions: Update stats due to change in MESI protocol by Nilay Vaish · 13 years ago
  94. 5b557a3 SPARC: Make PSTATE and HPSTATE a BitUnion. by Gabe Black · 13 years ago
  95. aa513a4 Ruby: Remove isTagPresent() calls from Sequencer.cc by Nilay Vaish · 13 years ago
  96. 69d8600 MESI: Add queues for stalled requests by Nilay Vaish · 13 years ago
  97. 72f3f52 sim/system: initialize the pagePtr variable by Nilay Vaish · 13 years ago
  98. 26ca8b8 Regressions: Update stats due to O3 CPU changes by Nilay Vaish · 13 years ago
  99. 6a7a626 O3 CPU: Improve handling of delayed commit flag by Nilay Vaish · 13 years ago
  100. cd765c2 O3 CPU: Strengthen condition for handling interrupts by Nilay Vaish · 13 years ago