)]}' { "log": [ { "commit": "04bc162f152b4a67aad921b4965353cb73cbc820", "tree": "9784e7db9e584d6d42bab1fe2b6322e544b1ddaf", "parents": [ "740756e97736ad6b65dcb651c2f1f69cc1282781" ], "author": { "name": "Anis Peysieux", "email": "anis.peysieux@inria.fr", "time": "Tue Apr 09 16:26:53 2019 +0200" }, "committer": { "name": "Anis Peysieux", "email": "anis.peysieux@gmail.com", "time": "Thu Apr 11 15:34:46 2019 +0000" }, "message": "mem-cache: Fix RRPV for RRIP\n\nThe RRPV values for RRIP and NRU replacment policies.\nLong re-rereference interval was used instead of\ndistant re-rereference interval and vice-versa.\nThe btp value permit to choose beetwen distant and\nlong insertion ratio. A btp value of 0 force the\npolicy to always insert at a distant re-reference\ninterval and a btp value of 100 force the policy to\nalways insert at a long (intermediate) re-rereference\ninterval.\n\nChange-Id: I516098f73942b769dcc31fe0edfe07c3e9c3effd\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17851\nReviewed-by: Daniel Carvalho \u003codanrc@yahoo.com.br\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nMaintainer: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n" }, { "commit": "740756e97736ad6b65dcb651c2f1f69cc1282781", "tree": "549488f783ecd705f82883e685c27127b2a16fd6", "parents": [ "680a689fd6ca844b373bf2c5ba9028b7b563a356" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Apr 09 09:30:43 2019 +0100" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Thu Apr 11 09:01:31 2019 +0000" }, "message": "arch-arm: Enable PMSELR_EL0 read in PMU\n\nChange-Id: Ic1ec1d03464a7ce42295cee8a9f4ebcd3e90def1\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17948\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "680a689fd6ca844b373bf2c5ba9028b7b563a356", "tree": "55bf84ea5a3d1ac7712aa26c5590b7c00cfbbdca", "parents": [ "729d9949f74a2fef8ed27de83e1f918fbb8c431d" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Fri Mar 22 15:46:57 2019 -0700" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Wed Apr 10 10:39:43 2019 +0000" }, "message": "mem: Plumb backdoor requests through the xbar classes.\n\nChange-Id: Ic8f49339ab95c31d2f00edfdf23a46f1271ec3aa\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17593\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-by: Daniel Carvalho \u003codanrc@yahoo.com.br\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "729d9949f74a2fef8ed27de83e1f918fbb8c431d", "tree": "bc4eb13404f3456e70c8daebd2ad09e0e860d20f", "parents": [ "64f415f9bf5bb70376859055ec2d96fbb8c998ce" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Thu Mar 21 17:28:26 2019 -0700" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Wed Apr 10 10:37:58 2019 +0000" }, "message": "systemc: Teach the TLM bridges how to use gem5\u0027s new backdoor mechanism.\n\nThis change teaches the TLM bridges to translate between TLM\u0027s DMI\nmechanism and gem5\u0027s backdoor mechanism.\n\nChange-Id: I942a6cce4fb87f10e8173f4ee49b6c7b0ffa7e4a\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17591\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "64f415f9bf5bb70376859055ec2d96fbb8c998ce", "tree": "caa8de425655fa20f717d6a796a31da3d98704ca", "parents": [ "a8d5dd1c136529e9605066368877d3b8e24dcdba" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Thu Mar 21 17:23:03 2019 -0700" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Wed Apr 10 10:37:27 2019 +0000" }, "message": "mem: Add sendAtomicBackdoor/recvAtomicBackdoor port methods.\n\nThese both perform atomic accesses like their non-backdoor equivalents,\nand also request a backdoor corresponding to the access.\n\nThe default implementation for recvAtomicBackdoor prints a warning\n(once per port instance), calls recvAtomic to do the actual access,\nand leaves the backdoor pointer as nullptr. That way if an object\ndoesn\u0027t know how to handle or transfer requests for a back door, it\nautomatically replies in a safe way that ignores the back door request.\n\nChange-Id: Ia9fbbe9996eb4b71ea62214d203aa039a05f1618\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17590\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-by: Daniel Carvalho \u003codanrc@yahoo.com.br\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "a8d5dd1c136529e9605066368877d3b8e24dcdba", "tree": "ccf4979676d9a1c0d82689a1dc9757a83c229ed0", "parents": [ "daa9dcbc0c3fe4e5014855c8b31f1cfeb5f0af91" ], "author": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Tue Feb 12 08:26:14 2019 +0000" }, "committer": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Wed Apr 10 09:05:02 2019 +0000" }, "message": "mem-cache: Fix MSHR handling of cache clean requests\n\nPreviously satisfied clean requests would not snoop in-service\nMSHRs. This is a problem when a clean request is also invalidating, in\nwhich case we have to post-invalidate or post-downgrade outstanding\nrequests. This changes fixes this bug.\n\nChange-Id: I31e42aa94dd3637b2818e00fbaae68c810145eaf\nSigned-off-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17728\nReviewed-by: Daniel Carvalho \u003codanrc@yahoo.com.br\u003e\n" }, { "commit": "daa9dcbc0c3fe4e5014855c8b31f1cfeb5f0af91", "tree": "65b0e6feced44355aa991fa47ab892a1d5e2f50f", "parents": [ "7f9c98472c97f8f71f71c7386496af67fc886d03" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Fri Mar 29 13:02:05 2019 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed Apr 10 08:41:53 2019 +0000" }, "message": "cpu: O3 switchFreeList checking VecElems instead of FloatRegs\n\nVector elements should be checked instead of floats since those are the\nones mapped to the vector registers.\n\nChange-Id: I36088ab90e63720d846fcf5b43360da105b6c736\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17850\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Jason Lowe-Power \u003cjason@lowepower.com\u003e\n" }, { "commit": "7f9c98472c97f8f71f71c7386496af67fc886d03", "tree": "cce0efd8ddd742f6346a5781f36340009f1b989e", "parents": [ "c1e646d886096ffeca7d9818316ba5e03391898a" ], "author": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Fri Apr 05 10:43:59 2019 -0700" }, "committer": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Mon Apr 08 22:51:38 2019 +0000" }, "message": "learning_gem5,configs: Update ruby_test\n\nUse SimpleMemory instead of DDR3 so we can use the timing results in\ntests. By using SimpleMemory, even if the DRAM timing changes the timing\nof this test won\u0027t change. I expect the timing of SimpleMemory to never\nchange.\n\nChange-Id: I4c75981d7b8bfc4dcca59e628e89f5a6ea4c0e36\nSigned-off-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17871\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-by: Anthony Gutierrez \u003canthony.gutierrez@amd.com\u003e\n" }, { "commit": "c1e646d886096ffeca7d9818316ba5e03391898a", "tree": "fc6791eee24d6f07dbbdd04cc622eabf108c0d50", "parents": [ "36bce3927e589dab1e4b446b75f2cff78cf1f531" ], "author": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Fri Apr 05 10:29:54 2019 -0700" }, "committer": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Mon Apr 08 22:51:38 2019 +0000" }, "message": "learning_gem5: Fix vector port panic in SimpleCache\n\nChange-Id: I0f3b71fdbed77690c533d9d14e774ab2cc08c053\nSigned-off-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17870\nReviewed-by: Anthony Gutierrez \u003canthony.gutierrez@amd.com\u003e\n" }, { "commit": "36bce3927e589dab1e4b446b75f2cff78cf1f531", "tree": "c0cbaa7aa9a5d3c9398c81053073b5091d2d316d", "parents": [ "6bcd13fcc4d0c5eb3c7ced0ce6bc827e193415eb" ], "author": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Thu Apr 04 18:36:42 2019 -0700" }, "committer": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Mon Apr 08 22:51:38 2019 +0000" }, "message": "configs: Fix import path error in learning_gem5 part3\n\nChange-Id: I2c5cd22bded998bae8e7aa77e42e1b042ce1c5f5\nSigned-off-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17869\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-by: Anthony Gutierrez \u003canthony.gutierrez@amd.com\u003e\n" }, { "commit": "6bcd13fcc4d0c5eb3c7ced0ce6bc827e193415eb", "tree": "5c75fefd7b6a9d4cca55cb275d777e6548f9ef65", "parents": [ "ca687eaab3f7117c9e2986e81afeaaee12cbcc63" ], "author": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Thu Apr 04 18:36:23 2019 -0700" }, "committer": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Mon Apr 08 22:51:38 2019 +0000" }, "message": "configs: Add full path for learning_gem5 binaries\n\nChange-Id: Ie48429d65e322136109a223ed404937989aae494\nSigned-off-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17868\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-by: Anthony Gutierrez \u003canthony.gutierrez@amd.com\u003e\n" }, { "commit": "ca687eaab3f7117c9e2986e81afeaaee12cbcc63", "tree": "c945d9f80fad132d4309505fbc019397e84ae729", "parents": [ "2cf18a811044e5a67ff4a4f9d1c419b5673a698e" ], "author": { "name": "Ryan Gambord", "email": "gambordr@oregonstate.edu", "time": "Sat Apr 06 23:37:24 2019 -0700" }, "committer": { "name": "Ryan Gambord", "email": "gambordr@oregonstate.edu", "time": "Mon Apr 08 08:25:26 2019 +0000" }, "message": "configs: Removed redudant exec-style import\n\ngarnet_synth_traffic.py imports common.Options on line 40, so exec\u0027ing\nthe Options.py file again seems redundant.\n\nIt also runs Options.py as a script rather than a module, which throws\nValueError: Attempted relative import in non-package due to the recent\nchange to python3 imports.\n\nChange-Id: Id729a8dfa776af0d14312e765168aff6900eb727\nSigned-off-by: Ryan Gambord \u003cgambordr@oregonstate.edu\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17888\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "2cf18a811044e5a67ff4a4f9d1c419b5673a698e", "tree": "36edc8de0d760e5b1d32a4b400f42ced5d0b38ad", "parents": [ "d0f87650e105395b6fa281c19b47eb705129372c" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Thu Mar 21 17:12:08 2019 -0700" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Sat Apr 06 00:52:15 2019 +0000" }, "message": "mem: Add a MemBackdoor type to track memory backdoors.\n\nThese are similar to the structures TLM\u0027s DMI mechanism uses. Instead\nof having an invalidation broadcast which propogates backwards up the\nport hierarchy, this mechanism tracks a set of callbacks which are\ntriggered when a back door is invalidated to let other holders clean\nup their bookkeeping.\n\nChange-Id: If24489258dcaee14d7b6e5b996dfb1c2636f26ab\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17589\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "d0f87650e105395b6fa281c19b47eb705129372c", "tree": "847fed4eafdc654c91a88be926b9073fcaa5b5e0", "parents": [ "271f2aea84a280b68c234a57438b94629f254e7f" ], "author": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Thu Feb 28 17:55:41 2019 +0000" }, "committer": { "name": "Nikos Nikoleris", "email": "nikos.nikoleris@arm.com", "time": "Fri Apr 05 21:52:19 2019 +0000" }, "message": "cpu: Correctly account for executed instructions in simple cpus\n\nChange-Id: I53f34b2d9db6e4d2e03dde42a970764bb2a5e701\nSigned-off-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17730\nReviewed-by: Anthony Gutierrez \u003canthony.gutierrez@amd.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "271f2aea84a280b68c234a57438b94629f254e7f", "tree": "afede1e2f1e1fdc54e060fb636ad25c0227f1f04", "parents": [ "529d0cdbfe77a4ad655fe57f2d5320dbb760ef13" ], "author": { "name": "Ryan Gambord", "email": "gambordr@oregonstate.edu", "time": "Thu Apr 04 12:25:07 2019 -0400" }, "committer": { "name": "Ryan Gambord", "email": "gambordr@oregonstate.edu", "time": "Fri Apr 05 18:10:04 2019 +0000" }, "message": "mem-cache: ambiguous use of abs function\n\nstd::abs doesn\u0027t accept unsigned long long, generating the error:\n\nerror: call to \u0027abs\u0027 is ambiguous\n\nUse instead a compare-and-subtract idiom.\n\nAlso, Changed return type of distanceFromTrigger from unsigned int to Addr to\nprevent overflow problems.\n\nChange-Id: Ia7752c1c7a838f98e8c7ed6ade9f586f31bbcf7d\nSigned-off-by: Ryan Gambord \u003cgambordr@oregonstate.edu\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17788\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n" }, { "commit": "529d0cdbfe77a4ad655fe57f2d5320dbb760ef13", "tree": "8c2433849ffe84bf3278140ea9a260e74ace202e", "parents": [ "07eca72e1a51910e8ff785c224bf3820183d3664" ], "author": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Thu Apr 04 14:10:16 2019 -0700" }, "committer": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Fri Apr 05 17:36:37 2019 +0000" }, "message": "mem: Reverse order of write/read mem queue check\n\nFor atomic RMW instructions that go directly to memory, we want to put\nthem on the write queue instead of the read queue. Swap the if/else\ncondition to accomplish this.\n\nNote: This is ignoring the read latency of the RMW, but these\ninstructions should usually be handled in caches anyway.\n\nChange-Id: I62dbfff3a16ac470f1ebdb489abe878962b20bb6\nSigned-off-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17828\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n" }, { "commit": "07eca72e1a51910e8ff785c224bf3820183d3664", "tree": "a74ee072041bcdd7d8e881272c8935694d9f4f14", "parents": [ "c2c1a976ee76cf3064045a21187ca985ca88a347" ], "author": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Mon Dec 03 11:19:37 2018 -0800" }, "committer": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Fri Apr 05 15:55:05 2019 +0000" }, "message": "tests: Add Jenkins presubmit and continuous test scripts\n\nNote that continuous currently isn\u0027t used.\n\nChange-Id: Ifcff88c8c4c75a9f630b97eaca22edd1681529c3\nSigned-off-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17456\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\n" }, { "commit": "c2c1a976ee76cf3064045a21187ca985ca88a347", "tree": "25e59c1f60fb26338a515a37afbcd21e3dc6eb8f", "parents": [ "e13d6dc9c0d7a4ae0215f1ee6793eb32570c5169" ], "author": { "name": "Javier Bueno", "email": "javier.bueno@metempsy.com", "time": "Tue Apr 02 23:34:20 2019 +0200" }, "committer": { "name": "Javier Bueno Hedo", "email": "javier.bueno@metempsy.com", "time": "Thu Apr 04 12:13:14 2019 +0000" }, "message": "mem-cache: AMPM Prefetcher fails when restoring from a checkpoint\n\nThe preriodic event triggers an assertion due to an incorrect tick value to\nschedule when restoring from a checkpoint.\n\nChange-Id: I9454dd0c97d5a098f8a409886e63f7a7e990947c\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17732\nReviewed-by: Daniel Carvalho \u003codanrc@yahoo.com.br\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n" }, { "commit": "e13d6dc9c0d7a4ae0215f1ee6793eb32570c5169", "tree": "460b5ce101d25d9251137506777c3394f8dd805b", "parents": [ "5084b90e2af6e5bfad3119b4431a3b063ef3b799" ], "author": { "name": "Andrea Mondelli", "email": "Andrea.Mondelli@ucf.edu", "time": "Wed Mar 06 10:50:48 2019 -0500" }, "committer": { "name": "Andrea Mondelli", "email": "Andrea.Mondelli@ucf.edu", "time": "Wed Apr 03 16:50:22 2019 +0000" }, "message": "misc: Removed inconsistency in O3* debug msgs\n\nAdded consistency in the DEBUG message form, to allow a better parsing.\nFixed sn/tid type parameter.\nRemoved some annoying newlines\n\nChange-Id: I4761c49fc12b874a7d8b46779475b606865cad4b\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17248\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Jason Lowe-Power \u003cjason@lowepower.com\u003e\n" }, { "commit": "5084b90e2af6e5bfad3119b4431a3b063ef3b799", "tree": "fa013c4f0e55cc67ed8746d72173619230fb1b99", "parents": [ "5caa4517345d4833af44e510f78717ee7e0ad8d4" ], "author": { "name": "Andrea Mondelli", "email": "Andrea.Mondelli@ucf.edu", "time": "Mon Mar 25 12:41:54 2019 -0400" }, "committer": { "name": "Andrea Mondelli", "email": "Andrea.Mondelli@ucf.edu", "time": "Wed Apr 03 16:48:55 2019 +0000" }, "message": "arch-mips: added missing override specifier (o3)\n\nChange-Id: Ic538825a2964fd62def672b933a83067a15bd12a\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17648\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Jason Lowe-Power \u003cjason@lowepower.com\u003e\n" }, { "commit": "5caa4517345d4833af44e510f78717ee7e0ad8d4", "tree": "78a26c95e2516f30d9b18b0f5d1a7c6b36e3c98c", "parents": [ "f662b8aaacba60632e69da11cf7fc0deba958604" ], "author": { "name": "Javier Bueno", "email": "javier.bueno@metempsy.com", "time": "Tue Apr 02 23:29:42 2019 +0200" }, "committer": { "name": "Javier Bueno Hedo", "email": "javier.bueno@metempsy.com", "time": "Wed Apr 03 09:20:28 2019 +0000" }, "message": "mem-cache: Fix PIF prefetcher compilation error with NULL ISA\n\nReferencing BaseCPU is causing a compilation error when using the NULL ISA.\nThis patch changes the reference to a SimObject, which fixes the problem.\n\nChange-Id: I2530486cab65974f5b83e54a733c4b0e98730d26\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17731\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n" }, { "commit": "f662b8aaacba60632e69da11cf7fc0deba958604", "tree": "a67d5192ea21acc8e6f4afa7f686f9b289acb816", "parents": [ "06b305bb342ac02b22b77050324864b3217e7482" ], "author": { "name": "Javier Bueno", "email": "javier.bueno@metempsy.com", "time": "Tue Apr 02 23:43:28 2019 +0200" }, "committer": { "name": "Javier Bueno Hedo", "email": "javier.bueno@metempsy.com", "time": "Wed Apr 03 09:14:22 2019 +0000" }, "message": "mem-cache: ISB prefetcher was triggering an assertion\n\nAn assertion ignored the case when an entry of the SP table had been invalidated.\n\nChange-Id: I5bf04e7a0979300b0f41f680c371f6397d4cbf3f\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17734\nReviewed-by: Daniel Carvalho \u003codanrc@yahoo.com.br\u003e\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n" }, { "commit": "06b305bb342ac02b22b77050324864b3217e7482", "tree": "f6b6a397dd52856d906686124e253824c1615015", "parents": [ "e7a1636889dec63a65723dc4df71d1970b013116" ], "author": { "name": "Javier Bueno", "email": "javier.bueno@metempsy.com", "time": "Tue Apr 02 23:39:06 2019 +0200" }, "committer": { "name": "Javier Bueno Hedo", "email": "javier.bueno@metempsy.com", "time": "Wed Apr 03 09:14:04 2019 +0000" }, "message": "mem-cache: Fix panic in Indirect Memory prefetcher\n\nMemory requests with a size non-power-of-two and less than 8 values were causing\na panic, but there these should be allowed and ignored by the prefetcher.\n\nChange-Id: I86baa60058cc8a7f232d6ba5748d4c24a463c840\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17733\nReviewed-by: Daniel Carvalho \u003codanrc@yahoo.com.br\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n" }, { "commit": "e7a1636889dec63a65723dc4df71d1970b013116", "tree": "3022c888d5365ae83faf64468264bb015e47f48b", "parents": [ "4628d87e3abbcad0c5a95b6a4562b8ac8c6f4661" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Mon Feb 18 14:33:36 2019 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Apr 02 16:20:54 2019 +0000" }, "message": "dev-arm: Make GICv3 maintenance interrupt an ArmInterrupt\n\nChange-Id: I88e2b72849cdf3f69026c62517303837e7d3d551\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Anouk Van Laer \u003canouk.vanlaer@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17629\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "4628d87e3abbcad0c5a95b6a4562b8ac8c6f4661", "tree": "bfc48023ee80f5b42b516e1c03cfb22e8e327706", "parents": [ "283e092eda0b739a3c28bfa6293822e57ca67db6" ], "author": { "name": "Ivan Pizarro", "email": "ivan.pizarro@metempsy.com", "time": "Mon Feb 25 14:30:55 2019 +0100" }, "committer": { "name": "Javier Bueno Hedo", "email": "javier.bueno@metempsy.com", "time": "Tue Apr 02 10:38:39 2019 +0000" }, "message": "mem-cache: Proactive Instruction Fetch Implementation\n\nFerdman, M., Kaynak, C., \u0026 Falsafi, B. (2011, December).\nProactive instruction fetch. In Proceedings of the 44th Annual IEEE/ACM\nInternational Symposium on Microarchitecture (pp. 152-162). ACM.\n\nChange-Id: I38c3ab30a94ab279f03e3d5936ce8ed118310c0e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16968\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-by: Daniel Carvalho \u003codanrc@yahoo.com.br\u003e\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n" }, { "commit": "283e092eda0b739a3c28bfa6293822e57ca67db6", "tree": "ba58ed333e5a365e76518aad47a2568d5409d070", "parents": [ "2a98a994df296f818b05da90ba073d879562da04" ], "author": { "name": "Andrea Mondelli", "email": "Andrea.Mondelli@ucf.edu", "time": "Thu Mar 14 18:20:54 2019 -0400" }, "committer": { "name": "Andrea Mondelli", "email": "Andrea.Mondelli@ucf.edu", "time": "Mon Apr 01 15:55:58 2019 +0000" }, "message": "dev-arm: Correct cast of template parameter\n\nClang with -Wconstant-conversion is _very_ restrictive on casting.\nThe shift operator results in an incorrect promotion.\n\nThis patch add a compile-time static cast that remove the error\nwhen clang is used.\n\nChange-Id: I3aa1e77da2565799feadc32317d5faa111b2de86\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17308\nReviewed-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "2a98a994df296f818b05da90ba073d879562da04", "tree": "18d0f98c27c157e1d1f9884031d1ff22f10e0fca", "parents": [ "b2efb725921c9387852f439ad20964c428072dd7" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Thu Mar 14 05:33:51 2019 -0700" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Fri Mar 29 22:46:00 2019 +0000" }, "message": "systemc: Templatize the gem5/TLM bridge SimObjects.\n\nThe C++ side is templated, and there are python versions for each\n(currently two) width of bridge supported.\n\nChange-Id: I4baa9f22d4c87629d45e9e1292eb66c65d25a655\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17234\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "b2efb725921c9387852f439ad20964c428072dd7", "tree": "09ddb0c6ca3649044502bf16975a32b4b512e4d2", "parents": [ "e65a89e39b1c86e002e28a515508f5302a91a58f" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Mon Mar 11 21:27:17 2019 -0700" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Fri Mar 29 22:45:09 2019 +0000" }, "message": "systemc: Delete extra code from src/systemc/tlm_bridge.\n\nMuch of the code in src/systemc/tlm_bridge has been absorbed into the\nTLM/gem5 bridge SimObjects and is no longer needed and redundant with\nthe original version in util/.\n\nChange-Id: I0fa7af67649987cf9f6fc5cd4783002dde2242ac\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17233\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "e65a89e39b1c86e002e28a515508f5302a91a58f", "tree": "357426716a6ed865287f68f683b5991026237bb3", "parents": [ "9a042daa84630d2d0d286947005e96448fb5114a" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Mon Mar 11 16:02:26 2019 -0700" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Fri Mar 29 22:44:29 2019 +0000" }, "message": "systemc: Create unified gem5/TLM bridge SimObjects.\n\nThese objects expose a standard TLM initiator or target socket with\nwidth 64, and a gem5 slave or master port. What goes in one type of\nport comes out the other with the appropriate conversion applied.\n\nChange-Id: I65e07f746d46d3db0197968b78fffc5ddaede9bf\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17232\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "9a042daa84630d2d0d286947005e96448fb5114a", "tree": "b67935085512ab406a30d583d8441b3ac0d5118e", "parents": [ "87c4a97650897fc98a673b02462261202f01d711" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Mon Feb 25 20:27:06 2019 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Fri Mar 29 22:43:42 2019 +0000" }, "message": "tlm: Initial import of tlm/gem5 bridge code.\n\nThis is a slightly mangled version of the existing bridge code in\nutil/tlm/src/. The changes fix some small style issues, change to gem5\nspecific include paths, and removes the Gem5SimControl code. That code\ncoordinates gem5 with the external systemc kernel, and in this usage\nthere\u0027s no external kernel.\n\nThe code imported here compiles, but it isn\u0027t yet expected to work.\n\nChange-Id: I9c593a52e2554534720d21cd31a03e543ad897ad\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17231\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "87c4a97650897fc98a673b02462261202f01d711", "tree": "18016f1a9fb115474eb9507ef6d07fd64e00ac6c", "parents": [ "1a27580e3bb113a0eca64a5075a00e45cc9cdd0d" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Tue Mar 12 17:16:23 2019 -0700" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Fri Mar 29 22:43:06 2019 +0000" }, "message": "systemc: Provide a utility Port TLM socket wrapper class.\n\nThis class should make it easy to attach TLM sockets into the gem5\npython Port config mechanism.\n\nChange-Id: I3548c654d56bfc852f3fc98fe6433163b14f7fe3\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17230\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "1a27580e3bb113a0eca64a5075a00e45cc9cdd0d", "tree": "301d84dbed9fe9ddeecd3feeb5d567fc7dd318eb", "parents": [ "cbaae5478224beafea921005b102caa18ddb4606" ], "author": { "name": "Javier Bueno", "email": "javier.bueno@metempsy.com", "time": "Tue Mar 26 23:12:00 2019 +0100" }, "committer": { "name": "Javier Bueno Hedo", "email": "javier.bueno@metempsy.com", "time": "Thu Mar 28 20:57:22 2019 +0000" }, "message": "cpu: Added a probe to notify the address of retired instructions\n\nA probe is added to notify the address of each retired instruction.\n\nChange-Id: Iefc1b09d74b3aa0aa5773b17ba637bf51f5a59c9\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17632\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "cbaae5478224beafea921005b102caa18ddb4606", "tree": "e86efe76a3761168818fc2aab8637596c74be280", "parents": [ "a93fe3f3cf2b2ad7b0c5b9916bc705a579ca231c" ], "author": { "name": "Daniel R. Carvalho", "email": "odanrc@yahoo.com.br", "time": "Wed Mar 27 16:38:07 2019 +0100" }, "committer": { "name": "Daniel Carvalho", "email": "odanrc@yahoo.com.br", "time": "Thu Mar 28 11:56:53 2019 +0000" }, "message": "mem-cache: Remove extra cache header from AMAP\n\nThe cache header was being included in the AMAP, although not\nused, which resulted in slightly longer compilation time.\n\nChange-Id: I3654bc719c6b5f558af116addae159301602a3cf\nSigned-off-by: Daniel R. Carvalho \u003codanrc@yahoo.com.br\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17711\nReviewed-by: Javier Bueno Hedo \u003cjavier.bueno@metempsy.com\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n" }, { "commit": "a93fe3f3cf2b2ad7b0c5b9916bc705a579ca231c", "tree": "3b395f98c47f59dbad26bb0aaafe26ef07d7d55b", "parents": [ "93ad0d4324acd674f1877a1146c58412a03b4c39" ], "author": { "name": "Javier Setoain", "email": "javier.setoain@arm.com", "time": "Thu Mar 14 17:42:44 2019 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Thu Mar 28 10:28:11 2019 +0000" }, "message": "arch-arm: Fix use of bitwise operators on booleans\n\nChange-Id: I3762b2921f1d00a9104d8dc11a19dc0a219581e5\nReviewed-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17288\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "93ad0d4324acd674f1877a1146c58412a03b4c39", "tree": "85bd54efc30f0a1f4e09945ea6d8474a72652e72", "parents": [ "631bfb6d257ed849270400cc7f6a39afdb732dff" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Mar 26 18:02:11 2019 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Thu Mar 28 09:34:21 2019 +0000" }, "message": "arch-arm: Fix index generation for VecElem operands\n\nCurrent operand generation is not providing VecElems with the right\nvector index and element index.\nThe bug was covered when registers were 128 bit wide, but with SVE we\nhave augmented the vector register size and the bug has been exposed.\n\nE.g. With dest \u003d 2,\n\nFpDestP2 \u003d (vec_index \u003d 0, elem_index \u003d 4)\n\nwhereas it should be\n\nFpDestP2 \u003d (vec_index \u003d 1, elem_index \u003d 0)\n\nChange-Id: Iad02fb477afd0d3dd3d437bf2ca4338fbd142107\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Ciro Santilli \u003cciro.santilli@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17710\n" }, { "commit": "631bfb6d257ed849270400cc7f6a39afdb732dff", "tree": "5a3f25a5bacb2e1cd58b68d93bdb9d56abeab1f1", "parents": [ "e8a6811ad6105605d1932627c3737fe9b645f8d0" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Mon Feb 18 14:15:41 2019 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed Mar 27 15:20:47 2019 +0000" }, "message": "dev-arm: Rename GIC maintenance interrupt from ppint to maint_int\n\nppint is a generic name which only reflects Arm recommendation of\nassigning the maintanance interrupt to a PPI (numbered 25)\n\nChange-Id: Ic5abb6ed50817ad2d165b5df46dd989eb195a9db\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Anouk Van Laer \u003canouk.vanlaer@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17628\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "e8a6811ad6105605d1932627c3737fe9b645f8d0", "tree": "7b331a8e15960259d9c00164a1c9b0702eb47715", "parents": [ "e36839e7780df11065ab0a08abaf3fcf68135aa7" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Fri Mar 08 11:06:21 2019 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed Mar 27 13:29:26 2019 +0000" }, "message": "dev-arm: Fix GICv3 overflow for INTID \u003e 256\n\nSPIs can get to a maximum number of 1023, so that an uint8_t is not capable\nof representing all of them.\n\nChange-Id: I7a2c43b41ac93eabdfcf8311681240416b954177\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Ciro Santilli \u003cciro.santilli@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17631\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "e36839e7780df11065ab0a08abaf3fcf68135aa7", "tree": "99b2cc04c0407bb48789f070a454662ec757a943", "parents": [ "9059aafbd3157f515d23b7ba5e89a2d1a8cfd41a" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Fri Mar 08 10:47:02 2019 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Wed Mar 27 13:29:10 2019 +0000" }, "message": "dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI (or RES0)\n\nFor SGIs and PPIs:\n* When ARE is 1 (only value supported in gem5) for the Security state of\nan interrupt, the field for that interrupt is RES0 and an implementation\nis permitted to make the field RAZ/WI in this case.\n\nChange-Id: I6da2a89b1c848d458f42540e0113e7139b910abb\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Ciro Santilli \u003cciro.santilli@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17630\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "9059aafbd3157f515d23b7ba5e89a2d1a8cfd41a", "tree": "768a8c785fb1a37a1984f3001a01ce2141a97f73", "parents": [ "78f1f4d8f9267b5345f5a34f113eabae2a2faac9" ], "author": { "name": "Javier Bueno", "email": "javier.bueno@metempsy.com", "time": "Wed Mar 27 12:35:54 2019 +0100" }, "committer": { "name": "Javier Bueno Hedo", "email": "javier.bueno@metempsy.com", "time": "Wed Mar 27 12:49:31 2019 +0000" }, "message": "config: Use the corresponding HPI Caches when using the HPI cpu\n\nThe HPI cpu comes with specific cache definitions, but they\nare ignored when using this cpu. This patch solves this in the same\nway it is done for the O3_ARM_v7a cpu.\n\nChange-Id: Iabf763291099d9508e3c5eac00b1e233cb38ce6b\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17708\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "78f1f4d8f9267b5345f5a34f113eabae2a2faac9", "tree": "938372c3ef5540642f4c6076c58ff3925ce7d7b3", "parents": [ "4fc7dfb7fbcf124461adc9df382695418a2b9dda" ], "author": { "name": "Pau Cabre", "email": "pau.cabre@metempsy.com", "time": "Fri Mar 01 17:32:16 2019 +0100" }, "committer": { "name": "Jairo Balart", "email": "jairo.balart@metempsy.com", "time": "Wed Mar 27 09:55:09 2019 +0000" }, "message": "cpu: Fixed the indirect branch predictor GHR handling\n\nThe internal indirect predictor global history was not being updated\nproperly, resulting in higher than expected miss rates\n\nAlso added a parameter to set the size of the indirect predictor GHR\n\nChange-Id: Ibc797816974cba6719da65122801e8919559a003\nSigned-off-by: Pau Cabre \u003cpau.cabre@metempsy.com\u003e\nReported-by: Daniel Carvalho \u003codanrc@yahoo.com.br\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16928\nReviewed-by: Daniel Carvalho \u003codanrc@yahoo.com.br\u003e\nReviewed-by: Andrea Mondelli \u003cAndrea.Mondelli@ucf.edu\u003e\nReviewed-by: Sudhanshu Jha \u003csudhanshu.jha@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "4fc7dfb7fbcf124461adc9df382695418a2b9dda", "tree": "7ffd87276cdc696996c32ea88971b802c79f3ca3", "parents": [ "599d2c91f88ba74098a917eb0b7f901add49276a" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Tue Mar 26 11:29:28 2019 -0700" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Tue Mar 26 18:31:59 2019 +0000" }, "message": "mem: Deleting this init() method was accidentally dropped during rebase.\n\nDeleting this init() method was part of a change just committed, but\nwas accidentally dropped during a rebase.\n\nChange-Id: I0f22778596ed11e182f3111d9999a0fef727f6cc\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17688\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "599d2c91f88ba74098a917eb0b7f901add49276a", "tree": "7018c702b25b008893d97959aa7ead613f2d6462", "parents": [ "fcc4c4fed945d0575d40fe314573a2081d66b2ee" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Fri Mar 22 14:23:21 2019 -0700" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Tue Mar 26 18:17:09 2019 +0000" }, "message": "mem: Clean up the xbars a little.\n\nGet rid of comments which just restate the code, get rid of redundant\n\"virtual\" keywords, add \"override\"s, fix style, and get rid of\nxbar::init which was empty and hiding the parent class init.\n\nChange-Id: I8ce20abee340baa88084d142f2fb8c633ee54ba9\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17592\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "fcc4c4fed945d0575d40fe314573a2081d66b2ee", "tree": "9dc92db64b915c50d969a8db865e7e03c2ef92ce", "parents": [ "c67d89f38287fa90631e41cf1cd85e422e8661ac" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Thu Mar 21 17:07:58 2019 -0700" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Tue Mar 26 18:11:06 2019 +0000" }, "message": "base: Make AddrRangeMap able to return non-const iterators.\n\nThe erase() method only accepts regular iterators which is consistent\nwith the normal STL map, but the existing find() only returns const\niterators. The STL container can return either depending on if \"this\"\nis const.\n\nUnfortunately there isn\u0027t a great way to have only one find\nimplementation which returns the right type of iterator under the right\nconditions. Also, it\u0027s not possible to turn a const_iterator into an\niterator, but it is possible to go the other way. This change\nduplicates very short functions which return iterators, and for find\ndoes the only thing I could find which avoids having to copy that\nwhole large function.\n\nChange-Id: I2f789b5d0881feb9adff9978bd40e31731c6a688\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17588\nReviewed-by: Daniel Carvalho \u003codanrc@yahoo.com.br\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "c67d89f38287fa90631e41cf1cd85e422e8661ac", "tree": "f06ca62183e7a7b3e40f1ca996b88d8d4d1d412b", "parents": [ "61f0e7e2676a54579cf104a385e0f6fa97266e4b" ], "author": { "name": "Javier Bueno", "email": "javier.bueno@metempsy.com", "time": "Sat Mar 23 23:02:44 2019 +0100" }, "committer": { "name": "Javier Bueno Hedo", "email": "javier.bueno@metempsy.com", "time": "Tue Mar 26 13:03:15 2019 +0000" }, "message": "configs: fix class reference in CacheConfigs\n\nOne reference was not properly updated when changing to absolute import paths\n\nChange-Id: Idf330487d5d08d92ebb4489f16d75429f882bd7a\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17541\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "61f0e7e2676a54579cf104a385e0f6fa97266e4b", "tree": "2a2ff4532756ac45b338f08933806017e439c18d", "parents": [ "ca4c0a168ae3a48fe97f0c132fefbf606d925bb8" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Mon Feb 25 17:05:09 2019 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Tue Mar 26 12:53:44 2019 +0000" }, "message": "dev-arm: Set/Unset dma coherent mode from python\n\nWith this patch it will be possible to automatically enable/disable the\ndma-coherent property for the GenericArmPciHost autogenerated DTB. This\nhas been done by adding the _dma_coherent param.\n\nChange-Id: I1759fced74e42410462637ca77997a351314a90a\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16748\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "ca4c0a168ae3a48fe97f0c132fefbf606d925bb8", "tree": "b321f70aa9285ed1f55a6eee5a0bea3facb7c49b", "parents": [ "149c1fc2d070a8ce073263880ecf2ccf7535e569" ], "author": { "name": "Isaac Sánchez Barrera", "email": "isaac.sanchez@bsc.es", "time": "Wed Mar 20 14:32:22 2019 +0100" }, "committer": { "name": "Isaac Sánchez Barrera", "email": "isaac.sanchez@bsc.es", "time": "Tue Mar 26 07:25:11 2019 +0000" }, "message": "base,python: Fix to allow multiple --debug-ignore values.\n\nWhen adding multiple SimObjects to --debug-ignore, either separating the values with\na colon or adding multiple --debug-ignore flags, the previous code only ignored the\nlast SimObject in the list. This changeset adds and uses new `ObjectMatch::add` and\n`Logger::addIgnore` methods to make the functionality of the flag consistent with\nits description.\n\nChange-Id: Ib6967a48611ea59a211f81af2a970c4de429b1be\nSigned-off-by: Isaac Sánchez Barrera \u003cisaac.sanchez@bsc.es\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17488\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "149c1fc2d070a8ce073263880ecf2ccf7535e569", "tree": "ef2cc79cee9c9d05e5b7f3c6b208c4d97d13cb88", "parents": [ "8e1a1418188b96ad5f6b27ab82aa463fc95f4179" ], "author": { "name": "Daniel R. Carvalho", "email": "odanrc@yahoo.com.br", "time": "Thu Jul 26 12:07:07 2018 +0200" }, "committer": { "name": "Daniel Carvalho", "email": "odanrc@yahoo.com.br", "time": "Mon Mar 25 12:11:51 2019 +0000" }, "message": "configs: Remove default kernel value from system creation\n\nKernel was being set using a placeholder and then assigned the\ncorrect value. This would generate the following error if the\nplaceholder file did not exist:\n\u0027IOError: Can\u0027t find file \u003cplaceholder\u003e on path\u0027\n\nThis patch follows the same directions of commit\n12eca7ac04ae1ba559bf322b5c625513929d369d and removes the default\nvalues, forcing the user to properly configure the kernel.\n\nChange-Id: I0eb45d12eda6b6efe9a3fe118996b640844a7b34\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11850\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "8e1a1418188b96ad5f6b27ab82aa463fc95f4179", "tree": "2fef7d24229e7c2ccea61ed13243237369a1b2bb", "parents": [ "f838a332be4b98ddc039f388bef1e307567db37c" ], "author": { "name": "Javier Setoain", "email": "javier.setoain@arm.com", "time": "Thu Mar 14 18:06:05 2019 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Mon Mar 25 09:40:46 2019 +0000" }, "message": "arch-arm: Add missing fall-through defaults\n\nChange-Id: Ie64b83d754c4719a77c7788879be71304a9b786e\nReviewed-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17289\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-by: Andrea Mondelli \u003cAndrea.Mondelli@ucf.edu\u003e\nMaintainer: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\n" }, { "commit": "f838a332be4b98ddc039f388bef1e307567db37c", "tree": "4b7dbad0f251304141c3592b943003722ee4287a", "parents": [ "4847330db3a12d08c9fe9fbfab052ff61e3365b6" ], "author": { "name": "Sandipan Das", "email": "sandipan@linux.ibm.com", "time": "Wed Jan 30 20:18:49 2019 +0530" }, "committer": { "name": "Sandipan Das", "email": "sandipan@linux.ibm.com", "time": "Mon Mar 25 04:48:58 2019 +0000" }, "message": "arch-power: Rename program counter registers\n\nThe Power ISA specification lists the Program Counter (PC) and\nthe Next Program Counter (NPC) registers as Current Instruction\nAddress (CIA) and Next Instruction Address (NIA). This applies\nthe ISA naming convention for these two registers.\n\nChange-Id: I8b9094ab1c809f4dfdb4d7330c17f360adf063e9\nSigned-off-by: Sandipan Das \u003csandipan@linux.ibm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16603\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "4847330db3a12d08c9fe9fbfab052ff61e3365b6", "tree": "179254f4551ef03694d0691f21795b2bbaa35931", "parents": [ "4effe34f94b599add133357473e1b120b54719ab" ], "author": { "name": "Sandipan Das", "email": "sandipan@linux.ibm.com", "time": "Wed Jan 30 20:18:49 2019 +0530" }, "committer": { "name": "Sandipan Das", "email": "sandipan@linux.ibm.com", "time": "Mon Mar 25 04:47:41 2019 +0000" }, "message": "arch-power: Simplify doubleword operand types\n\nCurrently, \u0027sq\u0027 and \u0027uq\u0027 are used to represent signed and\nunsigned doublewords respectively. Since all recent Power\nISA specifications list 128-bit quadwords as a valid data\ntype, it may be misleading to use the current terminology\nin case support for such operands are added in the future.\nSo, to simplify this, \u0027sd\u0027 and \u0027ud\u0027 are used to represent\nsigned and unsigned doublewords respectively.\n\nChange-Id: Ie7831c596fc8f9ddfdf3b652c37cfe26484ebe01\nSigned-off-by: Sandipan Das \u003csandipan@linux.ibm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16602\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "4effe34f94b599add133357473e1b120b54719ab", "tree": "6efc0c7ab1636384d31ff9d8a79b55179fe39050", "parents": [ "759795a6b9e6e75c1e671457ef91b6329a692b18" ], "author": { "name": "Andrea Mondelli", "email": "Andrea.Mondelli@ucf.edu", "time": "Tue Mar 19 13:12:58 2019 -0400" }, "committer": { "name": "Andrea Mondelli", "email": "Andrea.Mondelli@ucf.edu", "time": "Sat Mar 23 00:05:33 2019 +0000" }, "message": "misc: missing override specifier\n\nMissing specifier of overridden virtual function\ndeclared in sim_object.hh\n\nRemoved redundant \"virtual\" keyword\n\nChange-Id: I42aa3349b537c9e62607bce20cf1b3aabdb99bf2\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17468\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "759795a6b9e6e75c1e671457ef91b6329a692b18", "tree": "9888741654f378c5bf4cb7e544f4a782e16b21f0", "parents": [ "d94e5b5d91c1a4f29264bee9c13edbdb70d0417e" ], "author": { "name": "Tiago Muck", "email": "tiago.muck@arm.com", "time": "Tue Aug 28 12:44:54 2018 -0500" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Fri Mar 22 14:31:40 2019 +0000" }, "message": "sim-se: Fixed initialization array size\n\nDoubled the size of the zeroed auxiliary vector since 2 * intSize on\naarch64 \u003e sizeof(uint64).\n\nChange-Id: I5196b000a696e9ea3f2b5daa5d5bb071794369aa\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17088\nReviewed-by: Ciro Santilli \u003cciro.santilli@arm.com\u003e\nMaintainer: Brandon Potter \u003cBrandon.Potter@amd.com\u003e\n" }, { "commit": "d94e5b5d91c1a4f29264bee9c13edbdb70d0417e", "tree": "bb2da4b992981e1588949a5dc644d30b6aae48e3", "parents": [ "bbcbde7a924ca1ca58df997cfe9f750c285e5564" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Thu Mar 21 15:41:04 2019 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Fri Mar 22 10:01:10 2019 +0000" }, "message": "base: Fix CircularQueue\u0027s operator-\u003d when negative subtraction\n\nUsing operator-\u003d when the rhs is a negative value is equivalent\nto using +\u003d on -rhs. This is fixing rounding in that scenario.\n\nChange-Id: Ia22e51f81a6805d27fd6b2115d288bb23421d00f\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17528\nReviewed-by: Daniel Carvalho \u003codanrc@yahoo.com.br\u003e\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "bbcbde7a924ca1ca58df997cfe9f750c285e5564", "tree": "b185621387765b3749fc939bbc4112e7b7a9852a", "parents": [ "487ea069be405844e1fcf4aa1ed274b74f601c39" ], "author": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Fri Mar 08 16:01:20 2019 +0000" }, "committer": { "name": "Giacomo Travaglini", "email": "giacomo.travaglini@arm.com", "time": "Fri Mar 22 10:01:10 2019 +0000" }, "message": "base: Fix CircularQueue when diffing iterators\n\nThis patch is fixing CircularQueue iterators\u0027 subtraction, in particular\nthe behaviour when head and tail round multiple times.\n\nChange-Id: Ie79ac8accd30a10cf039cf4def87675b01375d6b\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Gabor Dozsa \u003cgabor.dozsa@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17188\nReviewed-by: Daniel Carvalho \u003codanrc@yahoo.com.br\u003e\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "487ea069be405844e1fcf4aa1ed274b74f601c39", "tree": "6a96d3a17964ff7666d1bcd93a0bff6eaa0ab208", "parents": [ "699ba19096a5a8ea7eea93a2a8768910ca176b0b" ], "author": { "name": "Andrea Mondelli", "email": "Andrea.Mondelli@ucf.edu", "time": "Tue Mar 19 13:56:59 2019 -0400" }, "committer": { "name": "Andrea Mondelli", "email": "Andrea.Mondelli@ucf.edu", "time": "Thu Mar 21 18:15:13 2019 +0000" }, "message": "dev-arm: ambiguous use of getPort()\n\nThe recent introduction of getPort() creates a conflict with\nthe existing method used in arm MMU.\n\nThis patch rename the old getPort() in getDMAPort() according\nto the returned value (DmaPort class type)\n\nChange-Id: Ief3d83650fd6b08490522341631244be06e380ce\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17469\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "699ba19096a5a8ea7eea93a2a8768910ca176b0b", "tree": "cfc3b48a33465ca8a0983af5d17c8d296b75bd71", "parents": [ "19eb23f12ef6f8d951c880b7b5b1a212703b0ccd" ], "author": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Fri Mar 15 18:29:17 2019 -0700" }, "committer": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Thu Mar 21 15:57:10 2019 +0000" }, "message": "tests: Add ignore for stdin not terminal\n\nChange-Id: I496a9f3a0156557415d455dd2ca54c92577ca5f5\nSigned-off-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17455\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "19eb23f12ef6f8d951c880b7b5b1a212703b0ccd", "tree": "0ac5ac59c0b6f08b477c288c5ebb8aec59615728", "parents": [ "ee0e0ff6a01f135d14ac93e73eb7e1f5affcfbc1" ], "author": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Fri Mar 15 09:23:51 2019 -0700" }, "committer": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Thu Mar 21 15:57:10 2019 +0000" }, "message": "tests: Use full path for DownloadedProgram\n\nChange-Id: I1dceca80a425293d64f81b06ddff499363f18bc0\nSigned-off-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17454\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "ee0e0ff6a01f135d14ac93e73eb7e1f5affcfbc1", "tree": "f7111d99ab122c87e3f04e8fe4040c8a40de3f54", "parents": [ "76d9c83887000301f23094488ea170b0a04d1862" ], "author": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Thu Mar 14 16:36:34 2019 -0700" }, "committer": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Thu Mar 21 15:57:10 2019 +0000" }, "message": "tests: Fix race condition in download fixture\n\nChange-Id: Idace0e9e71a484080fc581e232ce217b449085c1\nSigned-off-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17453\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "76d9c83887000301f23094488ea170b0a04d1862", "tree": "d2197f63195f434ea6b95af2d36f6e3d14d6c5c1", "parents": [ "4c28149ffa5d09e6fe14952dcaf8df5d0cd8f328" ], "author": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Thu Mar 14 16:24:11 2019 -0700" }, "committer": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Thu Mar 21 15:57:10 2019 +0000" }, "message": "ext,tests: Add back failing exceptions\n\nChange-Id: Idf4ba8a2a3888787abf33d1a4ac52fcf146ce732\nSigned-off-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17452\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "4c28149ffa5d09e6fe14952dcaf8df5d0cd8f328", "tree": "d7d9028095760d940280d4f6f21d0844e1167ea7", "parents": [ "fced86b061b9419b9e44cd79a5af428a453779f3" ], "author": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Wed Mar 13 10:32:07 2019 -0700" }, "committer": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Thu Mar 21 15:57:10 2019 +0000" }, "message": "tests,ext: Add skip_cleanup implementation for TempdirFixture\n\nChange-Id: Idc5ec9309a4ef3c0ad0c7e8b2df47294acc97ec4\nSigned-off-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17451\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "fced86b061b9419b9e44cd79a5af428a453779f3", "tree": "cd35fd1d19c3ca7ec8406c11d111107c77121a4e", "parents": [ "f871fd33e11f9c989a865db20d2e478b0b4418b5" ], "author": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Thu Mar 14 10:05:46 2019 -0700" }, "committer": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Thu Mar 21 15:57:10 2019 +0000" }, "message": "ext,tests: Make return code based on test results\n\nThis patch also fixes a spelling mistake.\n\nChange-Id: I8635216e512c10913a9cda54541d7e31e0d22a40\nSigned-off-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17450\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "f871fd33e11f9c989a865db20d2e478b0b4418b5", "tree": "a624de10101674a259c5745ccb6ac5928f10e5de", "parents": [ "541d89953a4d2264702b90204ed91bb589a056ae" ], "author": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Tue Mar 12 09:01:09 2019 -0700" }, "committer": { "name": "Jason Lowe-Power", "email": "jason@lowepower.com", "time": "Thu Mar 21 15:57:10 2019 +0000" }, "message": "ext,test: Provide default terminal size\n\nWhen creating the separator for printing things to the terminal (\u003d.*) we\nuse an ioctl that isn\u0027t supported in some sandboxed environments. When\nrunning on the Google jenkins server (kokoro) it errors with an IOError.\n\nChange-Id: I148dd87cffe6e93d6723a386aecf9a9ea6c5b455\nSigned-off-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17449\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "541d89953a4d2264702b90204ed91bb589a056ae", "tree": "a9cfaf0addf09239d6efc0d20c50ef79859b2aeb", "parents": [ "81e34b308f3738cc9e88ae3066b5ed47c918c9de" ], "author": { "name": "Ryan Gambord", "email": "gambordr@oregonstate.edu", "time": "Thu Mar 21 07:01:29 2019 -0700" }, "committer": { "name": "Ryan Gambord", "email": "gambordr@oregonstate.edu", "time": "Thu Mar 21 14:24:48 2019 +0000" }, "message": "cpu-kvm: Added informative error message\n\nPerfKvmCounter::attach fails if the user doesn\u0027t have privileges to make\nthe perf_event_open syscall. This is the default privilege setting since\nkernel 4.6. I\u0027ve seen some users in the mailing list resort to running\nas root; changing the perf_event_paranoid setting is an alternative.\n\nChange-Id: I2bc6f76abb6e97bf34b408a611f64b1910f50a43\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17508\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "81e34b308f3738cc9e88ae3066b5ed47c918c9de", "tree": "80d824dd9019b087e52de0853e8373544ad05f56", "parents": [ "dee6fe7b6a4ce4f2d1e08af9250b6d1d6ce96836" ], "author": { "name": "Javier Bueno", "email": "javier.bueno@metempsy.com", "time": "Thu Mar 07 16:13:03 2019 +0100" }, "committer": { "name": "Javier Bueno Hedo", "email": "javier.bueno@metempsy.com", "time": "Wed Mar 20 11:35:16 2019 +0000" }, "message": "mem-cache: Added the STeMS prefetcher\n\nReference:\n Stephen Somogyi, Thomas F. Wenisch, Anastasia Ailamaki, and\n Babak Falsafi. 2009. Spatio-temporal memory streaming.\n In Proceedings of the 36th annual international symposium on\n Computer architecture (ISCA \u002709). ACM, New York, NY, USA, 69-80.\n\nChange-Id: I58cea1a7faa9391f8aa4469eb4973feabd31097a\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16423\nReviewed-by: Daniel Carvalho \u003codanrc@yahoo.com.br\u003e\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n" }, { "commit": "dee6fe7b6a4ce4f2d1e08af9250b6d1d6ce96836", "tree": "c16ccab67f329f37c4b8a9abd8d06ee4ed015786", "parents": [ "d3d24835bcc03ecf312ac6ba7df114656770730f" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Tue Mar 12 00:33:52 2019 -0700" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Tue Mar 19 10:23:12 2019 +0000" }, "message": "systemc: Hook up gem5_getPort to the gem5 getPort mechanism.\n\nChange-Id: I771607c4436f4c1ca9d355d1da52924308cfc3b3\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17229\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "d3d24835bcc03ecf312ac6ba7df114656770730f", "tree": "43bb564a7bc3e22ffd7b1b906f6f96742ecb619a", "parents": [ "378d9ccbeb4053aeeab002159b26625854af54f7" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Thu Mar 07 03:02:35 2019 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Tue Mar 19 10:22:50 2019 +0000" }, "message": "arch, cpu, dev, gpu, mem, sim, python: start using getPort.\n\nReplace the getMasterPort, getSlavePort, and getEthPort functions\nwith getPort, and remove extraneous mechanisms that are no longer\nnecessary.\n\nChange-Id: Iab7e3c02d2f3a0cf33e7e824e18c28646b5bc318\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17040\nReviewed-by: Daniel Carvalho \u003codanrc@yahoo.com.br\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "378d9ccbeb4053aeeab002159b26625854af54f7", "tree": "8cb16b22c64054ec19480c4f918bd92f705b3543", "parents": [ "7f1458bec4ae3ea3fb5f0948f0323355e1f20512" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Thu Mar 07 01:36:08 2019 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Tue Mar 19 10:22:27 2019 +0000" }, "message": "python: Switch to the new getPort mechanism to connect ports.\n\nThis retrieves ports using the getPort method, and connects them using\nthe bind method on the ports themselves. Any smarts as far as what type\nof peers are allowed to connect or how they connect is left up to the\nindividual bind methods.\n\nChange-Id: Ic640d1fce8af1bed411116e5830edc4a8a0f9d66\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17039\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "7f1458bec4ae3ea3fb5f0948f0323355e1f20512", "tree": "4bdf685549971f6bd5b56e8049092f88a526f09d", "parents": [ "8e89366ada0213d45af088945406c82187b5014a" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Thu Mar 07 01:32:54 2019 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Tue Mar 19 10:21:46 2019 +0000" }, "message": "mem: Move bind() and unbind() into the Port class.\n\nThese are now pure virtual methods which more specialized port\nsubclasses will need to implement. The SlavePort class implements them\nby ignoring them and then providing parallel functions for the\nMasterPort to call. The MasterPort\u0027s methods do basically what they\ndid before, except now bind() uses dynamic cast to check if its peer\nis of the appropriate type and also to convert it into that type before\nconnecting to it.\n\nChange-Id: I0948799bc954acaebf371e6b6612cee1d3023bc4\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17038\nReviewed-by: Daniel Carvalho \u003codanrc@yahoo.com.br\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "8e89366ada0213d45af088945406c82187b5014a", "tree": "d29d7ad18e311c3e9dca5296ed1c7cf2e53ee6fd", "parents": [ "f870912a00dfa6b1ef8139ed35f65ef886b198c6" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Thu Mar 07 00:46:29 2019 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Tue Mar 19 10:21:14 2019 +0000" }, "message": "sim: Add a getPort function to SimObject.\n\nThis will retrieve a Port object from a given SimObject (which might\nnot be a MemObject) no matter what flavor of Port it is.\n\nChange-Id: I636b85e9d4929a05a769e165849106bcb5f3e9c1\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17037\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "f870912a00dfa6b1ef8139ed35f65ef886b198c6", "tree": "7d38ef203e46680518658d3c2ecc6464a9d4a9ee", "parents": [ "2da37b5efa70c34aa3665c947b0ef10c4e2a3ae7" ], "author": { "name": "Ryan Gambord", "email": "gambordr@oregonstate.edu", "time": "Mon Mar 18 01:08:32 2019 -0700" }, "committer": { "name": "Ryan Gambord", "email": "gambordr@oregonstate.edu", "time": "Tue Mar 19 00:13:50 2019 +0000" }, "message": "util: Build m5 with -no-pie flag\n\n\nAdded -no-pie flag to link /util/m5 to support newer versions of GCC \nthat enable PIE by default. Tested for backwards compatibility with GCC \n4.3, which, only warns for the unrecognized flag.\n\nChange-Id: I4b6df593936346b9d3e2fe29a5d85dde78b7cc5e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17429\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Jason Lowe-Power \u003cjason@lowepower.com\u003e\n" }, { "commit": "2da37b5efa70c34aa3665c947b0ef10c4e2a3ae7", "tree": "b9454cf2e18c01be576b53716c7d9769ad90421d", "parents": [ "7e38637c8dc1cff923c386e6ad74ceb9a1317ef2" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Wed Mar 06 20:43:59 2019 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Mon Mar 18 23:25:38 2019 +0000" }, "message": "python: Change || to \u0026\u0026 for MessageBuffers in connectPorts.\n\nThe connectPorts function currently checks if *either* of the peers in\na port connection are a MessageBuffer, and if so will ignore the\nconnection. This CL changes that || into a \u0026\u0026 so that *both* of the\npeers need to be a Ruby types (either a MessageBuffer or Network) for\nthe connection to be ignored. That makes it easier to contain that\nabnormal behavior to those types instead of having it apply even when\nother types of port owners are involved.\n\nUnfortunately the number of interesting Ruby types is unbounded, but\nthese are the types with ports as of today. This mechanism will\nhopefully be replacedall together so this should be a temporary issue.\n\nChange-Id: I140498770e5d37eb2abd3d99261d47e111f1c8ab\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17031\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Jason Lowe-Power \u003cjason@lowepower.com\u003e\n" }, { "commit": "7e38637c8dc1cff923c386e6ad74ceb9a1317ef2", "tree": "c0e44bd47e6547b2e3808934ed7c42d242202b84", "parents": [ "2a28a4f8d2ac1471ef3ba943fa5f52a2331759bf" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Thu Mar 14 04:12:19 2019 -0700" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Mon Mar 18 22:48:42 2019 +0000" }, "message": "python: Improve how templated SimObject classes are handled.\n\nWhen setting up a SimObject\u0027s Param structure, gem5 will autogenerate\na header file which attempts to declare the SimObject\u0027s C++ type. It\nhas had at least some level of sophistication there where it would\npull off the namespaces ahead of the class name and handle them\nproperly, but it didn\u0027t know how to handle templates.\n\nThis change improves that handling in two ways. First, it adds a new\nmagical SimObject attribute called \u0027cxx_template_params\u0027 which is used\nto specify what the template parameters are as a list. For instance, if\nyour SimObject was a template which took an integer constant as its\nfirst parameter and a type as its second, this attribute could look\nlike the following:\n\ncxx_template_params \u003d [ \u0027int FOO\u0027, \u0027class Bar\u0027 ]\n\nImportantly, if there are any default values for these template\nparameters, they should *not* be included here, they should be\nspecified where the class is later defined.\n\nThe second new mechanism is to add an internal CxxClass in the\nSimObject.cxx_param_decl method. This class accepts the class signature\nin the cxx_class attribute and the cxx_template_params and does two\nthings. First, it strips off namespaces like in the old implementation.\nSecond, it extracts and processes any template arguments attached to\nthe class. If these are constants (as determined by the contents of\ncxx_template_params), then they are stored verbatim. If they\u0027re types,\nthen they\u0027re recursively expanded into a CxxClass and stored that way.\nNote that these are the *values* of the template arguments, where as\ncxx_template_params lists the *types* and *names* of those arguments.\nIn our earlier example, if cxx_class was:\n\ncxx_class \u003d \u0027CoolClasses::ClassName\u003c12, Fruit::Apple\u003e\u0027\n\nThen CxxClass would extract the namespace \u0027CoolClasses\u0027, the class\nname \u0027ClassName\u0027, the argument \u002712\u0027, and the argument \u0027Fruit::Apple\u0027.\nThat second argument would be expanded into a CxxClass with the\nnamespace \u0027Fruit\u0027 and the class name \u0027Apple\u0027.\n\nImportantly here, because there were no default arguments given in\ncxx_template_params, all \"hidden\" arguments which would fall through\nto their defaults need to be fully specified in cxx_class.\n\nThe CxxClass has a method called declare() which uses the information\nextracted earlier to output all of the \"stuff\" necessary for declaring\nthe given class, including opening any containing namespaces and\nputting template\u003c...\u003e ahead of the actual class declaration with the\ntemplate parameters specified.\n\nIf any of the template arguments are themselves CxxClass instances,\nthen they\u0027ll be recursively declared immediately before the current\nclass is.\n\nAn alternative solution to this problem might be to include the header\nfile which actually defines the cxx_class type to avoid having to\ncome up with a declaration. Unfortunately this doesn\u0027t work since it\ncan set up include loops where the SimObject C++ header file includes\nthe param header to get access to the Param type, but that includes\nthe C++ header to get access to the SimObject type.\n\nThis also makes it harder for SimObjects to refer to each other, since\nthey rely on the declaration in the params header files when declaring\na member pointer to that type in their own Param structures.\n\nChange-Id: I68cfc36ddff6d789eb4cdef5178c4619ac2cc8b1\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17228\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "2a28a4f8d2ac1471ef3ba943fa5f52a2331759bf", "tree": "e1848c7026e79c1edfe56cae363ca9728fd94e8b", "parents": [ "eba0a509d80182c479e41d28bf71d3061f18590b" ], "author": { "name": "Hoa Nguyen", "email": "hoanguyen@ucdavis.edu", "time": "Thu Feb 28 17:51:51 2019 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Mon Mar 18 22:22:25 2019 +0000" }, "message": "scons: fix disable_partial logic for fast binary\n\nPartial linking should be disabled on darwin; however, the script\nfails to do so when force_lto is set, which results in gem5 building\nwith fast option fails on macOS. This fix changes disable_partial\nlogic, which should be True once it\u0027s True.\n\nSigned-off-by: Hoa Nguyen \u003choanguyen@ucdavis.edu\u003e\nChange-Id: I77d2a4cc4a9bf5c92c800c004eb744bb7081c42e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16888\nReviewed-by: Gabe Black \u003cgabeblack@google.com\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nMaintainer: Jason Lowe-Power \u003cjason@lowepower.com\u003e\n" }, { "commit": "eba0a509d80182c479e41d28bf71d3061f18590b", "tree": "6050185a3cb01af69e4a2c8a3f77a9c0a66aeb13", "parents": [ "0996afe2049e67d449557815af949caa79159e2e" ], "author": { "name": "Ryan Gambord", "email": "gambordr@oregonstate.edu", "time": "Sat Mar 16 20:52:34 2019 -0700" }, "committer": { "name": "Ryan Gambord", "email": "gambordr@oregonstate.edu", "time": "Mon Mar 18 21:00:17 2019 +0000" }, "message": "util: changed shebang on gem5img.py to python2.7\n\nChange-Id: Id1a2112ce940bf6721609e2637d925d35e5ded8a\nSigned-off-by: Ryan Gambord \u003cgambordr@oregonstate.edu\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17408\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Jason Lowe-Power \u003cjason@lowepower.com\u003e\n" }, { "commit": "0996afe2049e67d449557815af949caa79159e2e", "tree": "7f7833677a3f89d774a0e38e5578f183e16c5973", "parents": [ "fe3e8084959a6910f4c8d075c5c03e40d0269527" ], "author": { "name": "Andrea Mondelli", "email": "Andrea.Mondelli@ucf.edu", "time": "Fri Mar 15 17:00:20 2019 -0400" }, "committer": { "name": "Andrea Mondelli", "email": "Andrea.Mondelli@ucf.edu", "time": "Mon Mar 18 17:56:09 2019 +0000" }, "message": "mem-cache: tautological comparison of byteOrder\n\nError:\nbuild/X86/mem/cache/prefetch/indirect_memory.cc:56:24:\nerror: result of comparison of constant -1 with expression\nof type \u0027const ByteOrder\u0027 is always false\n[-Werror,-Wtautological-constant-out-of-range-compare]\n fatal_if(byteOrder \u003d\u003d -1, \"This prefetcher requires a defined ISA\\n\");\n ~~~~~~~~~ ^ ~~\nbuild/X86/base/logging.hh:205:14: note: expanded from macro \u0027fatal_if\u0027\n if ((cond)) { \\\n ^~~~\n1 error generated.\n\nFix:\ncast of constant (-1) used in comparison\n\nChange-Id: I3deb154c2fe5b92c4ddf499176cb185c4ec7cf64\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17388\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-by: Daniel Carvalho \u003codanrc@yahoo.com.br\u003e\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n" }, { "commit": "fe3e8084959a6910f4c8d075c5c03e40d0269527", "tree": "7e4e43608dfd8d3d5544177e439f57733f3837d8", "parents": [ "9e22a2ab603d743b187108986cfbeba07c0c0b8d" ], "author": { "name": "Andreas Sandberg", "email": "andreas.sandberg@arm.com", "time": "Mon Feb 25 11:55:02 2019 +0000" }, "committer": { "name": "Andreas Sandberg", "email": "andreas.sandberg@arm.com", "time": "Mon Mar 18 15:13:52 2019 +0000" }, "message": "configs: Use absolute import paths\n\nUse absoluate import paths to be Python 3 compatible. This also\nimports absolute_import from __future__ to ensure that Python 2.7\nbehaves the same way as Python 3.\n\nChange-Id: Ica06ed95814e9cd3e768b3e1785075e36f6e56d0\nSigned-off-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16708\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\n" }, { "commit": "9e22a2ab603d743b187108986cfbeba07c0c0b8d", "tree": "07b10923944be01fddf34ddd1309f8c666d445eb", "parents": [ "b496d4abcede94b0042c584cdedaee12cf541b7a" ], "author": { "name": "Ryan Gambord", "email": "gambordr@oregonstate.edu", "time": "Thu Mar 14 03:30:46 2019 -0700" }, "committer": { "name": "Ryan Gambord", "email": "gambordr@oregonstate.edu", "time": "Fri Mar 15 19:29:23 2019 +0000" }, "message": "mem: Removed circular include ref\n\nIf BasicLink.hh is modified, the style checker forces a reordering of \nthe includes, which results in build errors because it ends up including \nTopology.hh before including its xxxParams.hh files, which include \nforward declarations of the BasicLink family of classes, and so \nTopology.hh throws errors that BasicLink etc. are not declared. \n\nChange-Id: I664a0652e53f0cc61763c2190a980c655b85d397\nSigned-off-by: Ryan Gambord \u003cgambordr@oregonstate.edu\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17270\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n" }, { "commit": "b496d4abcede94b0042c584cdedaee12cf541b7a", "tree": "0470e172af881082b36af599a6f2fc83dfb2195e", "parents": [ "993c26938cb73239838893e3f5e46635392ea488" ], "author": { "name": "Javier Bueno", "email": "javier.bueno@metempsy.com", "time": "Thu Mar 07 15:42:10 2019 +0100" }, "committer": { "name": "Javier Bueno Hedo", "email": "javier.bueno@metempsy.com", "time": "Fri Mar 15 19:12:42 2019 +0000" }, "message": "mem-cache: Added the Indirect Memory Prefetcher\n\nReference:\n Xiangyao Yu, Christopher J. Hughes, Nadathur Satish, and Srinivas Devadas.\n 2015. IMP: indirect memory prefetcher. In Proceedings of the 48th\n International Symposium on Microarchitecture (MICRO-48). ACM,\n New York, NY, USA, 178-190. DOI: https://doi.org/10.1145/2830772.2830807\n\nChange-Id: I52790f69c13ec55b8c1c8b9396ef9a1fb1be9797\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16223\nReviewed-by: Daniel Carvalho \u003codanrc@yahoo.com.br\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n" }, { "commit": "993c26938cb73239838893e3f5e46635392ea488", "tree": "9fdc5b947df798923263c7c8d30327cd5ef73383", "parents": [ "6e8be00dff5717ba6bd066749d1847ea48680878" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Thu Mar 07 00:45:09 2019 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Fri Mar 15 18:38:35 2019 +0000" }, "message": "mem: Move the Port base class into sim.\n\nThe Port class is going to be officially used for more than just memory\nsystem connections.\n\nChange-Id: I493e721f99051865c5f0c06946a2303ff723c2af\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17036\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "6e8be00dff5717ba6bd066749d1847ea48680878", "tree": "fcf564fc8be09f570e597388c1231ccf50b12915", "parents": [ "a73069c87dab6d32d5de021d37e009a93cd50cac" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Thu Mar 07 00:33:53 2019 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Fri Mar 15 18:37:49 2019 +0000" }, "message": "dev: Make EtherInt inherit from Port.\n\nThis way a common function can return EtherInt (and master and slave\nports).\n\nChange-Id: I1215baaad918ef0352b228877241b2b6dd2503fc\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17035\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "a73069c87dab6d32d5de021d37e009a93cd50cac", "tree": "9962d8c6e3dd15dfff8c819fca625399694f0819", "parents": [ "b5046b2e512ccf3ffdbba85b169b1adcba6c4443" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Wed Mar 06 21:37:01 2019 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Fri Mar 15 18:37:02 2019 +0000" }, "message": "mem: Track the MemObject owner in MasterPort and SlavePort.\n\nThese types are much more tied to MemObjects and the gem5 memory\nprotocol than the Port or BaseMasterPort and BaseSlavePort classes.\n\nChange-Id: I36bc8c75b9c74d28ee8b65dbcbf742cd41135742\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17032\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "b5046b2e512ccf3ffdbba85b169b1adcba6c4443", "tree": "d5bedb1a6614f185fa3d44bc7efda2ea5858853a", "parents": [ "b482cff6c3330d1c43d5c8d18d25731f552f02ee" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Wed Mar 06 18:03:50 2019 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Fri Mar 15 18:14:25 2019 +0000" }, "message": "python: Simplify connectPorts() around EtherObject/EtherDevice.\n\nEtherDevice now inherits EtherObject and shares the same getEthPort\nvirtual function, so there\u0027s no need to treat them separately any more.\n\nChange-Id: Ia6c147fd97fece4a281c296521a7b095f793d32e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17030\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "b482cff6c3330d1c43d5c8d18d25731f552f02ee", "tree": "92c2a6059bcfec85e726a18b806b358723c8f70e", "parents": [ "f5ba0d66459c1c035d4613376d1d39af08e483de" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Wed Mar 06 17:38:23 2019 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Fri Mar 15 18:13:46 2019 +0000" }, "message": "dev: Make the EtherDevice class inherit EtherObject.\n\nThis avoids having to define two parallel versions of the getEthPort\nfunction, and the complex dynamic_cast macrame in connectPorts().\n\nChange-Id: I24c09864005ff39a049e50d7245ff17e9480edea\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17029\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "f5ba0d66459c1c035d4613376d1d39af08e483de", "tree": "2deb1b27c75279df5467d6035d27a0007380d01f", "parents": [ "94a00fb6d9270990cd04ae293556297a3c2f2563" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Wed Mar 06 17:29:43 2019 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Fri Mar 15 18:12:58 2019 +0000" }, "message": "dev: Turn EtherObject into an interface class.\n\nThis class used to drive from SimObject so that it could be derived\nfrom to get both the interface and SimObject while still using single\ninheritance.\n\nWith this change, EtherObject is now just an interface class with only\none pure virtual function which can be inherited alongside SimObject.\nThis makes it more flexible so that it can be used in places where you\nmight want a different inheritance hierarchy, for instance to inherit\nfrom MemObject.\n\nChange-Id: I0f07664d104eed012cf4ce6e30c416ada19505a7\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17028\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "94a00fb6d9270990cd04ae293556297a3c2f2563", "tree": "a31ca3cc465712e6b34fa67544657477394b7e33", "parents": [ "7bd864c144efd374adc36fe327339a0171ab4a72" ], "author": { "name": "Daniel", "email": "odanrc@yahoo.com.br", "time": "Thu Mar 14 00:51:35 2019 +0100" }, "committer": { "name": "Daniel Carvalho", "email": "odanrc@yahoo.com.br", "time": "Fri Mar 15 14:06:11 2019 +0000" }, "message": "mem-cache: Fix write hit latency calculation order\n\nPatch 6d8694a5fb5cfb905186249581cc6a3fde6cc38a changes the order\nat which the access latency is calculated for hits. This order\nis incorrect, since the calculations must use the blk\u0027s whenReady\nvalue before the access is satisfied.\n\nChange-Id: I30dae5435f54200cc8fdf71fd0dbd2cf9c6f8b17\nSigned-off-by: Daniel \u003codanrc@yahoo.com.br\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17190\nReviewed-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n" }, { "commit": "7bd864c144efd374adc36fe327339a0171ab4a72", "tree": "c622a139698a00a246ca003cc846ec4818bdd8f7", "parents": [ "1a2a7c76a09186ecf111a62526cd35ade67cfd07" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Thu Mar 07 00:28:50 2019 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Thu Mar 14 21:04:29 2019 +0000" }, "message": "python: Teach cxxMethod how to set return_value_policy.\n\nThis is passed through to the underlying call to PyBindMethod.\n\nChange-Id: Ib46c55664ba0707464bb84e137a0fad817aea1bb\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17034\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "1a2a7c76a09186ecf111a62526cd35ade67cfd07", "tree": "971ebbf54f9060ca7b06b470c77c49514530e4aa", "parents": [ "8cedf1df11f7de007fddd24a6f313eb875ebd1e8" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Thu Mar 07 00:27:52 2019 -0800" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Thu Mar 14 21:03:48 2019 +0000" }, "message": "python: Teach PyBindMethod how to set return_value_policy.\n\nChange-Id: Ia208e43672672556b36f905e8f71dce44b978d22\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17033\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "8cedf1df11f7de007fddd24a6f313eb875ebd1e8", "tree": "fd34c0d80c02a19e602eed9ce09cbd475220f811", "parents": [ "7f9cbfae9a091363ec46102cc3e693ac94b51493" ], "author": { "name": "Andrea Mondelli", "email": "Andrea.Mondelli@ucf.edu", "time": "Fri Mar 01 09:38:18 2019 -0500" }, "committer": { "name": "Andrea Mondelli", "email": "Andrea.Mondelli@ucf.edu", "time": "Thu Mar 14 15:09:07 2019 +0000" }, "message": "cpu: Refactor of Physical Register implementation\n\nThe implementation of the PhyRegId class is shared between multiple\ncpu models. The o3/misc.hh should only be included in o3 models.\n\nThis patch removes the dependencies between different model\nimplementations, allowing to add new O3-like CPU model.\n\nChange-Id: Ibb812517043befe75c48fab3ce9605a0d272870b\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16908\nReviewed-by: Anthony Gutierrez \u003canthony.gutierrez@amd.com\u003e\nReviewed-by: Bradley Wang \u003cradwang@ucdavis.edu\u003e\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "7f9cbfae9a091363ec46102cc3e693ac94b51493", "tree": "8b5637abbea3f430de96a9c2d90a4a1de665a536", "parents": [ "66c80fcb44dfbfb9dc70b972e33104f053bd3015" ], "author": { "name": "Daniel R. Carvalho", "email": "odanrc@yahoo.com.br", "time": "Thu Mar 07 17:12:23 2019 +0100" }, "committer": { "name": "Daniel Carvalho", "email": "odanrc@yahoo.com.br", "time": "Thu Mar 14 12:11:29 2019 +0000" }, "message": "python: Fix unknown params and proxy multiplication\n\nOne of the recent changes made params not visible anymore:\n NameError: global name \u0027params\u0027 is not defined\nThis is fixed by adding the proper import statement.\n\nHowever, the second error makes the multiplication values be assigned\nto other proxies (that are not even used on the multiplication). A\nworkaround is added to prevent this from happening by extending \"*\u003d\".\n\nChange-Id: I3ad276a456efff62058672d16caac2b3ad1b326b\nSigned-off-by: Daniel R. Carvalho \u003codanrc@yahoo.com.br\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17048\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "66c80fcb44dfbfb9dc70b972e33104f053bd3015", "tree": "a4968fad70027c90d39eb7093f31b9a5c1b67842", "parents": [ "c4cc3145cd1eeed236b5cd3f7b2424bc0761878e" ], "author": { "name": "Jairo Balart", "email": "jairo.balart@metempsy.com", "time": "Sat Feb 16 13:27:45 2019 +0100" }, "committer": { "name": "Jairo Balart", "email": "jairo.balart@metempsy.com", "time": "Thu Mar 14 10:54:16 2019 +0000" }, "message": "dev-arm: cleanup of gicv3 CPU interface code and fixes\n\nChange-Id: I4643140f60da4dc9179b5bfed1e3ddd7c2f23091\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16484\nReviewed-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nMaintainer: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\n" }, { "commit": "c4cc3145cd1eeed236b5cd3f7b2424bc0761878e", "tree": "b38eab6f5f389dfc53c2cf74275a83bacd2e9b18", "parents": [ "91195ae7f637d1d4879cc3bf0860147333846e75" ], "author": { "name": "Giacomo Gabrielli", "email": "giacomo.gabrielli@arm.com", "time": "Tue Oct 16 16:09:02 2018 +0100" }, "committer": { "name": "Giacomo Gabrielli", "email": "giacomo.gabrielli@arm.com", "time": "Thu Mar 14 10:42:27 2019 +0000" }, "message": "arch-arm,cpu: Add initial support for Arm SVE\n\nThis changeset adds initial support for the Arm Scalable Vector Extension\n(SVE) by implementing:\n- support for most data-processing instructions (no loads/stores yet);\n- basic system-level support.\n\nAdditional authors:\n- Javier Setoain \u003cjavier.setoain@arm.com\u003e\n- Gabor Dozsa \u003cgabor.dozsa@arm.com\u003e\n- Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\n\nThanks to Pau Cabre for his contribution of bugfixes.\n\nChange-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709\nSigned-off-by: Giacomo Gabrielli \u003cgiacomo.gabrielli@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13515\nReviewed-by: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\nMaintainer: Andreas Sandberg \u003candreas.sandberg@arm.com\u003e\n" }, { "commit": "91195ae7f637d1d4879cc3bf0860147333846e75", "tree": "c1638f69aaf37fd0dfd84e606fb6a08c92db08c6", "parents": [ "4ec5b85a31ded2afdf784555a7c736e61c8b594a" ], "author": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Tue Mar 12 05:00:41 2019 -0700" }, "committer": { "name": "Gabe Black", "email": "gabeblack@google.com", "time": "Tue Mar 12 15:43:38 2019 +0000" }, "message": "scons: Don\u0027t use isdir in AddLocalRPATH.\n\nisdir isn\u0027t a nice way to check if an FS.Base is a File or a Dir as was\ninitially assumed, it literally checks if a path can be stat-ed and is\nreported as a directory by stat. This means that if a directory is\ngoing to be created as part of the build, the result of that test will\nchange depending on whether that part of the build has happened\nsuccessfully before.\n\nA better check which behaves as originally intended is to check whether\nthe Node is an instance of the SCons.Node.FS.Dir class.\n\nChange-Id: Id041917d50b768a8205769c0a05320f92b09993c\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17128\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Gabe Black \u003cgabeblack@google.com\u003e\n" }, { "commit": "4ec5b85a31ded2afdf784555a7c736e61c8b594a", "tree": "4fcfb0de4ad484c306692c74e31ee071400c0d14", "parents": [ "509aa2179a1c7d403d69c6d766f0e93b14f7d37d" ], "author": { "name": "Daniel R. Carvalho", "email": "odanrc@yahoo.com.br", "time": "Wed Feb 20 11:05:29 2019 +0100" }, "committer": { "name": "Daniel Carvalho", "email": "odanrc@yahoo.com.br", "time": "Tue Mar 12 14:20:50 2019 +0000" }, "message": "sim: Add size to array unserialization error message\n\nAdd both acquired and expected size information to array\nunserialization error message.\n\nChange-Id: Ic0a493c5a7860066eb992e9e91e7a4746b197579\nSigned-off-by: Daniel R. Carvalho \u003codanrc@yahoo.com.br\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16542\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nMaintainer: Jason Lowe-Power \u003cjason@lowepower.com\u003e\n" }, { "commit": "509aa2179a1c7d403d69c6d766f0e93b14f7d37d", "tree": "d7d4bebb8faaedff36a562c69d13ba00c59c2f16", "parents": [ "5352c73dfa9113bdc0206e0c44bbf0861a9a3c39" ], "author": { "name": "Jairo Balart", "email": "jairo.balart@metempsy.com", "time": "Thu Feb 07 23:25:57 2019 +0100" }, "committer": { "name": "Jairo Balart", "email": "jairo.balart@metempsy.com", "time": "Tue Mar 12 09:33:40 2019 +0000" }, "message": "dev-arm: cleanup of gicv3 code\n\nChange-Id: I9aba90022f6408838c4ab87c6b90bba438752e53\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16222\nReviewed-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nMaintainer: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\n" }, { "commit": "5352c73dfa9113bdc0206e0c44bbf0861a9a3c39", "tree": "e6db43a632d98369f2dd1c8470e955949e417aa1", "parents": [ "7fd818f2b843a2810270da124d3441f836ca5e5f" ], "author": { "name": "Ryan Gambord", "email": "gambordr@oregonstate.edu", "time": "Sun Mar 10 20:32:21 2019 -0700" }, "committer": { "name": "Ryan Gambord", "email": "gambordr@oregonstate.edu", "time": "Tue Mar 12 00:20:22 2019 +0000" }, "message": "mem-cache: Removed default arg from get() in prefetch/base.hh\n\ncommit b0d1643 caused building against NULL to break due to\nNULLIsa::GuestByteOrder not being defined.\n\nRemoval of default argument in src/mem/cache/prefetch/base.hh fixes\nthis.\n\nChange-Id: I99a4abb4be1418fadec145481164f7caa3334ca0\nSigned-off-by: Ryan Gambord\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17070\nReviewed-by: Daniel Carvalho \u003codanrc@yahoo.com.br\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n" }, { "commit": "7fd818f2b843a2810270da124d3441f836ca5e5f", "tree": "984debd359631ddde0537d1852ccb9223202999d", "parents": [ "6d67e86a1b5241117a4e311de7bcf58512b90aa0" ], "author": { "name": "Ryan Gambord", "email": "gambordr@oregonstate.edu", "time": "Wed Mar 06 23:17:43 2019 -0800" }, "committer": { "name": "Ryan Gambord", "email": "gambordr@oregonstate.edu", "time": "Mon Mar 11 22:13:24 2019 +0000" }, "message": "arch-hsail: changed gen.py shebang from python(3) to python2.7\n\ngen.py includes code_formatter from m5.util. code_formatter uses the\npython2 __metaclass__ attribute, which is ignored by python3, causing\nthe code_formatter.pattern attribute to be unset.\n\nThis prevented scons from building against HSAIL_X86\n\nSigned-off-by: Ryan Gambord\n\u003cgambordr@oregonstate.edu\u003e\n\nChange-Id: I5a8bf9e730fd629eb7f9a7ac2dce928235a0dae4\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17008\nReviewed-by: Andrea Mondelli \u003cAndrea.Mondelli@ucf.edu\u003e\nReviewed-by: Anthony Gutierrez \u003canthony.gutierrez@amd.com\u003e\nMaintainer: Anthony Gutierrez \u003canthony.gutierrez@amd.com\u003e\n" }, { "commit": "6d67e86a1b5241117a4e311de7bcf58512b90aa0", "tree": "10159bd77a9595f88a0acad5f7cfd1893b4a0f4f", "parents": [ "29f68cc7ba4c9d4c1e07806ae226d148a8a25e0e" ], "author": { "name": "Ryan Gambord", "email": "gambordr@oregonstate.edu", "time": "Mon Mar 11 04:04:30 2019 -0700" }, "committer": { "name": "Ryan Gambord", "email": "gambordr@oregonstate.edu", "time": "Mon Mar 11 17:23:36 2019 +0000" }, "message": "arch-arm: Fixing implicit fallthrough build errors\n\n2c242d6 introduced implicit-fallthrough errors when building against\nARM.\n\nAdded \"default: return new Unknown(machInst);\" to offending switch\nstatements; please verify this is the corret behavior\n\nSigned-off-by: Ryan Gambord\n\nChange-Id: I5f5e3661ec562d4a3b2699e07d1195e6877ff959\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17071\nReviewed-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nMaintainer: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\n" }, { "commit": "29f68cc7ba4c9d4c1e07806ae226d148a8a25e0e", "tree": "62ed4a70716b3f2c89f3ee98fdf997074c5df83a", "parents": [ "b0d1643ddf849d5e9b68a2e6535fa1ef561eac92" ], "author": { "name": "Daniel R. Carvalho", "email": "odanrc@yahoo.com.br", "time": "Fri Mar 08 17:41:25 2019 +0100" }, "committer": { "name": "Daniel Carvalho", "email": "odanrc@yahoo.com.br", "time": "Mon Mar 11 08:57:24 2019 +0000" }, "message": "mem-cache: Revert \"mem-cache: Remove Packet dependency in Tags\"\n\nReverting patch due to polymorphism limitations.\n\nThis reverts commit 86a54d91936b524c0ef0f282959f0fc29bafe7eb.\n\nChange-Id: Ie032dcc5176448c62118c89732b3cc6b8efd5a13\nSigned-off-by: Daniel R. Carvalho \u003codanrc@yahoo.com.br\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17049\nReviewed-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n" }, { "commit": "b0d1643ddf849d5e9b68a2e6535fa1ef561eac92", "tree": "f069b86f6994da34fdbad081dcd3e57baf9ee22a", "parents": [ "a4686352714aa0d91b2d98b25a6f45b84262f97d" ], "author": { "name": "Javier Bueno", "email": "javier.bueno@metempsy.com", "time": "Thu Feb 21 22:12:05 2019 +0100" }, "committer": { "name": "Javier Bueno Hedo", "email": "javier.bueno@metempsy.com", "time": "Sun Mar 10 21:49:56 2019 +0000" }, "message": "mem-cache: Added extra information to PrefetchInfo\n\nAdded additional information to the PrefetchInfo data structure\n- Whether the event is triggered by a cache miss\n- Whether the event is a write or a read\n- Size of the data accessed\n- Data accessed by the request\n\nChange-Id: I070f3ffe837ea960a357388e7f2b8a61d7b2196c\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16583\nReviewed-by: Daniel Carvalho \u003codanrc@yahoo.com.br\u003e\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n" }, { "commit": "a4686352714aa0d91b2d98b25a6f45b84262f97d", "tree": "781fac0de8b1b05b0bef536aeb0fa15f246c6678", "parents": [ "6d8694a5fb5cfb905186249581cc6a3fde6cc38a" ], "author": { "name": "Daniel R. Carvalho", "email": "odanrc@yahoo.com.br", "time": "Wed Dec 05 15:29:58 2018 +0100" }, "committer": { "name": "Daniel Carvalho", "email": "odanrc@yahoo.com.br", "time": "Thu Mar 07 13:07:09 2019 +0000" }, "message": "mem-cache: Add header delay to handleFill whenReady\n\nA prefetch response will have a header delay, which was not being\ntaken into account.\n\nChange-Id: I66a071bc81ef41b8c0de37aa2df75171d1979a6f\nSigned-off-by: Daniel R. Carvalho \u003codanrc@yahoo.com.br\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14895\nReviewed-by: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\nMaintainer: Nikos Nikoleris \u003cnikos.nikoleris@arm.com\u003e\n" } ], "next": "6d8694a5fb5cfb905186249581cc6a3fde6cc38a" }