- 04bc162 mem-cache: Fix RRPV for RRIP by Anis Peysieux · 5 years ago master
- 740756e arch-arm: Enable PMSELR_EL0 read in PMU by Giacomo Travaglini · 5 years ago
- 680a689 mem: Plumb backdoor requests through the xbar classes. by Gabe Black · 5 years ago
- 729d994 systemc: Teach the TLM bridges how to use gem5's new backdoor mechanism. by Gabe Black · 5 years ago
- 64f415f mem: Add sendAtomicBackdoor/recvAtomicBackdoor port methods. by Gabe Black · 5 years ago
- a8d5dd1 mem-cache: Fix MSHR handling of cache clean requests by Nikos Nikoleris · 5 years ago
- daa9dcb cpu: O3 switchFreeList checking VecElems instead of FloatRegs by Giacomo Travaglini · 5 years ago
- 7f9c984 learning_gem5,configs: Update ruby_test by Jason Lowe-Power · 5 years ago
- c1e646d learning_gem5: Fix vector port panic in SimpleCache by Jason Lowe-Power · 5 years ago
- 36bce39 configs: Fix import path error in learning_gem5 part3 by Jason Lowe-Power · 5 years ago
- 6bcd13f configs: Add full path for learning_gem5 binaries by Jason Lowe-Power · 5 years ago
- ca687ea configs: Removed redudant exec-style import by Ryan Gambord · 5 years ago
- 2cf18a8 mem: Add a MemBackdoor type to track memory backdoors. by Gabe Black · 5 years ago
- d0f8765 cpu: Correctly account for executed instructions in simple cpus by Nikos Nikoleris · 5 years ago
- 271f2ae mem-cache: ambiguous use of abs function by Ryan Gambord · 5 years ago
- 529d0cd mem: Reverse order of write/read mem queue check by Jason Lowe-Power · 5 years ago
- 07eca72 tests: Add Jenkins presubmit and continuous test scripts by Jason Lowe-Power · 5 years ago
- c2c1a97 mem-cache: AMPM Prefetcher fails when restoring from a checkpoint by Javier Bueno · 5 years ago
- e13d6dc misc: Removed inconsistency in O3* debug msgs by Andrea Mondelli · 5 years ago
- 5084b90 arch-mips: added missing override specifier (o3) by Andrea Mondelli · 5 years ago
- 5caa451 mem-cache: Fix PIF prefetcher compilation error with NULL ISA by Javier Bueno · 5 years ago
- f662b8a mem-cache: ISB prefetcher was triggering an assertion by Javier Bueno · 5 years ago
- 06b305b mem-cache: Fix panic in Indirect Memory prefetcher by Javier Bueno · 5 years ago
- e7a1636 dev-arm: Make GICv3 maintenance interrupt an ArmInterrupt by Giacomo Travaglini · 5 years ago
- 4628d87 mem-cache: Proactive Instruction Fetch Implementation by Ivan Pizarro · 5 years ago
- 283e092 dev-arm: Correct cast of template parameter by Andrea Mondelli · 5 years ago
- 2a98a99 systemc: Templatize the gem5/TLM bridge SimObjects. by Gabe Black · 5 years ago
- b2efb72 systemc: Delete extra code from src/systemc/tlm_bridge. by Gabe Black · 5 years ago
- e65a89e systemc: Create unified gem5/TLM bridge SimObjects. by Gabe Black · 5 years ago
- 9a042da tlm: Initial import of tlm/gem5 bridge code. by Gabe Black · 5 years ago
- 87c4a97 systemc: Provide a utility Port TLM socket wrapper class. by Gabe Black · 5 years ago
- 1a27580 cpu: Added a probe to notify the address of retired instructions by Javier Bueno · 5 years ago
- cbaae54 mem-cache: Remove extra cache header from AMAP by Daniel R. Carvalho · 5 years ago
- a93fe3f arch-arm: Fix use of bitwise operators on booleans by Javier Setoain · 5 years ago
- 93ad0d4 arch-arm: Fix index generation for VecElem operands by Giacomo Travaglini · 5 years ago
- 631bfb6 dev-arm: Rename GIC maintenance interrupt from ppint to maint_int by Giacomo Travaglini · 5 years ago
- e8a6811 dev-arm: Fix GICv3 overflow for INTID > 256 by Giacomo Travaglini · 5 years ago
- e36839e dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI (or RES0) by Giacomo Travaglini · 5 years ago
- 9059aaf config: Use the corresponding HPI Caches when using the HPI cpu by Javier Bueno · 5 years ago
- 78f1f4d cpu: Fixed the indirect branch predictor GHR handling by Pau Cabre · 5 years ago
- 4fc7dfb mem: Deleting this init() method was accidentally dropped during rebase. by Gabe Black · 5 years ago
- 599d2c9 mem: Clean up the xbars a little. by Gabe Black · 5 years ago
- fcc4c4f base: Make AddrRangeMap able to return non-const iterators. by Gabe Black · 5 years ago
- c67d89f configs: fix class reference in CacheConfigs by Javier Bueno · 5 years ago
- 61f0e7e dev-arm: Set/Unset dma coherent mode from python by Giacomo Travaglini · 5 years ago
- ca4c0a1 base,python: Fix to allow multiple --debug-ignore values. by Isaac Sánchez Barrera · 5 years ago
- 149c1fc configs: Remove default kernel value from system creation by Daniel R. Carvalho · 6 years ago
- 8e1a141 arch-arm: Add missing fall-through defaults by Javier Setoain · 5 years ago
- f838a33 arch-power: Rename program counter registers by Sandipan Das · 5 years ago
- 4847330 arch-power: Simplify doubleword operand types by Sandipan Das · 5 years ago
- 4effe34 misc: missing override specifier by Andrea Mondelli · 5 years ago
- 759795a sim-se: Fixed initialization array size by Tiago Muck · 6 years ago
- d94e5b5 base: Fix CircularQueue's operator-= when negative subtraction by Giacomo Travaglini · 5 years ago
- bbcbde7 base: Fix CircularQueue when diffing iterators by Giacomo Travaglini · 5 years ago
- 487ea06 dev-arm: ambiguous use of getPort() by Andrea Mondelli · 5 years ago
- 699ba19 tests: Add ignore for stdin not terminal by Jason Lowe-Power · 5 years ago
- 19eb23f tests: Use full path for DownloadedProgram by Jason Lowe-Power · 5 years ago
- ee0e0ff tests: Fix race condition in download fixture by Jason Lowe-Power · 5 years ago
- 76d9c83 ext,tests: Add back failing exceptions by Jason Lowe-Power · 5 years ago
- 4c28149 tests,ext: Add skip_cleanup implementation for TempdirFixture by Jason Lowe-Power · 5 years ago
- fced86b ext,tests: Make return code based on test results by Jason Lowe-Power · 5 years ago
- f871fd3 ext,test: Provide default terminal size by Jason Lowe-Power · 5 years ago
- 541d899 cpu-kvm: Added informative error message by Ryan Gambord · 5 years ago
- 81e34b3 mem-cache: Added the STeMS prefetcher by Javier Bueno · 5 years ago
- dee6fe7 systemc: Hook up gem5_getPort to the gem5 getPort mechanism. by Gabe Black · 5 years ago
- d3d2483 arch, cpu, dev, gpu, mem, sim, python: start using getPort. by Gabe Black · 5 years ago
- 378d9cc python: Switch to the new getPort mechanism to connect ports. by Gabe Black · 5 years ago
- 7f1458b mem: Move bind() and unbind() into the Port class. by Gabe Black · 5 years ago
- 8e89366 sim: Add a getPort function to SimObject. by Gabe Black · 5 years ago
- f870912 util: Build m5 with -no-pie flag by Ryan Gambord · 5 years ago
- 2da37b5 python: Change || to && for MessageBuffers in connectPorts. by Gabe Black · 5 years ago
- 7e38637 python: Improve how templated SimObject classes are handled. by Gabe Black · 5 years ago
- 2a28a4f scons: fix disable_partial logic for fast binary by Hoa Nguyen · 5 years ago
- eba0a50 util: changed shebang on gem5img.py to python2.7 by Ryan Gambord · 5 years ago
- 0996afe mem-cache: tautological comparison of byteOrder by Andrea Mondelli · 5 years ago
- fe3e808 configs: Use absolute import paths by Andreas Sandberg · 5 years ago
- 9e22a2a mem: Removed circular include ref by Ryan Gambord · 5 years ago
- b496d4a mem-cache: Added the Indirect Memory Prefetcher by Javier Bueno · 5 years ago
- 993c269 mem: Move the Port base class into sim. by Gabe Black · 5 years ago
- 6e8be00 dev: Make EtherInt inherit from Port. by Gabe Black · 5 years ago
- a73069c mem: Track the MemObject owner in MasterPort and SlavePort. by Gabe Black · 5 years ago
- b5046b2 python: Simplify connectPorts() around EtherObject/EtherDevice. by Gabe Black · 5 years ago
- b482cff dev: Make the EtherDevice class inherit EtherObject. by Gabe Black · 5 years ago
- f5ba0d6 dev: Turn EtherObject into an interface class. by Gabe Black · 5 years ago
- 94a00fb mem-cache: Fix write hit latency calculation order by Daniel · 5 years ago
- 7bd864c python: Teach cxxMethod how to set return_value_policy. by Gabe Black · 5 years ago
- 1a2a7c7 python: Teach PyBindMethod how to set return_value_policy. by Gabe Black · 5 years ago
- 8cedf1d cpu: Refactor of Physical Register implementation by Andrea Mondelli · 5 years ago
- 7f9cbfa python: Fix unknown params and proxy multiplication by Daniel R. Carvalho · 5 years ago
- 66c80fc dev-arm: cleanup of gicv3 CPU interface code and fixes by Jairo Balart · 5 years ago
- c4cc314 arch-arm,cpu: Add initial support for Arm SVE by Giacomo Gabrielli · 6 years ago
- 91195ae scons: Don't use isdir in AddLocalRPATH. by Gabe Black · 5 years ago
- 4ec5b85 sim: Add size to array unserialization error message by Daniel R. Carvalho · 5 years ago
- 509aa21 dev-arm: cleanup of gicv3 code by Jairo Balart · 5 years ago
- 5352c73 mem-cache: Removed default arg from get() in prefetch/base.hh by Ryan Gambord · 5 years ago
- 7fd818f arch-hsail: changed gen.py shebang from python(3) to python2.7 by Ryan Gambord · 5 years ago
- 6d67e86 arch-arm: Fixing implicit fallthrough build errors by Ryan Gambord · 5 years ago
- 29f68cc mem-cache: Revert "mem-cache: Remove Packet dependency in Tags" by Daniel R. Carvalho · 5 years ago
- b0d1643 mem-cache: Added extra information to PrefetchInfo by Javier Bueno · 5 years ago
- a468635 mem-cache: Add header delay to handleFill whenReady by Daniel R. Carvalho · 5 years ago
