Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
--HG--
extra : convert_revision : c56b8160b403fde235636ca5b5b4cecd206ffa4c
diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 180f415..8b3e9a1 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -226,8 +226,8 @@
assert(removeAddr != outstandingAddrs.end());
outstandingAddrs.erase(removeAddr);
- switch (pkt->cmd) {
- case Packet::ReadResp:
+ switch (pkt->cmd.toInt()) {
+ case MemCmd::ReadResp:
if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
cerr << name() << ": on read of 0x" << hex << req->getPaddr()
@@ -254,7 +254,7 @@
exitSimLoop("Maximum number of loads reached!");
break;
- case Packet::WriteResp:
+ case MemCmd::WriteResp:
numWritesStat++;
break;
/*
@@ -389,7 +389,7 @@
<< dec << curTick << endl;
}
- PacketPtr pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
+ PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
pkt->dataDynamicArray(new uint8_t[req->getSize()]);
MemTestSenderState *state = new MemTestSenderState(result);
pkt->senderState = state;
@@ -429,7 +429,7 @@
<< dec << curTick << endl;
}
*/
- PacketPtr pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
+ PacketPtr pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
uint8_t *pkt_data = new uint8_t[req->getSize()];
pkt->dataDynamicArray(pkt_data);
memcpy(pkt_data, &data, req->getSize());
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index b80fc72..e6a7798 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -602,7 +602,7 @@
// Build packet here.
PacketPtr data_pkt = new Packet(mem_req,
- Packet::ReadReq, Packet::Broadcast);
+ MemCmd::ReadReq, Packet::Broadcast);
data_pkt->dataDynamicArray(new uint8_t[cacheBlkSize]);
cacheDataPC[tid] = block_PC;
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 9c7eb77..2419afe 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -574,7 +574,8 @@
"addr %#x, data %#x\n",
store_idx, req->getVaddr(), data);
- PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
+ PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq,
+ Packet::Broadcast);
data_pkt->dataStatic(load_inst->memData);
WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
@@ -638,7 +639,7 @@
// if we the cache is not blocked, do cache access
if (!lsq->cacheBlocked()) {
PacketPtr data_pkt =
- new Packet(req, Packet::ReadReq, Packet::Broadcast);
+ new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
data_pkt->dataStatic(load_inst->memData);
LSQSenderState *state = new LSQSenderState;
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index ebd9301..3ba22a5 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -613,7 +613,8 @@
(sizeof(TheISA::IntReg) - req->getSize()) : 0),
req->getSize());
- PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
+ PacketPtr data_pkt = new Packet(req, MemCmd::WriteReq,
+ Packet::Broadcast);
data_pkt->dataStatic(inst->memData);
LSQSenderState *state = new LSQSenderState;
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 3b3536e..fa47b0e 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -138,18 +138,18 @@
ifetch_req = new Request();
ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
- ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
+ ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
ifetch_pkt->dataStatic(&inst);
data_read_req = new Request();
data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
- data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
+ data_read_pkt = new Packet(data_read_req, MemCmd::ReadReq,
Packet::Broadcast);
data_read_pkt->dataStatic(&dataReg);
data_write_req = new Request();
data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
- data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
+ data_write_pkt = new Packet(data_write_req, MemCmd::WriteReq,
Packet::Broadcast);
}
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index dfffb0b..e4748c9 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -286,7 +286,7 @@
// Now do the access.
if (fault == NoFault) {
PacketPtr pkt =
- new Packet(req, Packet::ReadReq, Packet::Broadcast);
+ new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
pkt->dataDynamic<T>(new T);
if (!dcachePort.sendTiming(pkt)) {
@@ -365,7 +365,7 @@
// Now do the access.
if (fault == NoFault) {
assert(dcache_pkt == NULL);
- dcache_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
+ dcache_pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
dcache_pkt->allocate();
dcache_pkt->set(data);
@@ -454,7 +454,7 @@
ifetch_req->setThreadContext(cpu_id, /* thread ID */ 0);
Fault fault = setupFetchRequest(ifetch_req);
- ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
+ ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
ifetch_pkt->dataStatic(&inst);
if (fault == NoFault) {
diff --git a/src/dev/io_device.hh b/src/dev/io_device.hh
index c56eba2..902cde9 100644
--- a/src/dev/io_device.hh
+++ b/src/dev/io_device.hh
@@ -256,10 +256,13 @@
virtual ~DmaDevice();
void dmaWrite(Addr addr, int size, Event *event, uint8_t *data)
- { dmaPort->dmaAction(Packet::WriteInvalidateReq, addr, size, event, data) ; }
+ {
+ dmaPort->dmaAction(MemCmd::WriteInvalidateReq,
+ addr, size, event, data);
+ }
void dmaRead(Addr addr, int size, Event *event, uint8_t *data = NULL)
- { dmaPort->dmaAction(Packet::ReadReq, addr, size, event, data); }
+ { dmaPort->dmaAction(MemCmd::ReadReq, addr, size, event, data); }
bool dmaPending() { return dmaPort->dmaPending(); }
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index bd721dd..cc2137e 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -180,7 +180,8 @@
}
} else {
//Snoop didn't succeed
- DPRINTF(Bus, "Adding a retry to RETRY list %i\n", pktPort);
+ DPRINTF(Bus, "Adding a retry to RETRY list %d\n",
+ pktPort->getId());
addToRetryList(pktPort);
return false;
}
@@ -197,7 +198,8 @@
// Packet was successfully sent. Return true.
// Also take care of retries
if (inRetry) {
- DPRINTF(Bus, "Remove retry from list %i\n", retryList.front());
+ DPRINTF(Bus, "Remove retry from list %d\n",
+ retryList.front()->getId());
retryList.front()->onRetryList(false);
retryList.pop_front();
inRetry = false;
@@ -206,7 +208,8 @@
}
// Packet not successfully sent. Leave or put it on the retry list.
- DPRINTF(Bus, "Adding a retry to RETRY list %i\n", pktPort);
+ DPRINTF(Bus, "Adding a retry to RETRY list %d\n",
+ pktPort->getId());
addToRetryList(pktPort);
return false;
}
diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index 0ad4aad..350a67b 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -156,6 +156,8 @@
void onRetryList(bool newVal)
{ _onRetryList = newVal; }
+ int getId() { return id; }
+
protected:
/** When reciving a timing request from the peer port (at id),
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index d9e6c5e..ed665da 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -356,7 +356,7 @@
const char *
BaseCache::CacheEvent::description()
{
- return "timing event\n";
+ return "BaseCache timing event";
}
void
@@ -370,17 +370,12 @@
void
BaseCache::regStats()
{
- Request temp_req((Addr) NULL, 4, 0);
- Packet::Command temp_cmd = Packet::ReadReq;
- Packet temp_pkt(&temp_req, temp_cmd, 0); //@todo FIx command strings so this isn't neccessary
- temp_pkt.allocate(); //Temp allocate, all need data
-
using namespace Stats;
// Hit statistics
- for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
- Packet::Command cmd = (Packet::Command)access_idx;
- const string &cstr = temp_pkt.cmdIdxToString(cmd);
+ for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
+ MemCmd cmd(access_idx);
+ const string &cstr = cmd.toString();
hits[access_idx]
.init(maxThreadsPerCPU)
@@ -395,20 +390,20 @@
.desc("number of demand (read+write) hits")
.flags(total)
;
- demandHits = hits[Packet::ReadReq] + hits[Packet::WriteReq];
+ demandHits = hits[MemCmd::ReadReq] + hits[MemCmd::WriteReq];
overallHits
.name(name() + ".overall_hits")
.desc("number of overall hits")
.flags(total)
;
- overallHits = demandHits + hits[Packet::SoftPFReq] + hits[Packet::HardPFReq]
- + hits[Packet::Writeback];
+ overallHits = demandHits + hits[MemCmd::SoftPFReq] + hits[MemCmd::HardPFReq]
+ + hits[MemCmd::Writeback];
// Miss statistics
- for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
- Packet::Command cmd = (Packet::Command)access_idx;
- const string &cstr = temp_pkt.cmdIdxToString(cmd);
+ for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
+ MemCmd cmd(access_idx);
+ const string &cstr = cmd.toString();
misses[access_idx]
.init(maxThreadsPerCPU)
@@ -423,20 +418,20 @@
.desc("number of demand (read+write) misses")
.flags(total)
;
- demandMisses = misses[Packet::ReadReq] + misses[Packet::WriteReq];
+ demandMisses = misses[MemCmd::ReadReq] + misses[MemCmd::WriteReq];
overallMisses
.name(name() + ".overall_misses")
.desc("number of overall misses")
.flags(total)
;
- overallMisses = demandMisses + misses[Packet::SoftPFReq] +
- misses[Packet::HardPFReq] + misses[Packet::Writeback];
+ overallMisses = demandMisses + misses[MemCmd::SoftPFReq] +
+ misses[MemCmd::HardPFReq] + misses[MemCmd::Writeback];
// Miss latency statistics
- for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
- Packet::Command cmd = (Packet::Command)access_idx;
- const string &cstr = temp_pkt.cmdIdxToString(cmd);
+ for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
+ MemCmd cmd(access_idx);
+ const string &cstr = cmd.toString();
missLatency[access_idx]
.init(maxThreadsPerCPU)
@@ -451,20 +446,20 @@
.desc("number of demand (read+write) miss cycles")
.flags(total)
;
- demandMissLatency = missLatency[Packet::ReadReq] + missLatency[Packet::WriteReq];
+ demandMissLatency = missLatency[MemCmd::ReadReq] + missLatency[MemCmd::WriteReq];
overallMissLatency
.name(name() + ".overall_miss_latency")
.desc("number of overall miss cycles")
.flags(total)
;
- overallMissLatency = demandMissLatency + missLatency[Packet::SoftPFReq] +
- missLatency[Packet::HardPFReq];
+ overallMissLatency = demandMissLatency + missLatency[MemCmd::SoftPFReq] +
+ missLatency[MemCmd::HardPFReq];
// access formulas
- for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
- Packet::Command cmd = (Packet::Command)access_idx;
- const string &cstr = temp_pkt.cmdIdxToString(cmd);
+ for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
+ MemCmd cmd(access_idx);
+ const string &cstr = cmd.toString();
accesses[access_idx]
.name(name() + "." + cstr + "_accesses")
@@ -490,9 +485,9 @@
overallAccesses = overallHits + overallMisses;
// miss rate formulas
- for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
- Packet::Command cmd = (Packet::Command)access_idx;
- const string &cstr = temp_pkt.cmdIdxToString(cmd);
+ for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
+ MemCmd cmd(access_idx);
+ const string &cstr = cmd.toString();
missRate[access_idx]
.name(name() + "." + cstr + "_miss_rate")
@@ -518,9 +513,9 @@
overallMissRate = overallMisses / overallAccesses;
// miss latency formulas
- for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
- Packet::Command cmd = (Packet::Command)access_idx;
- const string &cstr = temp_pkt.cmdIdxToString(cmd);
+ for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
+ MemCmd cmd(access_idx);
+ const string &cstr = cmd.toString();
avgMissLatency[access_idx]
.name(name() + "." + cstr + "_avg_miss_latency")
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index c10d98e..ee871c1 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -200,14 +200,14 @@
*/
/** Number of hits per thread for each type of command. @sa Packet::Command */
- Stats::Vector<> hits[NUM_MEM_CMDS];
+ Stats::Vector<> hits[MemCmd::NUM_MEM_CMDS];
/** Number of hits for demand accesses. */
Stats::Formula demandHits;
/** Number of hit for all accesses. */
Stats::Formula overallHits;
/** Number of misses per thread for each type of command. @sa Packet::Command */
- Stats::Vector<> misses[NUM_MEM_CMDS];
+ Stats::Vector<> misses[MemCmd::NUM_MEM_CMDS];
/** Number of misses for demand accesses. */
Stats::Formula demandMisses;
/** Number of misses for all accesses. */
@@ -217,28 +217,28 @@
* Total number of cycles per thread/command spent waiting for a miss.
* Used to calculate the average miss latency.
*/
- Stats::Vector<> missLatency[NUM_MEM_CMDS];
+ Stats::Vector<> missLatency[MemCmd::NUM_MEM_CMDS];
/** Total number of cycles spent waiting for demand misses. */
Stats::Formula demandMissLatency;
/** Total number of cycles spent waiting for all misses. */
Stats::Formula overallMissLatency;
/** The number of accesses per command and thread. */
- Stats::Formula accesses[NUM_MEM_CMDS];
+ Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
/** The number of demand accesses. */
Stats::Formula demandAccesses;
/** The number of overall accesses. */
Stats::Formula overallAccesses;
/** The miss rate per command and thread. */
- Stats::Formula missRate[NUM_MEM_CMDS];
+ Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
/** The miss rate of all demand accesses. */
Stats::Formula demandMissRate;
/** The miss rate for all accesses. */
Stats::Formula overallMissRate;
/** The average miss latency per command and thread. */
- Stats::Formula avgMissLatency[NUM_MEM_CMDS];
+ Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
/** The average miss latency for demand misses. */
Stats::Formula demandAvgMissLatency;
/** The average miss latency for all misses. */
@@ -535,7 +535,7 @@
}
}
else {
- if (pkt->cmd != Packet::UpgradeReq)
+ if (pkt->cmd != MemCmd::UpgradeReq)
{
delete pkt->req;
delete pkt;
@@ -594,7 +594,7 @@
}
}
else {
- if (pkt->cmd != Packet::UpgradeReq)
+ if (pkt->cmd != MemCmd::UpgradeReq)
{
delete pkt->req;
delete pkt;
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 10c244b..ff35a07 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -90,7 +90,7 @@
coherence->setCache(this);
prefetcher->setCache(this);
invalidateReq = new Request((Addr) NULL, blkSize, 0);
- invalidatePkt = new Packet(invalidateReq, Packet::InvalidateReq, 0);
+ invalidatePkt = new Packet(invalidateReq, MemCmd::InvalidateReq, 0);
}
template<class TagStore, class Coherence>
@@ -239,7 +239,7 @@
target->flags |= SATISFIED;
- if (target->cmd == Packet::InvalidateReq) {
+ if (target->cmd == MemCmd::InvalidateReq) {
tags->invalidateBlk(blk);
blk = NULL;
}
@@ -316,7 +316,7 @@
Tick completion_time = tags->getHitLatency() +
transfer_offset ? pkt->finishTime : pkt->firstWordTime;
- if (target->cmd == Packet::InvalidateReq) {
+ if (target->cmd == MemCmd::InvalidateReq) {
//Mark the blk as invalid now, if it hasn't been already
if (blk) {
tags->invalidateBlk(blk);
@@ -430,7 +430,7 @@
Request *writebackReq =
new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0);
- PacketPtr writeback = new Packet(writebackReq, Packet::Writeback, -1);
+ PacketPtr writeback = new Packet(writebackReq, MemCmd::Writeback, -1);
writeback->allocate();
std::memcpy(writeback->getPtr<uint8_t>(),blk->data,blkSize);
@@ -555,11 +555,11 @@
/** @todo make the fast write alloc (wh64) work with coherence. */
/** @todo Do we want to do fast writes for writebacks as well? */
if (!blk && pkt->getSize() >= blkSize && coherence->allowFastWrites() &&
- (pkt->cmd == Packet::WriteReq
- || pkt->cmd == Packet::WriteInvalidateReq) ) {
+ (pkt->cmd == MemCmd::WriteReq
+ || pkt->cmd == MemCmd::WriteInvalidateReq) ) {
// not outstanding misses, can do this
MSHR* outstanding_miss = missQueue->findMSHR(pkt->getAddr());
- if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) {
+ if (pkt->cmd == MemCmd::WriteInvalidateReq || !outstanding_miss) {
if (outstanding_miss) {
warn("WriteInv doing a fastallocate"
"with an outstanding miss to the same address\n");
@@ -583,7 +583,7 @@
// clear dirty bit if write through
if (pkt->needsResponse())
respond(pkt, curTick+lat);
- if (pkt->cmd == Packet::Writeback) {
+ if (pkt->cmd == MemCmd::Writeback) {
//Signal that you can kill the pkt/req
pkt->flags |= SATISFIED;
}
@@ -610,7 +610,7 @@
missQueue->handleMiss(pkt, size, curTick + hitLatency);
}
- if (pkt->cmd == Packet::Writeback) {
+ if (pkt->cmd == MemCmd::Writeback) {
//Need to clean up the packet on a writeback miss, but leave the request
delete pkt;
}
@@ -627,11 +627,11 @@
PacketPtr pkt = missQueue->getPacket();
if (pkt) {
if (!pkt->req->isUncacheable()) {
- if (pkt->cmd == Packet::HardPFReq)
- misses[Packet::HardPFReq][0/*pkt->req->getThreadNum()*/]++;
+ if (pkt->cmd == MemCmd::HardPFReq)
+ misses[MemCmd::HardPFReq][0/*pkt->req->getThreadNum()*/]++;
BlkType *blk = tags->findBlock(pkt->getAddr());
- Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
- (blk)? blk->status : 0);
+ MemCmd cmd =
+ coherence->getBusCmd(pkt->cmd, (blk) ? blk->status : 0);
missQueue->setBusCmd(pkt, cmd);
}
}
@@ -650,7 +650,7 @@
if (success && !(SIGNAL_NACK_HACK)) {
//Remember if it was an upgrade because writeback MSHR's are removed
//in Mark in Service
- bool upgrade = (mshr->pkt && mshr->pkt->cmd == Packet::UpgradeReq);
+ bool upgrade = (mshr->pkt && mshr->pkt->cmd == MemCmd::UpgradeReq);
missQueue->markInService(mshr->pkt, mshr);
@@ -775,8 +775,8 @@
if (mshr) {
if (mshr->inService) {
if ((mshr->pkt->isInvalidate() || !mshr->pkt->isCacheFill())
- && (pkt->cmd != Packet::InvalidateReq
- && pkt->cmd != Packet::WriteInvalidateReq)) {
+ && (pkt->cmd != MemCmd::InvalidateReq
+ && pkt->cmd != MemCmd::WriteInvalidateReq)) {
//If the outstanding request was an invalidate
//(upgrade,readex,..) Then we need to ACK the request
//until we get the data Also NACK if the outstanding
@@ -982,11 +982,11 @@
panic("Atomic access ran into outstanding MSHR's or WB's!");
}
if (!pkt->req->isUncacheable() /*Uncacheables just go through*/
- && (pkt->cmd != Packet::Writeback)/*Writebacks on miss fall through*/) {
+ && (pkt->cmd != MemCmd::Writeback)/*Writebacks on miss fall through*/) {
// Fetch the cache block to fill
BlkType *blk = tags->findBlock(pkt->getAddr());
- Packet::Command temp_cmd = coherence->getBusCmd(pkt->cmd,
- (blk)? blk->status : 0);
+ MemCmd temp_cmd =
+ coherence->getBusCmd(pkt->cmd, (blk) ? blk->status : 0);
PacketPtr busPkt = new Packet(pkt->req,temp_cmd, -1, blkSize);
diff --git a/src/mem/cache/coherence/coherence_protocol.cc b/src/mem/cache/coherence/coherence_protocol.cc
index 3d77218..e852040 100644
--- a/src/mem/cache/coherence/coherence_protocol.cc
+++ b/src/mem/cache/coherence/coherence_protocol.cc
@@ -47,7 +47,7 @@
CoherenceProtocol::StateTransition::StateTransition()
- : busCmd(Packet::InvalidCmd), newState(-1), snoopFunc(invalidTransition)
+ : busCmd(MemCmd::InvalidCmd), newState(-1), snoopFunc(invalidTransition)
{
}
@@ -59,132 +59,132 @@
// requestCount and snoopCount arrays, most of these are invalid,
// so we just select the interesting ones to print here.
- requestCount[Invalid][Packet::ReadReq]
+ requestCount[Invalid][MemCmd::ReadReq]
.name(name() + ".read_invalid")
.desc("read misses to invalid blocks")
;
- requestCount[Invalid][Packet::WriteReq]
+ requestCount[Invalid][MemCmd::WriteReq]
.name(name() +".write_invalid")
.desc("write misses to invalid blocks")
;
- requestCount[Invalid][Packet::SoftPFReq]
+ requestCount[Invalid][MemCmd::SoftPFReq]
.name(name() +".swpf_invalid")
.desc("soft prefetch misses to invalid blocks")
;
- requestCount[Invalid][Packet::HardPFReq]
+ requestCount[Invalid][MemCmd::HardPFReq]
.name(name() +".hwpf_invalid")
.desc("hard prefetch misses to invalid blocks")
;
- requestCount[Shared][Packet::WriteReq]
+ requestCount[Shared][MemCmd::WriteReq]
.name(name() + ".write_shared")
.desc("write misses to shared blocks")
;
- requestCount[Owned][Packet::WriteReq]
+ requestCount[Owned][MemCmd::WriteReq]
.name(name() + ".write_owned")
.desc("write misses to owned blocks")
;
- snoopCount[Shared][Packet::ReadReq]
+ snoopCount[Shared][MemCmd::ReadReq]
.name(name() + ".snoop_read_shared")
.desc("read snoops on shared blocks")
;
- snoopCount[Shared][Packet::ReadExReq]
+ snoopCount[Shared][MemCmd::ReadExReq]
.name(name() + ".snoop_readex_shared")
.desc("readEx snoops on shared blocks")
;
- snoopCount[Shared][Packet::UpgradeReq]
+ snoopCount[Shared][MemCmd::UpgradeReq]
.name(name() + ".snoop_upgrade_shared")
.desc("upgradee snoops on shared blocks")
;
- snoopCount[Modified][Packet::ReadReq]
+ snoopCount[Modified][MemCmd::ReadReq]
.name(name() + ".snoop_read_modified")
.desc("read snoops on modified blocks")
;
- snoopCount[Modified][Packet::ReadExReq]
+ snoopCount[Modified][MemCmd::ReadExReq]
.name(name() + ".snoop_readex_modified")
.desc("readEx snoops on modified blocks")
;
- snoopCount[Owned][Packet::ReadReq]
+ snoopCount[Owned][MemCmd::ReadReq]
.name(name() + ".snoop_read_owned")
.desc("read snoops on owned blocks")
;
- snoopCount[Owned][Packet::ReadExReq]
+ snoopCount[Owned][MemCmd::ReadExReq]
.name(name() + ".snoop_readex_owned")
.desc("readEx snoops on owned blocks")
;
- snoopCount[Owned][Packet::UpgradeReq]
+ snoopCount[Owned][MemCmd::UpgradeReq]
.name(name() + ".snoop_upgrade_owned")
.desc("upgrade snoops on owned blocks")
;
- snoopCount[Exclusive][Packet::ReadReq]
+ snoopCount[Exclusive][MemCmd::ReadReq]
.name(name() + ".snoop_read_exclusive")
.desc("read snoops on exclusive blocks")
;
- snoopCount[Exclusive][Packet::ReadExReq]
+ snoopCount[Exclusive][MemCmd::ReadExReq]
.name(name() + ".snoop_readex_exclusive")
.desc("readEx snoops on exclusive blocks")
;
- snoopCount[Shared][Packet::InvalidateReq]
+ snoopCount[Shared][MemCmd::InvalidateReq]
.name(name() + ".snoop_inv_shared")
.desc("Invalidate snoops on shared blocks")
;
- snoopCount[Owned][Packet::InvalidateReq]
+ snoopCount[Owned][MemCmd::InvalidateReq]
.name(name() + ".snoop_inv_owned")
.desc("Invalidate snoops on owned blocks")
;
- snoopCount[Exclusive][Packet::InvalidateReq]
+ snoopCount[Exclusive][MemCmd::InvalidateReq]
.name(name() + ".snoop_inv_exclusive")
.desc("Invalidate snoops on exclusive blocks")
;
- snoopCount[Modified][Packet::InvalidateReq]
+ snoopCount[Modified][MemCmd::InvalidateReq]
.name(name() + ".snoop_inv_modified")
.desc("Invalidate snoops on modified blocks")
;
- snoopCount[Invalid][Packet::InvalidateReq]
+ snoopCount[Invalid][MemCmd::InvalidateReq]
.name(name() + ".snoop_inv_invalid")
.desc("Invalidate snoops on invalid blocks")
;
- snoopCount[Shared][Packet::WriteInvalidateReq]
+ snoopCount[Shared][MemCmd::WriteInvalidateReq]
.name(name() + ".snoop_writeinv_shared")
.desc("WriteInvalidate snoops on shared blocks")
;
- snoopCount[Owned][Packet::WriteInvalidateReq]
+ snoopCount[Owned][MemCmd::WriteInvalidateReq]
.name(name() + ".snoop_writeinv_owned")
.desc("WriteInvalidate snoops on owned blocks")
;
- snoopCount[Exclusive][Packet::WriteInvalidateReq]
+ snoopCount[Exclusive][MemCmd::WriteInvalidateReq]
.name(name() + ".snoop_writeinv_exclusive")
.desc("WriteInvalidate snoops on exclusive blocks")
;
- snoopCount[Modified][Packet::WriteInvalidateReq]
+ snoopCount[Modified][MemCmd::WriteInvalidateReq]
.name(name() + ".snoop_writeinv_modified")
.desc("WriteInvalidate snoops on modified blocks")
;
- snoopCount[Invalid][Packet::WriteInvalidateReq]
+ snoopCount[Invalid][MemCmd::WriteInvalidateReq]
.name(name() + ".snoop_writeinv_invalid")
.desc("WriteInvalidate snoops on invalid blocks")
;
@@ -278,11 +278,13 @@
}
// set up a few shortcuts to save typing & visual clutter
- typedef Packet P;
- StateTransition (&tt)[stateMax+1][NUM_MEM_CMDS] = transitionTable;
+ typedef MemCmd MC;
+ StateTransition (&tt)[stateMax+1][MC::NUM_MEM_CMDS] = transitionTable;
- P::Command writeToSharedCmd = doUpgrades ? P::UpgradeReq : P::ReadExReq;
- P::Command writeToSharedResp = doUpgrades ? P::UpgradeReq : P::ReadExResp;
+ MC::Command writeToSharedCmd =
+ doUpgrades ? MC::UpgradeReq : MC::ReadExReq;
+ MC::Command writeToSharedResp =
+ doUpgrades ? MC::UpgradeReq : MC::ReadExResp;
// Note that all transitions by default cause a panic.
// Override the valid transitions with the appropriate actions here.
@@ -290,34 +292,34 @@
//
// ----- incoming requests: specify outgoing bus request -----
//
- tt[Invalid][P::ReadReq].onRequest(P::ReadReq);
+ tt[Invalid][MC::ReadReq].onRequest(MC::ReadReq);
// we only support write allocate right now
- tt[Invalid][P::WriteReq].onRequest(P::ReadExReq);
- tt[Shared][P::WriteReq].onRequest(writeToSharedCmd);
+ tt[Invalid][MC::WriteReq].onRequest(MC::ReadExReq);
+ tt[Shared][MC::WriteReq].onRequest(writeToSharedCmd);
if (hasOwned) {
- tt[Owned][P::WriteReq].onRequest(writeToSharedCmd);
+ tt[Owned][MC::WriteReq].onRequest(writeToSharedCmd);
}
// Prefetching causes a read
- tt[Invalid][P::SoftPFReq].onRequest(P::ReadReq);
- tt[Invalid][P::HardPFReq].onRequest(P::ReadReq);
+ tt[Invalid][MC::SoftPFReq].onRequest(MC::ReadReq);
+ tt[Invalid][MC::HardPFReq].onRequest(MC::ReadReq);
//
// ----- on response to given request: specify new state -----
//
- tt[Invalid][P::ReadExResp].onResponse(Modified);
+ tt[Invalid][MC::ReadExResp].onResponse(Modified);
tt[Shared][writeToSharedResp].onResponse(Modified);
// Go to Exclusive state on read response if we have one (will
// move into shared if the shared line is asserted in the
// getNewState function)
//
// originally had this as:
- // tt[Invalid][P::ReadResp].onResponse(hasExclusive ? Exclusive: Shared);
+ // tt[Invalid][MC::ReadResp].onResponse(hasExclusive ? Exclusive: Shared);
// ...but for some reason that caused a link error...
if (hasExclusive) {
- tt[Invalid][P::ReadResp].onResponse(Exclusive);
+ tt[Invalid][MC::ReadResp].onResponse(Exclusive);
} else {
- tt[Invalid][P::ReadResp].onResponse(Shared);
+ tt[Invalid][MC::ReadResp].onResponse(Shared);
}
if (hasOwned) {
tt[Owned][writeToSharedResp].onResponse(Modified);
@@ -326,58 +328,58 @@
//
// ----- bus snoop transition functions -----
//
- tt[Invalid][P::ReadReq].onSnoop(nullTransition);
- tt[Invalid][P::ReadExReq].onSnoop(nullTransition);
- tt[Invalid][P::InvalidateReq].onSnoop(invalidateTrans);
- tt[Invalid][P::WriteInvalidateReq].onSnoop(invalidateTrans);
- tt[Shared][P::ReadReq].onSnoop(hasExclusive
+ tt[Invalid][MC::ReadReq].onSnoop(nullTransition);
+ tt[Invalid][MC::ReadExReq].onSnoop(nullTransition);
+ tt[Invalid][MC::InvalidateReq].onSnoop(invalidateTrans);
+ tt[Invalid][MC::WriteInvalidateReq].onSnoop(invalidateTrans);
+ tt[Shared][MC::ReadReq].onSnoop(hasExclusive
? assertShared : nullTransition);
- tt[Shared][P::ReadExReq].onSnoop(invalidateTrans);
- tt[Shared][P::InvalidateReq].onSnoop(invalidateTrans);
- tt[Shared][P::WriteInvalidateReq].onSnoop(invalidateTrans);
+ tt[Shared][MC::ReadExReq].onSnoop(invalidateTrans);
+ tt[Shared][MC::InvalidateReq].onSnoop(invalidateTrans);
+ tt[Shared][MC::WriteInvalidateReq].onSnoop(invalidateTrans);
if (doUpgrades) {
- tt[Invalid][P::UpgradeReq].onSnoop(nullTransition);
- tt[Shared][P::UpgradeReq].onSnoop(invalidateTrans);
+ tt[Invalid][MC::UpgradeReq].onSnoop(nullTransition);
+ tt[Shared][MC::UpgradeReq].onSnoop(invalidateTrans);
}
- tt[Modified][P::ReadExReq].onSnoop(supplyAndInvalidateTrans);
- tt[Modified][P::ReadReq].onSnoop(hasOwned
+ tt[Modified][MC::ReadExReq].onSnoop(supplyAndInvalidateTrans);
+ tt[Modified][MC::ReadReq].onSnoop(hasOwned
? supplyAndGotoOwnedTrans
: supplyAndGotoSharedTrans);
- tt[Modified][P::InvalidateReq].onSnoop(invalidateTrans);
- tt[Modified][P::WriteInvalidateReq].onSnoop(invalidateTrans);
+ tt[Modified][MC::InvalidateReq].onSnoop(invalidateTrans);
+ tt[Modified][MC::WriteInvalidateReq].onSnoop(invalidateTrans);
if (hasExclusive) {
- tt[Exclusive][P::ReadReq].onSnoop(assertShared);
- tt[Exclusive][P::ReadExReq].onSnoop(invalidateTrans);
- tt[Exclusive][P::InvalidateReq].onSnoop(invalidateTrans);
- tt[Exclusive][P::WriteInvalidateReq].onSnoop(invalidateTrans);
+ tt[Exclusive][MC::ReadReq].onSnoop(assertShared);
+ tt[Exclusive][MC::ReadExReq].onSnoop(invalidateTrans);
+ tt[Exclusive][MC::InvalidateReq].onSnoop(invalidateTrans);
+ tt[Exclusive][MC::WriteInvalidateReq].onSnoop(invalidateTrans);
}
if (hasOwned) {
- tt[Owned][P::ReadReq].onSnoop(supplyAndGotoOwnedTrans);
- tt[Owned][P::ReadExReq].onSnoop(supplyAndInvalidateTrans);
- tt[Owned][P::UpgradeReq].onSnoop(invalidateTrans);
- tt[Owned][P::InvalidateReq].onSnoop(invalidateTrans);
- tt[Owned][P::WriteInvalidateReq].onSnoop(invalidateTrans);
+ tt[Owned][MC::ReadReq].onSnoop(supplyAndGotoOwnedTrans);
+ tt[Owned][MC::ReadExReq].onSnoop(supplyAndInvalidateTrans);
+ tt[Owned][MC::UpgradeReq].onSnoop(invalidateTrans);
+ tt[Owned][MC::InvalidateReq].onSnoop(invalidateTrans);
+ tt[Owned][MC::WriteInvalidateReq].onSnoop(invalidateTrans);
}
// @todo add in hardware prefetch to this list
}
-Packet::Command
-CoherenceProtocol::getBusCmd(Packet::Command cmdIn, CacheBlk::State state,
+MemCmd
+CoherenceProtocol::getBusCmd(MemCmd cmdIn, CacheBlk::State state,
MSHR *mshr)
{
state &= stateMask;
- int cmd_idx = (int) cmdIn;
+ int cmd_idx = cmdIn.toInt();
assert(0 <= state && state <= stateMax);
- assert(0 <= cmd_idx && cmd_idx < NUM_MEM_CMDS);
+ assert(0 <= cmd_idx && cmd_idx < MemCmd::NUM_MEM_CMDS);
- Packet::Command cmdOut = transitionTable[state][cmd_idx].busCmd;
+ MemCmd::Command cmdOut = transitionTable[state][cmd_idx].busCmd;
- assert(cmdOut != Packet::InvalidCmd);
+ assert(cmdOut != MemCmd::InvalidCmd);
++requestCount[state][cmd_idx];
@@ -392,7 +394,7 @@
int cmd_idx = pkt->cmdToIndex();
assert(0 <= state && state <= stateMax);
- assert(0 <= cmd_idx && cmd_idx < NUM_MEM_CMDS);
+ assert(0 <= cmd_idx && cmd_idx < MemCmd::NUM_MEM_CMDS);
CacheBlk::State newState = transitionTable[state][cmd_idx].newState;
@@ -425,7 +427,7 @@
int cmd_idx = pkt->cmdToIndex();
assert(0 <= state && state <= stateMax);
- assert(0 <= cmd_idx && cmd_idx < NUM_MEM_CMDS);
+ assert(0 <= cmd_idx && cmd_idx < MemCmd::NUM_MEM_CMDS);
// assert(mshr == NULL); // can't currently handle outstanding requests
//Check first if MSHR, and also insure, if there is one, that it is not in service
diff --git a/src/mem/cache/coherence/coherence_protocol.hh b/src/mem/cache/coherence/coherence_protocol.hh
index 4812775..775bc80 100644
--- a/src/mem/cache/coherence/coherence_protocol.hh
+++ b/src/mem/cache/coherence/coherence_protocol.hh
@@ -80,8 +80,8 @@
* @param mshr The MSHR matching the request.
* @return The proper bus command, as determined by the protocol.
*/
- Packet::Command getBusCmd(Packet::Command cmd, CacheBlk::State status,
- MSHR *mshr = NULL);
+ MemCmd getBusCmd(MemCmd cmd, CacheBlk::State status,
+ MSHR *mshr = NULL);
/**
* Return the proper state given the current state and the bus response.
@@ -235,7 +235,7 @@
* The table of all possible transitions, organized by starting state and
* request command.
*/
- StateTransition transitionTable[stateMax+1][NUM_MEM_CMDS];
+ StateTransition transitionTable[stateMax+1][MemCmd::NUM_MEM_CMDS];
/**
* @addtogroup CoherenceStatistics
@@ -244,11 +244,11 @@
/**
* State accesses from parent cache.
*/
- Stats::Scalar<> requestCount[stateMax+1][NUM_MEM_CMDS];
+ Stats::Scalar<> requestCount[stateMax+1][MemCmd::NUM_MEM_CMDS];
/**
* State accesses from snooped requests.
*/
- Stats::Scalar<> snoopCount[stateMax+1][NUM_MEM_CMDS];
+ Stats::Scalar<> snoopCount[stateMax+1][MemCmd::NUM_MEM_CMDS];
/**
* @}
*/
diff --git a/src/mem/cache/coherence/simple_coherence.hh b/src/mem/cache/coherence/simple_coherence.hh
index a1fd330..1c89c70 100644
--- a/src/mem/cache/coherence/simple_coherence.hh
+++ b/src/mem/cache/coherence/simple_coherence.hh
@@ -131,7 +131,7 @@
//Got rid of, there could be an MSHR, but it can't be in service
if (blk != NULL)
{
- if (pkt->cmd != Packet::Writeback) {
+ if (pkt->cmd != MemCmd::Writeback) {
return protocol->handleBusRequest(cache, pkt, blk, mshr,
new_state);
}
@@ -148,9 +148,10 @@
* @param state The current state of the cache block.
* @return The proper bus command, as determined by the protocol.
*/
- Packet::Command getBusCmd(Packet::Command &cmd, CacheBlk::State state)
+ MemCmd getBusCmd(MemCmd cmd,
+ CacheBlk::State state)
{
- if (cmd == Packet::Writeback) return Packet::Writeback;
+ if (cmd == MemCmd::Writeback) return MemCmd::Writeback;
return protocol->getBusCmd(cmd, state);
}
diff --git a/src/mem/cache/coherence/uni_coherence.cc b/src/mem/cache/coherence/uni_coherence.cc
index ea615d7..6061c89 100644
--- a/src/mem/cache/coherence/uni_coherence.cc
+++ b/src/mem/cache/coherence/uni_coherence.cc
@@ -99,19 +99,19 @@
if (isTiming) {
// Forward to other caches
Request* req = new Request(pkt->req->getPaddr(), pkt->getSize(), 0);
- PacketPtr tmp = new Packet(req, Packet::InvalidateReq, -1);
+ PacketPtr tmp = new Packet(req, MemCmd::InvalidateReq, -1);
cshrs.allocate(tmp);
cache->setSlaveRequest(Request_Coherence, curTick);
if (cshrs.isFull())
cache->setBlockedForSnoop(Blocked_Coherence);
}
else {
- PacketPtr tmp = new Packet(pkt->req, Packet::InvalidateReq, -1);
+ PacketPtr tmp = new Packet(pkt->req, MemCmd::InvalidateReq, -1);
cache->cpuSidePort->sendAtomic(tmp);
delete tmp;
}
/**/
-/* PacketPtr tmp = new Packet(pkt->req, Packet::InvalidateReq, -1);
+/* PacketPtr tmp = new Packet(pkt->req, MemCmd::InvalidateReq, -1);
cache->cpuSidePort->sendFunctional(tmp);
delete tmp;
*/
@@ -119,7 +119,7 @@
if (pkt->isRead()) {
/*For now we will see if someone above us has the data by
doing a functional access on reads. Fix this later */
- PacketPtr tmp = new Packet(pkt->req, Packet::ReadReq, -1);
+ PacketPtr tmp = new Packet(pkt->req, MemCmd::ReadReq, -1);
tmp->allocate();
cache->cpuSidePort->sendFunctional(tmp);
bool hit = (tmp->result == Packet::Success);
diff --git a/src/mem/cache/coherence/uni_coherence.hh b/src/mem/cache/coherence/uni_coherence.hh
index 9a4aacd..9efb4e1 100644
--- a/src/mem/cache/coherence/uni_coherence.hh
+++ b/src/mem/cache/coherence/uni_coherence.hh
@@ -77,13 +77,13 @@
* @return The proper bus command, as determined by the protocol.
* @todo Make changes so writebacks don't get here.
*/
- Packet::Command getBusCmd(Packet::Command &cmd, CacheBlk::State state)
+ MemCmd getBusCmd(MemCmd cmd, CacheBlk::State state)
{
- if (cmd == Packet::HardPFReq && state)
+ if (cmd == MemCmd::HardPFReq && state)
warn("Trying to issue a prefetch to a block we already have\n");
- if (cmd == Packet::Writeback)
- return Packet::Writeback;
- return Packet::ReadReq;
+ if (cmd == MemCmd::Writeback)
+ return MemCmd::Writeback;
+ return MemCmd::ReadReq;
}
/**
@@ -96,7 +96,7 @@
{
if (pkt->senderState) //Blocking Buffers don't get mshrs
{
- if (((MSHR *)(pkt->senderState))->originalCmd == Packet::HardPFReq) {
+ if (((MSHR *)(pkt->senderState))->originalCmd == MemCmd::HardPFReq) {
DPRINTF(HWPrefetch, "Marking a hardware prefetch as such in the state\n");
return BlkHWPrefetched | BlkValid | BlkWritable;
}
diff --git a/src/mem/cache/miss/blocking_buffer.cc b/src/mem/cache/miss/blocking_buffer.cc
index a1af883..e8ff268 100644
--- a/src/mem/cache/miss/blocking_buffer.cc
+++ b/src/mem/cache/miss/blocking_buffer.cc
@@ -90,7 +90,7 @@
}
void
-BlockingBuffer::setBusCmd(PacketPtr &pkt, Packet::Command cmd)
+BlockingBuffer::setBusCmd(PacketPtr &pkt, MemCmd cmd)
{
MSHR *mshr = (MSHR*) pkt->senderState;
mshr->originalCmd = pkt->cmd;
@@ -189,7 +189,7 @@
{
// Generate request
Request * req = new Request(addr, size, 0);
- PacketPtr pkt = new Packet(req, Packet::Writeback, -1);
+ PacketPtr pkt = new Packet(req, MemCmd::Writeback, -1);
pkt->allocate();
if (data) {
std::memcpy(pkt->getPtr<uint8_t>(), data, size);
diff --git a/src/mem/cache/miss/blocking_buffer.hh b/src/mem/cache/miss/blocking_buffer.hh
index 24386a2..86b24d5 100644
--- a/src/mem/cache/miss/blocking_buffer.hh
+++ b/src/mem/cache/miss/blocking_buffer.hh
@@ -104,7 +104,7 @@
* @param pkt The request to update.
* @param cmd The bus command to use.
*/
- void setBusCmd(PacketPtr &pkt, Packet::Command cmd);
+ void setBusCmd(PacketPtr &pkt, MemCmd cmd);
/**
* Restore the original command in case of a bus transmission error.
diff --git a/src/mem/cache/miss/miss_buffer.hh b/src/mem/cache/miss/miss_buffer.hh
index 3e30805..9a86db3 100644
--- a/src/mem/cache/miss/miss_buffer.hh
+++ b/src/mem/cache/miss/miss_buffer.hh
@@ -123,7 +123,7 @@
* @param pkt The request to update.
* @param cmd The bus command to use.
*/
- virtual void setBusCmd(PacketPtr &pkt, Packet::Command cmd) = 0;
+ virtual void setBusCmd(PacketPtr &pkt, MemCmd cmd) = 0;
/**
* Restore the original command in case of a bus transmission error.
diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc
index 1d3e223..25b8fcb 100644
--- a/src/mem/cache/miss/miss_queue.cc
+++ b/src/mem/cache/miss/miss_queue.cc
@@ -67,17 +67,12 @@
{
MissBuffer::regStats(name);
- Request temp_req((Addr) NULL, 4, 0);
- Packet::Command temp_cmd = Packet::ReadReq;
- Packet temp_pkt(&temp_req, temp_cmd, 0); //@todo FIx command strings so this isn't neccessary
- temp_pkt.allocate();
-
using namespace Stats;
// MSHR hit statistics
- for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
- Packet::Command cmd = (Packet::Command)access_idx;
- const string &cstr = temp_pkt.cmdIdxToString(cmd);
+ for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
+ MemCmd cmd(access_idx);
+ const string &cstr = cmd.toString();
mshr_hits[access_idx]
.init(maxThreadsPerCPU)
@@ -92,20 +87,20 @@
.desc("number of demand (read+write) MSHR hits")
.flags(total)
;
- demandMshrHits = mshr_hits[Packet::ReadReq] + mshr_hits[Packet::WriteReq];
+ demandMshrHits = mshr_hits[MemCmd::ReadReq] + mshr_hits[MemCmd::WriteReq];
overallMshrHits
.name(name + ".overall_mshr_hits")
.desc("number of overall MSHR hits")
.flags(total)
;
- overallMshrHits = demandMshrHits + mshr_hits[Packet::SoftPFReq] +
- mshr_hits[Packet::HardPFReq];
+ overallMshrHits = demandMshrHits + mshr_hits[MemCmd::SoftPFReq] +
+ mshr_hits[MemCmd::HardPFReq];
// MSHR miss statistics
- for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
- Packet::Command cmd = (Packet::Command)access_idx;
- const string &cstr = temp_pkt.cmdIdxToString(cmd);
+ for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
+ MemCmd cmd(access_idx);
+ const string &cstr = cmd.toString();
mshr_misses[access_idx]
.init(maxThreadsPerCPU)
@@ -120,20 +115,20 @@
.desc("number of demand (read+write) MSHR misses")
.flags(total)
;
- demandMshrMisses = mshr_misses[Packet::ReadReq] + mshr_misses[Packet::WriteReq];
+ demandMshrMisses = mshr_misses[MemCmd::ReadReq] + mshr_misses[MemCmd::WriteReq];
overallMshrMisses
.name(name + ".overall_mshr_misses")
.desc("number of overall MSHR misses")
.flags(total)
;
- overallMshrMisses = demandMshrMisses + mshr_misses[Packet::SoftPFReq] +
- mshr_misses[Packet::HardPFReq];
+ overallMshrMisses = demandMshrMisses + mshr_misses[MemCmd::SoftPFReq] +
+ mshr_misses[MemCmd::HardPFReq];
// MSHR miss latency statistics
- for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
- Packet::Command cmd = (Packet::Command)access_idx;
- const string &cstr = temp_pkt.cmdIdxToString(cmd);
+ for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
+ MemCmd cmd(access_idx);
+ const string &cstr = cmd.toString();
mshr_miss_latency[access_idx]
.init(maxThreadsPerCPU)
@@ -148,8 +143,8 @@
.desc("number of demand (read+write) MSHR miss cycles")
.flags(total)
;
- demandMshrMissLatency = mshr_miss_latency[Packet::ReadReq]
- + mshr_miss_latency[Packet::WriteReq];
+ demandMshrMissLatency = mshr_miss_latency[MemCmd::ReadReq]
+ + mshr_miss_latency[MemCmd::WriteReq];
overallMshrMissLatency
.name(name + ".overall_mshr_miss_latency")
@@ -157,12 +152,12 @@
.flags(total)
;
overallMshrMissLatency = demandMshrMissLatency +
- mshr_miss_latency[Packet::SoftPFReq] + mshr_miss_latency[Packet::HardPFReq];
+ mshr_miss_latency[MemCmd::SoftPFReq] + mshr_miss_latency[MemCmd::HardPFReq];
// MSHR uncacheable statistics
- for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
- Packet::Command cmd = (Packet::Command)access_idx;
- const string &cstr = temp_pkt.cmdIdxToString(cmd);
+ for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
+ MemCmd cmd(access_idx);
+ const string &cstr = cmd.toString();
mshr_uncacheable[access_idx]
.init(maxThreadsPerCPU)
@@ -177,14 +172,14 @@
.desc("number of overall MSHR uncacheable misses")
.flags(total)
;
- overallMshrUncacheable = mshr_uncacheable[Packet::ReadReq]
- + mshr_uncacheable[Packet::WriteReq] + mshr_uncacheable[Packet::SoftPFReq]
- + mshr_uncacheable[Packet::HardPFReq];
+ overallMshrUncacheable = mshr_uncacheable[MemCmd::ReadReq]
+ + mshr_uncacheable[MemCmd::WriteReq] + mshr_uncacheable[MemCmd::SoftPFReq]
+ + mshr_uncacheable[MemCmd::HardPFReq];
// MSHR miss latency statistics
- for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
- Packet::Command cmd = (Packet::Command)access_idx;
- const string &cstr = temp_pkt.cmdIdxToString(cmd);
+ for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
+ MemCmd cmd(access_idx);
+ const string &cstr = cmd.toString();
mshr_uncacheable_lat[access_idx]
.init(maxThreadsPerCPU)
@@ -199,16 +194,16 @@
.desc("number of overall MSHR uncacheable cycles")
.flags(total)
;
- overallMshrUncacheableLatency = mshr_uncacheable_lat[Packet::ReadReq]
- + mshr_uncacheable_lat[Packet::WriteReq]
- + mshr_uncacheable_lat[Packet::SoftPFReq]
- + mshr_uncacheable_lat[Packet::HardPFReq];
+ overallMshrUncacheableLatency = mshr_uncacheable_lat[MemCmd::ReadReq]
+ + mshr_uncacheable_lat[MemCmd::WriteReq]
+ + mshr_uncacheable_lat[MemCmd::SoftPFReq]
+ + mshr_uncacheable_lat[MemCmd::HardPFReq];
#if 0
// MSHR access formulas
- for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
- Packet::Command cmd = (Packet::Command)access_idx;
- const string &cstr = temp_pkt.cmdIdxToString(cmd);
+ for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
+ MemCmd cmd(access_idx);
+ const string &cstr = cmd.toString();
mshrAccesses[access_idx]
.name(name + "." + cstr + "_mshr_accesses")
@@ -237,9 +232,9 @@
#endif
// MSHR miss rate formulas
- for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
- Packet::Command cmd = (Packet::Command)access_idx;
- const string &cstr = temp_pkt.cmdIdxToString(cmd);
+ for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
+ MemCmd cmd(access_idx);
+ const string &cstr = cmd.toString();
mshrMissRate[access_idx]
.name(name + "." + cstr + "_mshr_miss_rate")
@@ -266,9 +261,9 @@
overallMshrMissRate = overallMshrMisses / cache->overallAccesses;
// mshrMiss latency formulas
- for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
- Packet::Command cmd = (Packet::Command)access_idx;
- const string &cstr = temp_pkt.cmdIdxToString(cmd);
+ for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
+ MemCmd cmd(access_idx);
+ const string &cstr = cmd.toString();
avgMshrMissLatency[access_idx]
.name(name + "." + cstr + "_avg_mshr_miss_latency")
@@ -295,9 +290,9 @@
overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses;
// mshrUncacheable latency formulas
- for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
- Packet::Command cmd = (Packet::Command)access_idx;
- const string &cstr = temp_pkt.cmdIdxToString(cmd);
+ for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
+ MemCmd cmd(access_idx);
+ const string &cstr = cmd.toString();
avgMshrUncacheableLatency[access_idx]
.name(name + "." + cstr + "_avg_mshr_uncacheable_latency")
@@ -351,7 +346,7 @@
if (mq.isFull()) {
cache->setBlocked(Blocked_NoMSHRs);
}
- if (pkt->cmd != Packet::HardPFReq) {
+ if (pkt->cmd != MemCmd::HardPFReq) {
//If we need to request the bus (not on HW prefetch), do so
cache->setMasterRequest(Request_MSHR, time);
}
@@ -500,17 +495,17 @@
}
void
-MissQueue::setBusCmd(PacketPtr &pkt, Packet::Command cmd)
+MissQueue::setBusCmd(PacketPtr &pkt, MemCmd cmd)
{
assert(pkt->senderState != 0);
MSHR * mshr = (MSHR*)pkt->senderState;
mshr->originalCmd = pkt->cmd;
- if (cmd == Packet::UpgradeReq || cmd == Packet::InvalidateReq) {
+ if (cmd == MemCmd::UpgradeReq || cmd == MemCmd::InvalidateReq) {
pkt->flags |= NO_ALLOCATE;
pkt->flags &= ~CACHE_LINE_FILL;
}
else if (!pkt->req->isUncacheable() && !pkt->isNoAllocate() &&
- (cmd & (1 << 6)/*NeedsResponse*/)) {
+ cmd.needsResponse()) {
pkt->flags |= CACHE_LINE_FILL;
}
if (pkt->isCacheFill() || pkt->isNoAllocate())
@@ -552,7 +547,7 @@
if (!mq.havePending()){
cache->clearMasterRequest(Request_MSHR);
}
- if (mshr->originalCmd == Packet::HardPFReq) {
+ if (mshr->originalCmd == MemCmd::HardPFReq) {
DPRINTF(HWPrefetch, "%s:Marking a HW_PF in service\n",
cache->name());
//Also clear pending if need be
@@ -576,7 +571,7 @@
MissQueue::handleResponse(PacketPtr &pkt, Tick time)
{
MSHR* mshr = (MSHR*)pkt->senderState;
- if (((MSHR*)(pkt->senderState))->originalCmd == Packet::HardPFReq) {
+ if (((MSHR*)(pkt->senderState))->originalCmd == MemCmd::HardPFReq) {
DPRINTF(HWPrefetch, "%s:Handling the response to a HW_PF\n",
cache->name());
}
@@ -589,7 +584,7 @@
BlockedCause cause = NUM_BLOCKED_CAUSES;
if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
- mshr_miss_latency[mshr->originalCmd][0/*pkt->req->getThreadNum()*/] +=
+ mshr_miss_latency[mshr->originalCmd.toInt()][0/*pkt->req->getThreadNum()*/] +=
curTick - pkt->time;
// targets were handled in the cache tags
if (mshr == noTargetMSHR) {
@@ -601,7 +596,7 @@
if (mshr->hasTargets()) {
// Didn't satisfy all the targets, need to resend
- Packet::Command cmd = mshr->getTarget()->cmd;
+ MemCmd cmd = mshr->getTarget()->cmd;
mshr->pkt->setDest(Packet::Broadcast);
mshr->pkt->result = Packet::Unknown;
mq.markPending(mshr, cmd);
@@ -618,7 +613,7 @@
}
} else {
if (pkt->req->isUncacheable()) {
- mshr_uncacheable_lat[pkt->cmd][0/*pkt->req->getThreadNum()*/] +=
+ mshr_uncacheable_lat[pkt->cmd.toInt()][0/*pkt->req->getThreadNum()*/] +=
curTick - pkt->time;
}
if (mshr->hasTargets() && pkt->req->isUncacheable()) {
@@ -713,7 +708,7 @@
{
// Generate request
Request * req = new Request(addr, size, 0);
- PacketPtr pkt = new Packet(req, Packet::Writeback, -1);
+ PacketPtr pkt = new Packet(req, MemCmd::Writeback, -1);
pkt->allocate();
if (data) {
memcpy(pkt->getPtr<uint8_t>(), data, size);
diff --git a/src/mem/cache/miss/miss_queue.hh b/src/mem/cache/miss/miss_queue.hh
index 1f9bb1e..d3560ff 100644
--- a/src/mem/cache/miss/miss_queue.hh
+++ b/src/mem/cache/miss/miss_queue.hh
@@ -77,59 +77,59 @@
* @{
*/
/** Number of misses that hit in the MSHRs per command and thread. */
- Stats::Vector<> mshr_hits[NUM_MEM_CMDS];
+ Stats::Vector<> mshr_hits[MemCmd::NUM_MEM_CMDS];
/** Demand misses that hit in the MSHRs. */
Stats::Formula demandMshrHits;
/** Total number of misses that hit in the MSHRs. */
Stats::Formula overallMshrHits;
/** Number of misses that miss in the MSHRs, per command and thread. */
- Stats::Vector<> mshr_misses[NUM_MEM_CMDS];
+ Stats::Vector<> mshr_misses[MemCmd::NUM_MEM_CMDS];
/** Demand misses that miss in the MSHRs. */
Stats::Formula demandMshrMisses;
/** Total number of misses that miss in the MSHRs. */
Stats::Formula overallMshrMisses;
/** Number of misses that miss in the MSHRs, per command and thread. */
- Stats::Vector<> mshr_uncacheable[NUM_MEM_CMDS];
+ Stats::Vector<> mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
/** Total number of misses that miss in the MSHRs. */
Stats::Formula overallMshrUncacheable;
/** Total cycle latency of each MSHR miss, per command and thread. */
- Stats::Vector<> mshr_miss_latency[NUM_MEM_CMDS];
+ Stats::Vector<> mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
/** Total cycle latency of demand MSHR misses. */
Stats::Formula demandMshrMissLatency;
/** Total cycle latency of overall MSHR misses. */
Stats::Formula overallMshrMissLatency;
/** Total cycle latency of each MSHR miss, per command and thread. */
- Stats::Vector<> mshr_uncacheable_lat[NUM_MEM_CMDS];
+ Stats::Vector<> mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
/** Total cycle latency of overall MSHR misses. */
Stats::Formula overallMshrUncacheableLatency;
/** The total number of MSHR accesses per command and thread. */
- Stats::Formula mshrAccesses[NUM_MEM_CMDS];
+ Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
/** The total number of demand MSHR accesses. */
Stats::Formula demandMshrAccesses;
/** The total number of MSHR accesses. */
Stats::Formula overallMshrAccesses;
/** The miss rate in the MSHRs pre command and thread. */
- Stats::Formula mshrMissRate[NUM_MEM_CMDS];
+ Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
/** The demand miss rate in the MSHRs. */
Stats::Formula demandMshrMissRate;
/** The overall miss rate in the MSHRs. */
Stats::Formula overallMshrMissRate;
/** The average latency of an MSHR miss, per command and thread. */
- Stats::Formula avgMshrMissLatency[NUM_MEM_CMDS];
+ Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
/** The average latency of a demand MSHR miss. */
Stats::Formula demandAvgMshrMissLatency;
/** The average overall latency of an MSHR miss. */
Stats::Formula overallAvgMshrMissLatency;
/** The average latency of an MSHR miss, per command and thread. */
- Stats::Formula avgMshrUncacheableLatency[NUM_MEM_CMDS];
+ Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
/** The average overall latency of an MSHR miss. */
Stats::Formula overallAvgMshrUncacheableLatency;
@@ -220,7 +220,7 @@
* @param pkt The request to update.
* @param cmd The bus command to use.
*/
- void setBusCmd(PacketPtr &pkt, Packet::Command cmd);
+ void setBusCmd(PacketPtr &pkt, MemCmd cmd);
/**
* Restore the original command in case of a bus transmission error.
diff --git a/src/mem/cache/miss/mshr.cc b/src/mem/cache/miss/mshr.cc
index fc520b4..352d1ec 100644
--- a/src/mem/cache/miss/mshr.cc
+++ b/src/mem/cache/miss/mshr.cc
@@ -54,7 +54,7 @@
}
void
-MSHR::allocate(Packet::Command cmd, Addr _addr, int size,
+MSHR::allocate(MemCmd cmd, Addr _addr, int size,
PacketPtr &target)
{
addr = _addr;
@@ -148,7 +148,7 @@
*/
if (!inService && target->isWrite()) {
- pkt->cmd = Packet::WriteReq;
+ pkt->cmd = MemCmd::WriteReq;
}
}
diff --git a/src/mem/cache/miss/mshr.hh b/src/mem/cache/miss/mshr.hh
index 281ea9d..d0410ac 100644
--- a/src/mem/cache/miss/mshr.hh
+++ b/src/mem/cache/miss/mshr.hh
@@ -72,7 +72,7 @@
/** The number of currently allocated targets. */
short ntargets;
/** The original requesting command. */
- Packet::Command originalCmd;
+ MemCmd originalCmd;
/** Order number of assigned by the miss queue. */
uint64_t order;
@@ -100,7 +100,7 @@
* @param size The number of bytes to request.
* @param pkt The original miss.
*/
- void allocate(Packet::Command cmd, Addr addr, int size,
+ void allocate(MemCmd cmd, Addr addr, int size,
PacketPtr &pkt);
/**
diff --git a/src/mem/cache/miss/mshr_queue.cc b/src/mem/cache/miss/mshr_queue.cc
index 6cb6242..add11df 100644
--- a/src/mem/cache/miss/mshr_queue.cc
+++ b/src/mem/cache/miss/mshr_queue.cc
@@ -136,7 +136,7 @@
MSHR *mshr = freeList.front();
assert(mshr->getNumTargets() == 0);
freeList.pop_front();
- mshr->allocate(Packet::ReadReq, addr, size, target);
+ mshr->allocate(MemCmd::ReadReq, addr, size, target);
mshr->allocIter = allocatedList.insert(allocatedList.end(), mshr);
mshr->readyIter = pendingList.insert(pendingList.end(), mshr);
@@ -151,7 +151,7 @@
assert(mshr->getNumTargets() == 0);
freeList.pop_front();
PacketPtr dummy;
- mshr->allocate(Packet::ReadReq, addr, size, dummy);
+ mshr->allocate(MemCmd::ReadReq, addr, size, dummy);
mshr->allocIter = allocatedList.insert(allocatedList.end(), mshr);
mshr->inService = true;
++inServiceMSHRs;
@@ -196,7 +196,7 @@
MSHRQueue::markInService(MSHR* mshr)
{
//assert(mshr == pendingList.front());
- if (!mshr->pkt->needsResponse() && !(mshr->pkt->cmd == Packet::UpgradeReq)) {
+ if (!mshr->pkt->needsResponse() && !(mshr->pkt->cmd == MemCmd::UpgradeReq)) {
assert(mshr->getNumTargets() == 0);
deallocate(mshr);
return;
@@ -209,7 +209,7 @@
}
void
-MSHRQueue::markPending(MSHR* mshr, Packet::Command cmd)
+MSHRQueue::markPending(MSHR* mshr, MemCmd cmd)
{
//assert(mshr->readyIter == NULL);
mshr->pkt->cmd = cmd;
diff --git a/src/mem/cache/miss/mshr_queue.hh b/src/mem/cache/miss/mshr_queue.hh
index ec2ddae..5069db6 100644
--- a/src/mem/cache/miss/mshr_queue.hh
+++ b/src/mem/cache/miss/mshr_queue.hh
@@ -185,7 +185,7 @@
* @param mshr The MSHR to resend.
* @param cmd The command to resend.
*/
- void markPending(MSHR* mshr, Packet::Command cmd);
+ void markPending(MSHR* mshr, MemCmd cmd);
/**
* Squash outstanding requests with the given thread number. If a request
diff --git a/src/mem/cache/prefetch/base_prefetcher.cc b/src/mem/cache/prefetch/base_prefetcher.cc
index 4254800..44daf75 100644
--- a/src/mem/cache/prefetch/base_prefetcher.cc
+++ b/src/mem/cache/prefetch/base_prefetcher.cc
@@ -200,7 +200,7 @@
//create a prefetch memreq
Request * prefetchReq = new Request(*addr, blkSize, 0);
PacketPtr prefetch;
- prefetch = new Packet(prefetchReq, Packet::HardPFReq, -1);
+ prefetch = new Packet(prefetchReq, MemCmd::HardPFReq, -1);
prefetch->allocate();
prefetch->req->setThreadContext(pkt->req->getCpuNum(),
pkt->req->getThreadNum());
diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc
index e547e11..20e2ef0 100644
--- a/src/mem/cache/tags/iic.cc
+++ b/src/mem/cache/tags/iic.cc
@@ -372,7 +372,8 @@
*/
Request *writebackReq = new Request(regenerateBlkAddr(tag_ptr->tag, 0),
blkSize, 0);
- PacketPtr writeback = new Packet(writebackReq, Packet::Writeback, -1);
+ PacketPtr writeback = new Packet(writebackReq, MemCmd::Writeback,
+ -1);
writeback->allocate();
memcpy(writeback->getPtr<uint8_t>(), tag_ptr->data, blkSize);
diff --git a/src/mem/packet.cc b/src/mem/packet.cc
index 4480523..dde6c00 100644
--- a/src/mem/packet.cc
+++ b/src/mem/packet.cc
@@ -41,68 +41,62 @@
#include "base/trace.hh"
#include "mem/packet.hh"
-static const std::string ReadReqString("ReadReq");
-static const std::string WriteReqString("WriteReq");
-static const std::string WriteReqNoAckString("WriteReqNoAck|Writeback");
-static const std::string ReadRespString("ReadResp");
-static const std::string WriteRespString("WriteResp");
-static const std::string SoftPFReqString("SoftPFReq");
-static const std::string SoftPFRespString("SoftPFResp");
-static const std::string HardPFReqString("HardPFReq");
-static const std::string HardPFRespString("HardPFResp");
-static const std::string InvalidateReqString("InvalidateReq");
-static const std::string WriteInvalidateReqString("WriteInvalidateReq");
-static const std::string WriteInvalidateRespString("WriteInvalidateResp");
-static const std::string UpgradeReqString("UpgradeReq");
-static const std::string ReadExReqString("ReadExReq");
-static const std::string ReadExRespString("ReadExResp");
-static const std::string OtherCmdString("<other>");
+// The one downside to bitsets is that static initializers can get ugly.
+#define SET1(a1) (1 << (a1))
+#define SET2(a1, a2) (SET1(a1) | SET1(a2))
+#define SET3(a1, a2, a3) (SET2(a1, a2) | SET1(a3))
+#define SET4(a1, a2, a3, a4) (SET3(a1, a2, a3) | SET1(a4))
+#define SET5(a1, a2, a3, a4, a5) (SET4(a1, a2, a3, a4) | SET1(a5))
+#define SET6(a1, a2, a3, a4, a5, a6) (SET5(a1, a2, a3, a4, a5) | SET1(a6))
-const std::string &
-Packet::cmdString() const
+const MemCmd::CommandInfo
+MemCmd::commandInfo[] =
{
- switch (cmd) {
- case ReadReq: return ReadReqString;
- case WriteReq: return WriteReqString;
- case WriteReqNoAck: return WriteReqNoAckString;
- case ReadResp: return ReadRespString;
- case WriteResp: return WriteRespString;
- case SoftPFReq: return SoftPFReqString;
- case SoftPFResp: return SoftPFRespString;
- case HardPFReq: return HardPFReqString;
- case HardPFResp: return HardPFRespString;
- case InvalidateReq: return InvalidateReqString;
- case WriteInvalidateReq:return WriteInvalidateReqString;
- case WriteInvalidateResp:return WriteInvalidateRespString;
- case UpgradeReq: return UpgradeReqString;
- case ReadExReq: return ReadExReqString;
- case ReadExResp: return ReadExRespString;
- default: return OtherCmdString;
- }
-}
+ /* InvalidCmd */
+ { 0, InvalidCmd, "InvalidCmd" },
+ /* ReadReq */
+ { SET3(IsRead, IsRequest, NeedsResponse), ReadResp, "ReadReq" },
+ /* WriteReq */
+ { SET4(IsWrite, IsRequest, NeedsResponse, HasData),
+ WriteResp, "WriteReq" },
+ /* WriteReqNoAck */
+ { SET3(IsWrite, IsRequest, HasData), InvalidCmd, "WriteReqNoAck" },
+ /* ReadResp */
+ { SET3(IsRead, IsResponse, HasData), InvalidCmd, "ReadResp" },
+ /* WriteResp */
+ { SET2(IsWrite, IsResponse), InvalidCmd, "WriteResp" },
+ /* Writeback */
+ { SET3(IsWrite, IsRequest, HasData), InvalidCmd, "Writeback" },
+ /* SoftPFReq */
+ { SET4(IsRead, IsRequest, IsSWPrefetch, NeedsResponse),
+ SoftPFResp, "SoftPFReq" },
+ /* HardPFReq */
+ { SET4(IsRead, IsRequest, IsHWPrefetch, NeedsResponse),
+ HardPFResp, "HardPFReq" },
+ /* SoftPFResp */
+ { SET4(IsRead, IsResponse, IsSWPrefetch, HasData),
+ InvalidCmd, "SoftPFResp" },
+ /* HardPFResp */
+ { SET4(IsRead, IsResponse, IsHWPrefetch, HasData),
+ InvalidCmd, "HardPFResp" },
+ /* InvalidateReq */
+ { SET2(IsInvalidate, IsRequest), InvalidCmd, "InvalidateReq" },
+ /* WriteInvalidateReq */
+ { SET5(IsWrite, IsInvalidate, IsRequest, HasData, NeedsResponse),
+ WriteInvalidateResp, "WriteInvalidateReq" },
+ /* WriteInvalidateResp */
+ { SET5(IsWrite, IsInvalidate, IsRequest, NeedsResponse, IsResponse),
+ InvalidCmd, "WriteInvalidateResp" },
+ /* UpgradeReq */
+ { SET3(IsInvalidate, IsRequest, IsUpgrade), InvalidCmd, "UpgradeReq" },
+ /* ReadExReq */
+ { SET4(IsRead, IsInvalidate, IsRequest, NeedsResponse),
+ ReadExResp, "ReadExReq" },
+ /* ReadExResp */
+ { SET4(IsRead, IsInvalidate, IsResponse, HasData),
+ InvalidCmd, "ReadExResp" }
+};
-const std::string &
-Packet::cmdIdxToString(Packet::Command idx)
-{
- switch (idx) {
- case ReadReq: return ReadReqString;
- case WriteReq: return WriteReqString;
- case WriteReqNoAck: return WriteReqNoAckString;
- case ReadResp: return ReadRespString;
- case WriteResp: return WriteRespString;
- case SoftPFReq: return SoftPFReqString;
- case SoftPFResp: return SoftPFRespString;
- case HardPFReq: return HardPFReqString;
- case HardPFResp: return HardPFRespString;
- case InvalidateReq: return InvalidateReqString;
- case WriteInvalidateReq:return WriteInvalidateReqString;
- case WriteInvalidateResp:return WriteInvalidateRespString;
- case UpgradeReq: return UpgradeReqString;
- case ReadExReq: return ReadExReqString;
- case ReadExResp: return ReadExRespString;
- default: return OtherCmdString;
- }
-}
/** delete the data pointed to in the data pointer. Ok to call to matter how
* data was allocted. */
@@ -149,9 +143,17 @@
bool result;
if (timing->isRead() || timing->isWrite()) {
- timing->toggleData();
+ // Ugly hack to deal with the fact that we queue the requests
+ // and don't convert them to responses until we issue them on
+ // the bus. I tried to avoid this by converting packets to
+ // responses right away, but this breaks during snoops where a
+ // responder may do the conversion before other caches have
+ // done the snoop. Would work if we copied the packet instead
+ // of just hanging on to a pointer.
+ MemCmd oldCmd = timing->cmd;
+ timing->cmd = timing->cmd.responseCommand();
result = fixPacket(func, timing);
- timing->toggleData();
+ timing->cmd = oldCmd;
}
else {
//Don't toggle if it isn't a read/write response
@@ -171,11 +173,6 @@
assert(!(funcStart > timingEnd || timingStart > funcEnd));
- if (DTRACE(FunctionalAccess)) {
- DebugOut() << func;
- DebugOut() << timing;
- }
-
// this packet can't solve our problem, continue on
if (!timing->hasData())
return true;
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index a4c003e..65d2207 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -40,6 +40,7 @@
#include <cassert>
#include <list>
+#include <bitset>
#include "base/compiler.hh"
#include "base/misc.hh"
@@ -62,8 +63,114 @@
#define NO_ALLOCATE (1 << 5)
#define SNOOP_COMMIT (1 << 6)
-//for now. @todo fix later
-#define NUM_MEM_CMDS (1 << 11)
+
+class MemCmd
+{
+ public:
+
+ /** List of all commands associated with a packet. */
+ enum Command
+ {
+ InvalidCmd,
+ ReadReq,
+ WriteReq,
+ WriteReqNoAck,
+ ReadResp,
+ WriteResp,
+ Writeback,
+ SoftPFReq,
+ HardPFReq,
+ SoftPFResp,
+ HardPFResp,
+ InvalidateReq,
+ WriteInvalidateReq,
+ WriteInvalidateResp,
+ UpgradeReq,
+ ReadExReq,
+ ReadExResp,
+ NUM_MEM_CMDS
+ };
+
+ private:
+ /** List of command attributes. */
+ enum Attribute
+ {
+ IsRead,
+ IsWrite,
+ IsPrefetch,
+ IsInvalidate,
+ IsRequest,
+ IsResponse,
+ NeedsResponse,
+ IsSWPrefetch,
+ IsHWPrefetch,
+ IsUpgrade,
+ HasData,
+ NUM_COMMAND_ATTRIBUTES
+ };
+
+ /** Structure that defines attributes and other data associated
+ * with a Command. */
+ struct CommandInfo {
+ /** Set of attribute flags. */
+ const std::bitset<NUM_COMMAND_ATTRIBUTES> attributes;
+ /** Corresponding response for requests; InvalidCmd if no
+ * response is applicable. */
+ const Command response;
+ /** String representation (for printing) */
+ const std::string str;
+ };
+
+ /** Array to map Command enum to associated info. */
+ static const CommandInfo commandInfo[];
+
+ private:
+
+ Command cmd;
+
+ bool testCmdAttrib(MemCmd::Attribute attrib) const {
+ return commandInfo[cmd].attributes[attrib] != 0;
+ }
+
+ public:
+
+ bool isRead() const { return testCmdAttrib(IsRead); }
+ bool isWrite() const { return testCmdAttrib(IsWrite); }
+ bool isRequest() const { return testCmdAttrib(IsRequest); }
+ bool isResponse() const { return testCmdAttrib(IsResponse); }
+ bool needsResponse() const { return testCmdAttrib(NeedsResponse); }
+ bool isInvalidate() const { return testCmdAttrib(IsInvalidate); }
+ bool hasData() const { return testCmdAttrib(HasData); }
+
+ const Command responseCommand() const {
+ return commandInfo[cmd].response;
+ }
+
+ /** Return the string to a cmd given by idx. */
+ const std::string &toString() const {
+ return commandInfo[cmd].str;
+ }
+
+ int toInt() const { return (int)cmd; }
+
+ MemCmd(Command _cmd)
+ : cmd(_cmd)
+ { }
+
+ MemCmd(int _cmd)
+ : cmd((Command)_cmd)
+ { }
+
+ MemCmd()
+ : cmd(InvalidCmd)
+ { }
+
+ bool operator==(MemCmd c2) { return (cmd == c2.cmd); }
+ bool operator!=(MemCmd c2) { return (cmd != c2.cmd); }
+
+ friend class Packet;
+};
+
/**
* A Packet is used to encapsulate a transfer between two objects in
* the memory system (e.g., the L1 and L2 cache). (In contrast, a
@@ -74,6 +181,9 @@
class Packet
{
public:
+
+ typedef MemCmd::Command Command;
+
/** Temporary FLAGS field until cache gets working, this should be in coherence/sender state. */
uint64_t flags;
@@ -169,73 +279,27 @@
* to cast to the state appropriate to the sender. */
SenderState *senderState;
- private:
- /** List of command attributes. */
- // If you add a new CommandAttribute, make sure to increase NUM_MEM_CMDS
- // as well.
- enum CommandAttribute
- {
- IsRead = 1 << 0,
- IsWrite = 1 << 1,
- IsPrefetch = 1 << 2,
- IsInvalidate = 1 << 3,
- IsRequest = 1 << 4,
- IsResponse = 1 << 5,
- NeedsResponse = 1 << 6,
- IsSWPrefetch = 1 << 7,
- IsHWPrefetch = 1 << 8,
- IsUpgrade = 1 << 9,
- HasData = 1 << 10
- };
-
public:
- /** List of all commands associated with a packet. */
- enum Command
- {
- InvalidCmd = 0,
- ReadReq = IsRead | IsRequest | NeedsResponse,
- WriteReq = IsWrite | IsRequest | NeedsResponse | HasData,
- WriteReqNoAck = IsWrite | IsRequest | HasData,
- ReadResp = IsRead | IsResponse | NeedsResponse | HasData,
- WriteResp = IsWrite | IsResponse | NeedsResponse,
- Writeback = IsWrite | IsRequest | HasData,
- SoftPFReq = IsRead | IsRequest | IsSWPrefetch | NeedsResponse,
- HardPFReq = IsRead | IsRequest | IsHWPrefetch | NeedsResponse,
- SoftPFResp = IsRead | IsResponse | IsSWPrefetch
- | NeedsResponse | HasData,
- HardPFResp = IsRead | IsResponse | IsHWPrefetch
- | NeedsResponse | HasData,
- InvalidateReq = IsInvalidate | IsRequest,
- WriteInvalidateReq = IsWrite | IsInvalidate | IsRequest
- | HasData | NeedsResponse,
- WriteInvalidateResp = IsWrite | IsInvalidate | IsRequest
- | NeedsResponse | IsResponse,
- UpgradeReq = IsInvalidate | IsRequest | IsUpgrade,
- ReadExReq = IsRead | IsInvalidate | IsRequest | NeedsResponse,
- ReadExResp = IsRead | IsInvalidate | IsResponse
- | NeedsResponse | HasData
- };
+
+ /** The command field of the packet. */
+ MemCmd cmd;
/** Return the string name of the cmd field (for debugging and
* tracing). */
- const std::string &cmdString() const;
-
- /** Reutrn the string to a cmd given by idx. */
- const std::string &cmdIdxToString(Command idx);
+ const std::string &cmdString() const { return cmd.toString(); }
/** Return the index of this command. */
- inline int cmdToIndex() const { return (int) cmd; }
+ inline int cmdToIndex() const { return cmd.toInt(); }
- /** The command field of the packet. */
- Command cmd;
+ public:
- bool isRead() const { return (cmd & IsRead) != 0; }
- bool isWrite() const { return (cmd & IsWrite) != 0; }
- bool isRequest() const { return (cmd & IsRequest) != 0; }
- bool isResponse() const { return (cmd & IsResponse) != 0; }
- bool needsResponse() const { return (cmd & NeedsResponse) != 0; }
- bool isInvalidate() const { return (cmd & IsInvalidate) != 0; }
- bool hasData() const { return (cmd & HasData) != 0; }
+ bool isRead() const { return cmd.isRead(); }
+ bool isWrite() const { return cmd.isWrite(); }
+ bool isRequest() const { return cmd.isRequest(); }
+ bool isResponse() const { return cmd.isResponse(); }
+ bool needsResponse() const { return cmd.needsResponse(); }
+ bool isInvalidate() const { return cmd.isInvalidate(); }
+ bool hasData() const { return cmd.hasData(); }
bool isCacheFill() const { return (flags & CACHE_LINE_FILL) != 0; }
bool isNoAllocate() const { return (flags & NO_ALLOCATE) != 0; }
@@ -269,13 +333,13 @@
Addr getOffset(int blkSize) const { return addr & (Addr)(blkSize - 1); }
void addrOverride(Addr newAddr) { assert(addrSizeValid); addr = newAddr; }
- void cmdOverride(Command newCmd) { cmd = newCmd; }
+ void cmdOverride(MemCmd newCmd) { cmd = newCmd; }
/** Constructor. Note that a Request object must be constructed
* first, but the Requests's physical address and size fields
* need not be valid. The command and destination addresses
* must be supplied. */
- Packet(Request *_req, Command _cmd, short _dest)
+ Packet(Request *_req, MemCmd _cmd, short _dest)
: data(NULL), staticData(false), dynamicData(false), arrayData(false),
addr(_req->paddr), size(_req->size), dest(_dest),
addrSizeValid(_req->validPaddr),
@@ -290,7 +354,7 @@
/** Alternate constructor if you are trying to create a packet with
* a request that is for a whole block, not the address from the req.
* this allows for overriding the size/addr of the req.*/
- Packet(Request *_req, Command _cmd, short _dest, int _blkSize)
+ Packet(Request *_req, MemCmd _cmd, short _dest, int _blkSize)
: data(NULL), staticData(false), dynamicData(false), arrayData(false),
addr(_req->paddr & ~(_blkSize - 1)), size(_blkSize),
dest(_dest),
@@ -335,25 +399,11 @@
void makeTimingResponse() {
assert(needsResponse());
assert(isRequest());
- int icmd = (int)cmd;
- icmd &= ~(IsRequest);
- icmd |= IsResponse;
- if (isRead())
- icmd |= HasData;
- if (isWrite())
- icmd &= ~HasData;
- cmd = (Command)icmd;
+ cmd = cmd.responseCommand();
dest = src;
srcValid = false;
}
-
- void toggleData() {
- int icmd = (int)cmd;
- icmd ^= HasData;
- cmd = (Command)icmd;
- }
-
/**
* Take a request packet and modify it in place to be suitable for
* returning as a response to that request.
@@ -362,14 +412,7 @@
{
assert(needsResponse());
assert(isRequest());
- int icmd = (int)cmd;
- icmd &= ~(IsRequest);
- icmd |= IsResponse;
- if (isRead())
- icmd |= HasData;
- if (isWrite())
- icmd &= ~HasData;
- cmd = (Command)icmd;
+ cmd = cmd.responseCommand();
}
/**
diff --git a/src/mem/port.cc b/src/mem/port.cc
index da719bb..048d7cf 100644
--- a/src/mem/port.cc
+++ b/src/mem/port.cc
@@ -46,7 +46,7 @@
}
void
-Port::blobHelper(Addr addr, uint8_t *p, int size, Packet::Command cmd)
+Port::blobHelper(Addr addr, uint8_t *p, int size, MemCmd cmd)
{
Request req;
Packet pkt(&req, cmd, Packet::Broadcast);
@@ -64,13 +64,13 @@
void
Port::writeBlob(Addr addr, uint8_t *p, int size)
{
- blobHelper(addr, p, size, Packet::WriteReq);
+ blobHelper(addr, p, size, MemCmd::WriteReq);
}
void
Port::readBlob(Addr addr, uint8_t *p, int size)
{
- blobHelper(addr, p, size, Packet::ReadReq);
+ blobHelper(addr, p, size, MemCmd::ReadReq);
}
void
@@ -80,7 +80,7 @@
uint8_t *buf = new uint8_t[size];
std::memset(buf, val, size);
- blobHelper(addr, buf, size, Packet::WriteReq);
+ blobHelper(addr, buf, size, MemCmd::WriteReq);
delete [] buf;
}
diff --git a/src/mem/port.hh b/src/mem/port.hh
index 5e55225..fdb5bfa 100644
--- a/src/mem/port.hh
+++ b/src/mem/port.hh
@@ -245,7 +245,7 @@
/** Internal helper function for read/writeBlob().
*/
- void blobHelper(Addr addr, uint8_t *p, int size, Packet::Command cmd);
+ void blobHelper(Addr addr, uint8_t *p, int size, MemCmd cmd);
};
/** A simple functional port that is only meant for one way communication to
diff --git a/src/mem/tport.cc b/src/mem/tport.cc
index c43c9aa..b384a04 100644
--- a/src/mem/tport.cc
+++ b/src/mem/tport.cc
@@ -68,7 +68,7 @@
sendTiming(pkt, latency);
}
else {
- if (pkt->cmd != Packet::UpgradeReq)
+ if (pkt->cmd != MemCmd::UpgradeReq)
{
delete pkt->req;
delete pkt;
diff --git a/src/sim/eventq.cc b/src/sim/eventq.cc
index 6ae8388..356472d 100644
--- a/src/sim/eventq.cc
+++ b/src/sim/eventq.cc
@@ -53,6 +53,10 @@
//
EventQueue mainEventQueue("MainEventQueue");
+#ifndef NDEBUG
+Counter Event::instanceCounter = 0;
+#endif
+
void
EventQueue::insert(Event *event)
{
diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh
index fa65b08..1aeb26e 100644
--- a/src/sim/eventq.hh
+++ b/src/sim/eventq.hh
@@ -75,6 +75,18 @@
friend class EventQueue;
private:
+
+#ifndef NDEBUG
+ /// Global counter to generate unique IDs for Event instances
+ static Counter instanceCounter;
+
+ /// This event's unique ID. We can also use pointer values for
+ /// this but they're not consistent across runs making debugging
+ /// more difficult. Thus we use a global counter value when
+ /// debugging.
+ Counter instanceId;
+#endif // NDEBUG
+
/// queue to which this event belongs (though it may or may not be
/// scheduled on this queue yet)
EventQueue *queue;
@@ -173,12 +185,19 @@
#endif
annotated_value(0)
{
+#ifndef NDEBUG
+ instanceId = ++instanceCounter;
+#endif
}
~Event() {}
virtual const std::string name() const {
+#ifndef NDEBUG
+ return csprintf("Event_%d", instanceId);
+#else
return csprintf("Event_%x", (uintptr_t)this);
+#endif
}
/// Determine if the current event is scheduled
diff --git a/tests/SConscript b/tests/SConscript
index 8c9029b..54fa250 100644
--- a/tests/SConscript
+++ b/tests/SConscript
@@ -205,7 +205,7 @@
'twosys-tsunami-simple-atomic']
else:
- configs += ['simple-atomic', 'simple-timing', 'o3-timing']
+ configs += ['simple-atomic', 'simple-timing', 'o3-timing', 'memtest']
cwd = os.getcwd()
os.chdir(str(Dir('.').srcdir))
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index 2b99041..f56edef 100644
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -53,7 +53,7 @@
#MAX CORES IS 8 with the fals sharing method
nb_cores = 8
-cpus = [ MemTest(atomic=False, max_loads=1e12, percent_uncacheable=10, progress_interval=1000) for i in xrange(nb_cores) ]
+cpus = [ MemTest() for i in xrange(nb_cores) ]
# system simulated
system = System(cpu = cpus, funcmem = PhysicalMemory(),
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
new file mode 100644
index 0000000..05eb914
--- /dev/null
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini
@@ -0,0 +1,621 @@
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[exetrace]
+intel_format=false
+legion_lockstep=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem l2c membus physmem toL2Bus
+mem_mode=timing
+physmem=system.physmem
+
+[system.cpu0]
+type=MemTest
+children=l1c
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.port
+test=system.cpu0.l1c.cpu_side
+
+[system.cpu0.l1c]
+type=BaseCache
+children=protocol
+adaptive_compression=false
+assoc=4
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=12
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=system.cpu0.l1c.protocol
+repl=Null
+size=32768
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.test
+mem_side=system.toL2Bus.port[1]
+
+[system.cpu0.l1c.protocol]
+type=CoherenceProtocol
+do_upgrades=true
+protocol=moesi
+
+[system.cpu1]
+type=MemTest
+children=l1c
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.functional
+test=system.cpu1.l1c.cpu_side
+
+[system.cpu1.l1c]
+type=BaseCache
+children=protocol
+adaptive_compression=false
+assoc=4
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=12
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=system.cpu1.l1c.protocol
+repl=Null
+size=32768
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.test
+mem_side=system.toL2Bus.port[2]
+
+[system.cpu1.l1c.protocol]
+type=CoherenceProtocol
+do_upgrades=true
+protocol=moesi
+
+[system.cpu2]
+type=MemTest
+children=l1c
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.functional
+test=system.cpu2.l1c.cpu_side
+
+[system.cpu2.l1c]
+type=BaseCache
+children=protocol
+adaptive_compression=false
+assoc=4
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=12
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=system.cpu2.l1c.protocol
+repl=Null
+size=32768
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu2.test
+mem_side=system.toL2Bus.port[3]
+
+[system.cpu2.l1c.protocol]
+type=CoherenceProtocol
+do_upgrades=true
+protocol=moesi
+
+[system.cpu3]
+type=MemTest
+children=l1c
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.functional
+test=system.cpu3.l1c.cpu_side
+
+[system.cpu3.l1c]
+type=BaseCache
+children=protocol
+adaptive_compression=false
+assoc=4
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=12
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=system.cpu3.l1c.protocol
+repl=Null
+size=32768
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu3.test
+mem_side=system.toL2Bus.port[4]
+
+[system.cpu3.l1c.protocol]
+type=CoherenceProtocol
+do_upgrades=true
+protocol=moesi
+
+[system.cpu4]
+type=MemTest
+children=l1c
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.functional
+test=system.cpu4.l1c.cpu_side
+
+[system.cpu4.l1c]
+type=BaseCache
+children=protocol
+adaptive_compression=false
+assoc=4
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=12
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=system.cpu4.l1c.protocol
+repl=Null
+size=32768
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu4.test
+mem_side=system.toL2Bus.port[5]
+
+[system.cpu4.l1c.protocol]
+type=CoherenceProtocol
+do_upgrades=true
+protocol=moesi
+
+[system.cpu5]
+type=MemTest
+children=l1c
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.functional
+test=system.cpu5.l1c.cpu_side
+
+[system.cpu5.l1c]
+type=BaseCache
+children=protocol
+adaptive_compression=false
+assoc=4
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=12
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=system.cpu5.l1c.protocol
+repl=Null
+size=32768
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu5.test
+mem_side=system.toL2Bus.port[6]
+
+[system.cpu5.l1c.protocol]
+type=CoherenceProtocol
+do_upgrades=true
+protocol=moesi
+
+[system.cpu6]
+type=MemTest
+children=l1c
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.functional
+test=system.cpu6.l1c.cpu_side
+
+[system.cpu6.l1c]
+type=BaseCache
+children=protocol
+adaptive_compression=false
+assoc=4
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=12
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=system.cpu6.l1c.protocol
+repl=Null
+size=32768
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu6.test
+mem_side=system.toL2Bus.port[7]
+
+[system.cpu6.l1c.protocol]
+type=CoherenceProtocol
+do_upgrades=true
+protocol=moesi
+
+[system.cpu7]
+type=MemTest
+children=l1c
+atomic=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+trace_addr=0
+functional=system.funcmem.functional
+test=system.cpu7.l1c.cpu_side
+
+[system.cpu7.l1c]
+type=BaseCache
+children=protocol
+adaptive_compression=false
+assoc=4
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=12
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=system.cpu7.l1c.protocol
+repl=Null
+size=32768
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu7.test
+mem_side=system.toL2Bus.port[8]
+
+[system.cpu7.l1c.protocol]
+type=CoherenceProtocol
+do_upgrades=true
+protocol=moesi
+
+[system.funcmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+zero=false
+functional=system.cpu7.functional
+port=system.cpu0.functional
+
+[system.l2c]
+type=BaseCache
+adaptive_compression=false
+assoc=8
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=10
+lifo=false
+max_miss_count=0
+mshrs=92
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=65536
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=16
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.port[0]
+mem_side=system.membus.port[0]
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=2
+responder_set=false
+width=16
+port=system.l2c.mem_side system.physmem.port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+zero=false
+port=system.membus.port[1]
+
+[system.toL2Bus]
+type=Bus
+bus_id=0
+clock=2
+responder_set=false
+width=16
+port=system.l2c.cpu_side system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
+
+[trace]
+bufsize=0
+cycle=0
+dump_on_exit=false
+file=cout
+flags=
+ignore=
+start=0
+
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out
new file mode 100644
index 0000000..b8ae04b
--- /dev/null
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.out
@@ -0,0 +1,574 @@
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+zero=false
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=timing
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=2
+width=16
+responder_set=false
+
+[system.l2c]
+type=BaseCache
+size=65536
+assoc=8
+block_size=64
+latency=10
+mshrs=92
+tgts_per_mshr=16
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu6]
+type=MemTest
+memory_size=65536
+percent_reads=65
+percent_functional=50
+percent_uncacheable=10
+progress_interval=10000
+percent_source_unaligned=50
+percent_dest_unaligned=50
+trace_addr=0
+max_loads=100000
+atomic=false
+
+[system.cpu6.l1c.protocol]
+type=CoherenceProtocol
+protocol=moesi
+do_upgrades=true
+
+[system.cpu6.l1c]
+type=BaseCache
+size=32768
+assoc=4
+block_size=64
+latency=1
+mshrs=12
+tgts_per_mshr=8
+write_buffers=8
+prioritizeRequests=false
+protocol=system.cpu6.l1c.protocol
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu4]
+type=MemTest
+memory_size=65536
+percent_reads=65
+percent_functional=50
+percent_uncacheable=10
+progress_interval=10000
+percent_source_unaligned=50
+percent_dest_unaligned=50
+trace_addr=0
+max_loads=100000
+atomic=false
+
+[system.cpu4.l1c.protocol]
+type=CoherenceProtocol
+protocol=moesi
+do_upgrades=true
+
+[system.cpu4.l1c]
+type=BaseCache
+size=32768
+assoc=4
+block_size=64
+latency=1
+mshrs=12
+tgts_per_mshr=8
+write_buffers=8
+prioritizeRequests=false
+protocol=system.cpu4.l1c.protocol
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu5]
+type=MemTest
+memory_size=65536
+percent_reads=65
+percent_functional=50
+percent_uncacheable=10
+progress_interval=10000
+percent_source_unaligned=50
+percent_dest_unaligned=50
+trace_addr=0
+max_loads=100000
+atomic=false
+
+[system.cpu5.l1c.protocol]
+type=CoherenceProtocol
+protocol=moesi
+do_upgrades=true
+
+[system.cpu5.l1c]
+type=BaseCache
+size=32768
+assoc=4
+block_size=64
+latency=1
+mshrs=12
+tgts_per_mshr=8
+write_buffers=8
+prioritizeRequests=false
+protocol=system.cpu5.l1c.protocol
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu2]
+type=MemTest
+memory_size=65536
+percent_reads=65
+percent_functional=50
+percent_uncacheable=10
+progress_interval=10000
+percent_source_unaligned=50
+percent_dest_unaligned=50
+trace_addr=0
+max_loads=100000
+atomic=false
+
+[system.cpu2.l1c.protocol]
+type=CoherenceProtocol
+protocol=moesi
+do_upgrades=true
+
+[system.cpu2.l1c]
+type=BaseCache
+size=32768
+assoc=4
+block_size=64
+latency=1
+mshrs=12
+tgts_per_mshr=8
+write_buffers=8
+prioritizeRequests=false
+protocol=system.cpu2.l1c.protocol
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu3]
+type=MemTest
+memory_size=65536
+percent_reads=65
+percent_functional=50
+percent_uncacheable=10
+progress_interval=10000
+percent_source_unaligned=50
+percent_dest_unaligned=50
+trace_addr=0
+max_loads=100000
+atomic=false
+
+[system.cpu3.l1c.protocol]
+type=CoherenceProtocol
+protocol=moesi
+do_upgrades=true
+
+[system.cpu3.l1c]
+type=BaseCache
+size=32768
+assoc=4
+block_size=64
+latency=1
+mshrs=12
+tgts_per_mshr=8
+write_buffers=8
+prioritizeRequests=false
+protocol=system.cpu3.l1c.protocol
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu0]
+type=MemTest
+memory_size=65536
+percent_reads=65
+percent_functional=50
+percent_uncacheable=10
+progress_interval=10000
+percent_source_unaligned=50
+percent_dest_unaligned=50
+trace_addr=0
+max_loads=100000
+atomic=false
+
+[system.cpu0.l1c.protocol]
+type=CoherenceProtocol
+protocol=moesi
+do_upgrades=true
+
+[system.cpu0.l1c]
+type=BaseCache
+size=32768
+assoc=4
+block_size=64
+latency=1
+mshrs=12
+tgts_per_mshr=8
+write_buffers=8
+prioritizeRequests=false
+protocol=system.cpu0.l1c.protocol
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu1]
+type=MemTest
+memory_size=65536
+percent_reads=65
+percent_functional=50
+percent_uncacheable=10
+progress_interval=10000
+percent_source_unaligned=50
+percent_dest_unaligned=50
+trace_addr=0
+max_loads=100000
+atomic=false
+
+[system.cpu1.l1c.protocol]
+type=CoherenceProtocol
+protocol=moesi
+do_upgrades=true
+
+[system.cpu1.l1c]
+type=BaseCache
+size=32768
+assoc=4
+block_size=64
+latency=1
+mshrs=12
+tgts_per_mshr=8
+write_buffers=8
+prioritizeRequests=false
+protocol=system.cpu1.l1c.protocol
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.funcmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+zero=false
+
+[system.cpu7]
+type=MemTest
+memory_size=65536
+percent_reads=65
+percent_functional=50
+percent_uncacheable=10
+progress_interval=10000
+percent_source_unaligned=50
+percent_dest_unaligned=50
+trace_addr=0
+max_loads=100000
+atomic=false
+
+[system.cpu7.l1c.protocol]
+type=CoherenceProtocol
+protocol=moesi
+do_upgrades=true
+
+[system.cpu7.l1c]
+type=BaseCache
+size=32768
+assoc=4
+block_size=64
+latency=1
+mshrs=12
+tgts_per_mshr=8
+write_buffers=8
+prioritizeRequests=false
+protocol=system.cpu7.l1c.protocol
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.toL2Bus]
+type=Bus
+bus_id=0
+clock=2
+width=16
+responder_set=false
+
+[trace]
+flags=
+start=0
+cycle=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+print_reg_delta=false
+pc_symbol=true
+intel_format=false
+legion_lockstep=false
+trace_system=client
+
+[statsreset]
+reset_cycle=0
+
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt
new file mode 100644
index 0000000..a65b235
--- /dev/null
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt
@@ -0,0 +1,952 @@
+
+---------- Begin Simulation Statistics ----------
+host_mem_usage 435124 # Number of bytes of host memory used
+host_seconds 28.46 # Real time elapsed on the host
+host_tick_rate 202211 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_seconds 0.000006 # Number of seconds simulated
+sim_ticks 5755736 # Number of ticks simulated
+system.cpu0.l1c.ReadReq_accesses 45048 # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.ReadReq_avg_miss_latency 959.688548 # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 884.132516 # average ReadReq mshr miss latency
+system.cpu0.l1c.ReadReq_hits 7543 # number of ReadReq hits
+system.cpu0.l1c.ReadReq_miss_latency 35993119 # number of ReadReq miss cycles
+system.cpu0.l1c.ReadReq_miss_rate 0.832556 # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_misses 37505 # number of ReadReq misses
+system.cpu0.l1c.ReadReq_mshr_miss_latency 33159390 # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_miss_rate 0.832556 # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_mshr_misses 37505 # number of ReadReq MSHR misses
+system.cpu0.l1c.ReadReq_mshr_uncacheable 9815 # number of ReadReq MSHR uncacheable
+system.cpu0.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
+system.cpu0.l1c.ReadResp_mshr_uncacheable_latency 17521633 # number of ReadResp MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_accesses 24308 # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_avg_miss_latency 862.246942 # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 778.821396 # average WriteReq mshr miss latency
+system.cpu0.l1c.WriteReq_hits 1173 # number of WriteReq hits
+system.cpu0.l1c.WriteReq_miss_latency 19948083 # number of WriteReq miss cycles
+system.cpu0.l1c.WriteReq_miss_rate 0.951744 # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_misses 23135 # number of WriteReq misses
+system.cpu0.l1c.WriteReq_mshr_miss_latency 18018033 # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_rate 0.951744 # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_mshr_misses 23135 # number of WriteReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_uncacheable 5428 # number of WriteReq MSHR uncacheable
+system.cpu0.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
+system.cpu0.l1c.WriteResp_mshr_uncacheable_latency 10755873 # number of WriteResp MSHR uncacheable cycles
+system.cpu0.l1c.avg_blocked_cycles_no_mshrs 81.366905 # average number of cycles each access was blocked
+system.cpu0.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu0.l1c.avg_refs 0.417208 # Average number of references to valid blocks.
+system.cpu0.l1c.blocked_no_mshrs 69811 # number of cycles access was blocked
+system.cpu0.l1c.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu0.l1c.blocked_cycles_no_mshrs 5680305 # number of cycles access was blocked
+system.cpu0.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu0.l1c.cache_copies 0 # number of cache copies performed
+system.cpu0.l1c.demand_accesses 69356 # number of demand (read+write) accesses
+system.cpu0.l1c.demand_avg_miss_latency 922.513226 # average overall miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency 843.954865 # average overall mshr miss latency
+system.cpu0.l1c.demand_hits 8716 # number of demand (read+write) hits
+system.cpu0.l1c.demand_miss_latency 55941202 # number of demand (read+write) miss cycles
+system.cpu0.l1c.demand_miss_rate 0.874330 # miss rate for demand accesses
+system.cpu0.l1c.demand_misses 60640 # number of demand (read+write) misses
+system.cpu0.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu0.l1c.demand_mshr_miss_latency 51177423 # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_rate 0.874330 # mshr miss rate for demand accesses
+system.cpu0.l1c.demand_mshr_misses 60640 # number of demand (read+write) MSHR misses
+system.cpu0.l1c.fast_writes 0 # number of fast writes performed
+system.cpu0.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu0.l1c.overall_accesses 69356 # number of overall (read+write) accesses
+system.cpu0.l1c.overall_avg_miss_latency 922.513226 # average overall miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency 843.954865 # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
+system.cpu0.l1c.overall_hits 8716 # number of overall hits
+system.cpu0.l1c.overall_miss_latency 55941202 # number of overall miss cycles
+system.cpu0.l1c.overall_miss_rate 0.874330 # miss rate for overall accesses
+system.cpu0.l1c.overall_misses 60640 # number of overall misses
+system.cpu0.l1c.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu0.l1c.overall_mshr_miss_latency 51177423 # number of overall MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_rate 0.874330 # mshr miss rate for overall accesses
+system.cpu0.l1c.overall_mshr_misses 60640 # number of overall MSHR misses
+system.cpu0.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_misses 15243 # number of overall MSHR uncacheable misses
+system.cpu0.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu0.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu0.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu0.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu0.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu0.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu0.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu0.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu0.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu0.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
+system.cpu0.l1c.protocol.read_invalid 109554 # read misses to invalid blocks
+system.cpu0.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
+system.cpu0.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
+system.cpu0.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
+system.cpu0.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
+system.cpu0.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
+system.cpu0.l1c.protocol.snoop_read_exclusive 2807 # read snoops on exclusive blocks
+system.cpu0.l1c.protocol.snoop_read_modified 12380 # read snoops on modified blocks
+system.cpu0.l1c.protocol.snoop_read_owned 7157 # read snoops on owned blocks
+system.cpu0.l1c.protocol.snoop_read_shared 22767 # read snoops on shared blocks
+system.cpu0.l1c.protocol.snoop_readex_exclusive 1535 # readEx snoops on exclusive blocks
+system.cpu0.l1c.protocol.snoop_readex_modified 6851 # readEx snoops on modified blocks
+system.cpu0.l1c.protocol.snoop_readex_owned 3877 # readEx snoops on owned blocks
+system.cpu0.l1c.protocol.snoop_readex_shared 12465 # readEx snoops on shared blocks
+system.cpu0.l1c.protocol.snoop_upgrade_owned 887 # upgrade snoops on owned blocks
+system.cpu0.l1c.protocol.snoop_upgrade_shared 2994 # upgradee snoops on shared blocks
+system.cpu0.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
+system.cpu0.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
+system.cpu0.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
+system.cpu0.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
+system.cpu0.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
+system.cpu0.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
+system.cpu0.l1c.protocol.write_invalid 60706 # write misses to invalid blocks
+system.cpu0.l1c.protocol.write_owned 1361 # write misses to owned blocks
+system.cpu0.l1c.protocol.write_shared 4416 # write misses to shared blocks
+system.cpu0.l1c.replacements 27529 # number of replacements
+system.cpu0.l1c.sampled_refs 27883 # Sample count of references to valid blocks.
+system.cpu0.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu0.l1c.tagsinuse 342.460043 # Cycle average of tags in use
+system.cpu0.l1c.total_refs 11633 # Total number of references to valid blocks.
+system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu0.l1c.writebacks 10915 # number of writebacks
+system.cpu0.num_copies 0 # number of copy accesses completed
+system.cpu0.num_reads 99586 # number of read accesses completed
+system.cpu0.num_writes 53803 # number of write accesses completed
+system.cpu1.l1c.ReadReq_accesses 44416 # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.ReadReq_avg_miss_latency 969.343786 # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 893.327484 # average ReadReq mshr miss latency
+system.cpu1.l1c.ReadReq_hits 7486 # number of ReadReq hits
+system.cpu1.l1c.ReadReq_miss_latency 35797866 # number of ReadReq miss cycles
+system.cpu1.l1c.ReadReq_miss_rate 0.831457 # miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_misses 36930 # number of ReadReq misses
+system.cpu1.l1c.ReadReq_mshr_miss_latency 32990584 # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate 0.831457 # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_mshr_misses 36930 # number of ReadReq MSHR misses
+system.cpu1.l1c.ReadReq_mshr_uncacheable 9894 # number of ReadReq MSHR uncacheable
+system.cpu1.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
+system.cpu1.l1c.ReadResp_mshr_uncacheable_latency 17663360 # number of ReadResp MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_accesses 24084 # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_avg_miss_latency 871.179293 # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 786.258930 # average WriteReq mshr miss latency
+system.cpu1.l1c.WriteReq_hits 1155 # number of WriteReq hits
+system.cpu1.l1c.WriteReq_miss_latency 19975270 # number of WriteReq miss cycles
+system.cpu1.l1c.WriteReq_miss_rate 0.952043 # miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_misses 22929 # number of WriteReq misses
+system.cpu1.l1c.WriteReq_mshr_miss_latency 18028131 # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_rate 0.952043 # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_mshr_misses 22929 # number of WriteReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_uncacheable 5271 # number of WriteReq MSHR uncacheable
+system.cpu1.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
+system.cpu1.l1c.WriteResp_mshr_uncacheable_latency 10523322 # number of WriteResp MSHR uncacheable cycles
+system.cpu1.l1c.avg_blocked_cycles_no_mshrs 82.260179 # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu1.l1c.avg_refs 0.414867 # Average number of references to valid blocks.
+system.cpu1.l1c.blocked_no_mshrs 68941 # number of cycles access was blocked
+system.cpu1.l1c.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu1.l1c.blocked_cycles_no_mshrs 5671099 # number of cycles access was blocked
+system.cpu1.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu1.l1c.cache_copies 0 # number of cache copies performed
+system.cpu1.l1c.demand_accesses 68500 # number of demand (read+write) accesses
+system.cpu1.l1c.demand_avg_miss_latency 931.741860 # average overall miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency 852.314857 # average overall mshr miss latency
+system.cpu1.l1c.demand_hits 8641 # number of demand (read+write) hits
+system.cpu1.l1c.demand_miss_latency 55773136 # number of demand (read+write) miss cycles
+system.cpu1.l1c.demand_miss_rate 0.873854 # miss rate for demand accesses
+system.cpu1.l1c.demand_misses 59859 # number of demand (read+write) misses
+system.cpu1.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu1.l1c.demand_mshr_miss_latency 51018715 # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_rate 0.873854 # mshr miss rate for demand accesses
+system.cpu1.l1c.demand_mshr_misses 59859 # number of demand (read+write) MSHR misses
+system.cpu1.l1c.fast_writes 0 # number of fast writes performed
+system.cpu1.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.l1c.overall_accesses 68500 # number of overall (read+write) accesses
+system.cpu1.l1c.overall_avg_miss_latency 931.741860 # average overall miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency 852.314857 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
+system.cpu1.l1c.overall_hits 8641 # number of overall hits
+system.cpu1.l1c.overall_miss_latency 55773136 # number of overall miss cycles
+system.cpu1.l1c.overall_miss_rate 0.873854 # miss rate for overall accesses
+system.cpu1.l1c.overall_misses 59859 # number of overall misses
+system.cpu1.l1c.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu1.l1c.overall_mshr_miss_latency 51018715 # number of overall MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_rate 0.873854 # mshr miss rate for overall accesses
+system.cpu1.l1c.overall_mshr_misses 59859 # number of overall MSHR misses
+system.cpu1.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_misses 15165 # number of overall MSHR uncacheable misses
+system.cpu1.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu1.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu1.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu1.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu1.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu1.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu1.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu1.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu1.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu1.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
+system.cpu1.l1c.protocol.read_invalid 114228 # read misses to invalid blocks
+system.cpu1.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
+system.cpu1.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
+system.cpu1.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
+system.cpu1.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
+system.cpu1.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
+system.cpu1.l1c.protocol.snoop_read_exclusive 2718 # read snoops on exclusive blocks
+system.cpu1.l1c.protocol.snoop_read_modified 12396 # read snoops on modified blocks
+system.cpu1.l1c.protocol.snoop_read_owned 7348 # read snoops on owned blocks
+system.cpu1.l1c.protocol.snoop_read_shared 23222 # read snoops on shared blocks
+system.cpu1.l1c.protocol.snoop_readex_exclusive 1497 # readEx snoops on exclusive blocks
+system.cpu1.l1c.protocol.snoop_readex_modified 6706 # readEx snoops on modified blocks
+system.cpu1.l1c.protocol.snoop_readex_owned 3865 # readEx snoops on owned blocks
+system.cpu1.l1c.protocol.snoop_readex_shared 12512 # readEx snoops on shared blocks
+system.cpu1.l1c.protocol.snoop_upgrade_owned 852 # upgrade snoops on owned blocks
+system.cpu1.l1c.protocol.snoop_upgrade_shared 2973 # upgradee snoops on shared blocks
+system.cpu1.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
+system.cpu1.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
+system.cpu1.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
+system.cpu1.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
+system.cpu1.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
+system.cpu1.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
+system.cpu1.l1c.protocol.write_invalid 61595 # write misses to invalid blocks
+system.cpu1.l1c.protocol.write_owned 1320 # write misses to owned blocks
+system.cpu1.l1c.protocol.write_shared 4183 # write misses to shared blocks
+system.cpu1.l1c.replacements 27139 # number of replacements
+system.cpu1.l1c.sampled_refs 27498 # Sample count of references to valid blocks.
+system.cpu1.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.l1c.tagsinuse 341.113569 # Cycle average of tags in use
+system.cpu1.l1c.total_refs 11408 # Total number of references to valid blocks.
+system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu1.l1c.writebacks 10884 # number of writebacks
+system.cpu1.num_copies 0 # number of copy accesses completed
+system.cpu1.num_reads 98821 # number of read accesses completed
+system.cpu1.num_writes 53366 # number of write accesses completed
+system.cpu2.l1c.ReadReq_accesses 45016 # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.ReadReq_avg_miss_latency 956.031371 # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 880.781951 # average ReadReq mshr miss latency
+system.cpu2.l1c.ReadReq_hits 7529 # number of ReadReq hits
+system.cpu2.l1c.ReadReq_miss_latency 35838748 # number of ReadReq miss cycles
+system.cpu2.l1c.ReadReq_miss_rate 0.832748 # miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_misses 37487 # number of ReadReq misses
+system.cpu2.l1c.ReadReq_mshr_miss_latency 33017873 # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_miss_rate 0.832748 # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_mshr_misses 37487 # number of ReadReq MSHR misses
+system.cpu2.l1c.ReadReq_mshr_uncacheable 9887 # number of ReadReq MSHR uncacheable
+system.cpu2.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
+system.cpu2.l1c.ReadResp_mshr_uncacheable_latency 17582637 # number of ReadResp MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_accesses 24456 # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_avg_miss_latency 859.707355 # average WriteReq miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 777.777296 # average WriteReq mshr miss latency
+system.cpu2.l1c.WriteReq_hits 1165 # number of WriteReq hits
+system.cpu2.l1c.WriteReq_miss_latency 20023444 # number of WriteReq miss cycles
+system.cpu2.l1c.WriteReq_miss_rate 0.952363 # miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_misses 23291 # number of WriteReq misses
+system.cpu2.l1c.WriteReq_mshr_miss_latency 18115211 # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_rate 0.952363 # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_mshr_misses 23291 # number of WriteReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_uncacheable 5362 # number of WriteReq MSHR uncacheable
+system.cpu2.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
+system.cpu2.l1c.WriteResp_mshr_uncacheable_latency 10583136 # number of WriteResp MSHR uncacheable cycles
+system.cpu2.l1c.avg_blocked_cycles_no_mshrs 81.152375 # average number of cycles each access was blocked
+system.cpu2.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu2.l1c.avg_refs 0.404365 # Average number of references to valid blocks.
+system.cpu2.l1c.blocked_no_mshrs 69867 # number of cycles access was blocked
+system.cpu2.l1c.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu2.l1c.blocked_cycles_no_mshrs 5669873 # number of cycles access was blocked
+system.cpu2.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu2.l1c.cache_copies 0 # number of cache copies performed
+system.cpu2.l1c.demand_accesses 69472 # number of demand (read+write) accesses
+system.cpu2.l1c.demand_avg_miss_latency 919.118628 # average overall miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency 841.309092 # average overall mshr miss latency
+system.cpu2.l1c.demand_hits 8694 # number of demand (read+write) hits
+system.cpu2.l1c.demand_miss_latency 55862192 # number of demand (read+write) miss cycles
+system.cpu2.l1c.demand_miss_rate 0.874856 # miss rate for demand accesses
+system.cpu2.l1c.demand_misses 60778 # number of demand (read+write) misses
+system.cpu2.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu2.l1c.demand_mshr_miss_latency 51133084 # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_rate 0.874856 # mshr miss rate for demand accesses
+system.cpu2.l1c.demand_mshr_misses 60778 # number of demand (read+write) MSHR misses
+system.cpu2.l1c.fast_writes 0 # number of fast writes performed
+system.cpu2.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu2.l1c.overall_accesses 69472 # number of overall (read+write) accesses
+system.cpu2.l1c.overall_avg_miss_latency 919.118628 # average overall miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency 841.309092 # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
+system.cpu2.l1c.overall_hits 8694 # number of overall hits
+system.cpu2.l1c.overall_miss_latency 55862192 # number of overall miss cycles
+system.cpu2.l1c.overall_miss_rate 0.874856 # miss rate for overall accesses
+system.cpu2.l1c.overall_misses 60778 # number of overall misses
+system.cpu2.l1c.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu2.l1c.overall_mshr_miss_latency 51133084 # number of overall MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_rate 0.874856 # mshr miss rate for overall accesses
+system.cpu2.l1c.overall_mshr_misses 60778 # number of overall MSHR misses
+system.cpu2.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_misses 15249 # number of overall MSHR uncacheable misses
+system.cpu2.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu2.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu2.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu2.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu2.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu2.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu2.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu2.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu2.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu2.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
+system.cpu2.l1c.protocol.read_invalid 111528 # read misses to invalid blocks
+system.cpu2.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
+system.cpu2.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
+system.cpu2.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
+system.cpu2.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
+system.cpu2.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
+system.cpu2.l1c.protocol.snoop_read_exclusive 2757 # read snoops on exclusive blocks
+system.cpu2.l1c.protocol.snoop_read_modified 12587 # read snoops on modified blocks
+system.cpu2.l1c.protocol.snoop_read_owned 7252 # read snoops on owned blocks
+system.cpu2.l1c.protocol.snoop_read_shared 22967 # read snoops on shared blocks
+system.cpu2.l1c.protocol.snoop_readex_exclusive 1579 # readEx snoops on exclusive blocks
+system.cpu2.l1c.protocol.snoop_readex_modified 6680 # readEx snoops on modified blocks
+system.cpu2.l1c.protocol.snoop_readex_owned 3891 # readEx snoops on owned blocks
+system.cpu2.l1c.protocol.snoop_readex_shared 12468 # readEx snoops on shared blocks
+system.cpu2.l1c.protocol.snoop_upgrade_owned 850 # upgrade snoops on owned blocks
+system.cpu2.l1c.protocol.snoop_upgrade_shared 2951 # upgradee snoops on shared blocks
+system.cpu2.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
+system.cpu2.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
+system.cpu2.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
+system.cpu2.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
+system.cpu2.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
+system.cpu2.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
+system.cpu2.l1c.protocol.write_invalid 57618 # write misses to invalid blocks
+system.cpu2.l1c.protocol.write_owned 1263 # write misses to owned blocks
+system.cpu2.l1c.protocol.write_shared 4251 # write misses to shared blocks
+system.cpu2.l1c.replacements 28062 # number of replacements
+system.cpu2.l1c.sampled_refs 28405 # Sample count of references to valid blocks.
+system.cpu2.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu2.l1c.tagsinuse 344.040679 # Cycle average of tags in use
+system.cpu2.l1c.total_refs 11486 # Total number of references to valid blocks.
+system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu2.l1c.writebacks 11295 # number of writebacks
+system.cpu2.num_copies 0 # number of copy accesses completed
+system.cpu2.num_reads 100000 # number of read accesses completed
+system.cpu2.num_writes 54133 # number of write accesses completed
+system.cpu3.l1c.ReadReq_accesses 44504 # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.ReadReq_avg_miss_latency 968.772953 # average ReadReq miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 892.914985 # average ReadReq mshr miss latency
+system.cpu3.l1c.ReadReq_hits 7428 # number of ReadReq hits
+system.cpu3.l1c.ReadReq_miss_latency 35918226 # number of ReadReq miss cycles
+system.cpu3.l1c.ReadReq_miss_rate 0.833094 # miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_misses 37076 # number of ReadReq misses
+system.cpu3.l1c.ReadReq_mshr_miss_latency 33105716 # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_miss_rate 0.833094 # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_mshr_misses 37076 # number of ReadReq MSHR misses
+system.cpu3.l1c.ReadReq_mshr_uncacheable 9876 # number of ReadReq MSHR uncacheable
+system.cpu3.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
+system.cpu3.l1c.ReadResp_mshr_uncacheable_latency 17594905 # number of ReadResp MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_accesses 24087 # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_avg_miss_latency 868.499565 # average WriteReq miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 784.537397 # average WriteReq mshr miss latency
+system.cpu3.l1c.WriteReq_hits 1117 # number of WriteReq hits
+system.cpu3.l1c.WriteReq_miss_latency 19949435 # number of WriteReq miss cycles
+system.cpu3.l1c.WriteReq_miss_rate 0.953626 # miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_misses 22970 # number of WriteReq misses
+system.cpu3.l1c.WriteReq_mshr_miss_latency 18020824 # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_rate 0.953626 # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_mshr_misses 22970 # number of WriteReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_uncacheable 5355 # number of WriteReq MSHR uncacheable
+system.cpu3.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
+system.cpu3.l1c.WriteResp_mshr_uncacheable_latency 10637792 # number of WriteResp MSHR uncacheable cycles
+system.cpu3.l1c.avg_blocked_cycles_no_mshrs 82.097897 # average number of cycles each access was blocked
+system.cpu3.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu3.l1c.avg_refs 0.411489 # Average number of references to valid blocks.
+system.cpu3.l1c.blocked_no_mshrs 69124 # number of cycles access was blocked
+system.cpu3.l1c.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu3.l1c.blocked_cycles_no_mshrs 5674935 # number of cycles access was blocked
+system.cpu3.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu3.l1c.cache_copies 0 # number of cache copies performed
+system.cpu3.l1c.demand_accesses 68591 # number of demand (read+write) accesses
+system.cpu3.l1c.demand_avg_miss_latency 930.414366 # average overall miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency 851.456217 # average overall mshr miss latency
+system.cpu3.l1c.demand_hits 8545 # number of demand (read+write) hits
+system.cpu3.l1c.demand_miss_latency 55867661 # number of demand (read+write) miss cycles
+system.cpu3.l1c.demand_miss_rate 0.875421 # miss rate for demand accesses
+system.cpu3.l1c.demand_misses 60046 # number of demand (read+write) misses
+system.cpu3.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu3.l1c.demand_mshr_miss_latency 51126540 # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_rate 0.875421 # mshr miss rate for demand accesses
+system.cpu3.l1c.demand_mshr_misses 60046 # number of demand (read+write) MSHR misses
+system.cpu3.l1c.fast_writes 0 # number of fast writes performed
+system.cpu3.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu3.l1c.overall_accesses 68591 # number of overall (read+write) accesses
+system.cpu3.l1c.overall_avg_miss_latency 930.414366 # average overall miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency 851.456217 # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
+system.cpu3.l1c.overall_hits 8545 # number of overall hits
+system.cpu3.l1c.overall_miss_latency 55867661 # number of overall miss cycles
+system.cpu3.l1c.overall_miss_rate 0.875421 # miss rate for overall accesses
+system.cpu3.l1c.overall_misses 60046 # number of overall misses
+system.cpu3.l1c.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu3.l1c.overall_mshr_miss_latency 51126540 # number of overall MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_rate 0.875421 # mshr miss rate for overall accesses
+system.cpu3.l1c.overall_mshr_misses 60046 # number of overall MSHR misses
+system.cpu3.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_misses 15231 # number of overall MSHR uncacheable misses
+system.cpu3.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu3.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu3.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu3.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu3.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu3.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu3.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu3.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu3.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu3.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
+system.cpu3.l1c.protocol.read_invalid 110901 # read misses to invalid blocks
+system.cpu3.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
+system.cpu3.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
+system.cpu3.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
+system.cpu3.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
+system.cpu3.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
+system.cpu3.l1c.protocol.snoop_read_exclusive 2843 # read snoops on exclusive blocks
+system.cpu3.l1c.protocol.snoop_read_modified 12490 # read snoops on modified blocks
+system.cpu3.l1c.protocol.snoop_read_owned 7235 # read snoops on owned blocks
+system.cpu3.l1c.protocol.snoop_read_shared 23011 # read snoops on shared blocks
+system.cpu3.l1c.protocol.snoop_readex_exclusive 1535 # readEx snoops on exclusive blocks
+system.cpu3.l1c.protocol.snoop_readex_modified 6732 # readEx snoops on modified blocks
+system.cpu3.l1c.protocol.snoop_readex_owned 3954 # readEx snoops on owned blocks
+system.cpu3.l1c.protocol.snoop_readex_shared 12354 # readEx snoops on shared blocks
+system.cpu3.l1c.protocol.snoop_upgrade_owned 858 # upgrade snoops on owned blocks
+system.cpu3.l1c.protocol.snoop_upgrade_shared 3087 # upgradee snoops on shared blocks
+system.cpu3.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
+system.cpu3.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
+system.cpu3.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
+system.cpu3.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
+system.cpu3.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
+system.cpu3.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
+system.cpu3.l1c.protocol.write_invalid 59061 # write misses to invalid blocks
+system.cpu3.l1c.protocol.write_owned 1261 # write misses to owned blocks
+system.cpu3.l1c.protocol.write_shared 4235 # write misses to shared blocks
+system.cpu3.l1c.replacements 27216 # number of replacements
+system.cpu3.l1c.sampled_refs 27556 # Sample count of references to valid blocks.
+system.cpu3.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu3.l1c.tagsinuse 341.602377 # Cycle average of tags in use
+system.cpu3.l1c.total_refs 11339 # Total number of references to valid blocks.
+system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu3.l1c.writebacks 10831 # number of writebacks
+system.cpu3.num_copies 0 # number of copy accesses completed
+system.cpu3.num_reads 98893 # number of read accesses completed
+system.cpu3.num_writes 53654 # number of write accesses completed
+system.cpu4.l1c.ReadReq_accesses 44272 # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.ReadReq_avg_miss_latency 976.655364 # average ReadReq miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 901.292278 # average ReadReq mshr miss latency
+system.cpu4.l1c.ReadReq_hits 7468 # number of ReadReq hits
+system.cpu4.l1c.ReadReq_miss_latency 35944824 # number of ReadReq miss cycles
+system.cpu4.l1c.ReadReq_miss_rate 0.831316 # miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_misses 36804 # number of ReadReq misses
+system.cpu4.l1c.ReadReq_mshr_miss_latency 33171161 # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_miss_rate 0.831316 # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_mshr_misses 36804 # number of ReadReq MSHR misses
+system.cpu4.l1c.ReadReq_mshr_uncacheable 9822 # number of ReadReq MSHR uncacheable
+system.cpu4.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
+system.cpu4.l1c.ReadResp_mshr_uncacheable_latency 17532387 # number of ReadResp MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_accesses 23994 # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_avg_miss_latency 874.063859 # average WriteReq miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 788.017488 # average WriteReq mshr miss latency
+system.cpu4.l1c.WriteReq_hits 1178 # number of WriteReq hits
+system.cpu4.l1c.WriteReq_miss_latency 19942641 # number of WriteReq miss cycles
+system.cpu4.l1c.WriteReq_miss_rate 0.950904 # miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_misses 22816 # number of WriteReq misses
+system.cpu4.l1c.WriteReq_mshr_miss_latency 17979407 # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_rate 0.950904 # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_mshr_misses 22816 # number of WriteReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_uncacheable 5315 # number of WriteReq MSHR uncacheable
+system.cpu4.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
+system.cpu4.l1c.WriteResp_mshr_uncacheable_latency 10563676 # number of WriteResp MSHR uncacheable cycles
+system.cpu4.l1c.avg_blocked_cycles_no_mshrs 82.703233 # average number of cycles each access was blocked
+system.cpu4.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu4.l1c.avg_refs 0.416368 # Average number of references to valid blocks.
+system.cpu4.l1c.blocked_no_mshrs 68707 # number of cycles access was blocked
+system.cpu4.l1c.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu4.l1c.blocked_cycles_no_mshrs 5682291 # number of cycles access was blocked
+system.cpu4.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu4.l1c.cache_copies 0 # number of cache copies performed
+system.cpu4.l1c.demand_accesses 68266 # number of demand (read+write) accesses
+system.cpu4.l1c.demand_avg_miss_latency 937.394582 # average overall miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency 857.943106 # average overall mshr miss latency
+system.cpu4.l1c.demand_hits 8646 # number of demand (read+write) hits
+system.cpu4.l1c.demand_miss_latency 55887465 # number of demand (read+write) miss cycles
+system.cpu4.l1c.demand_miss_rate 0.873348 # miss rate for demand accesses
+system.cpu4.l1c.demand_misses 59620 # number of demand (read+write) misses
+system.cpu4.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu4.l1c.demand_mshr_miss_latency 51150568 # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_rate 0.873348 # mshr miss rate for demand accesses
+system.cpu4.l1c.demand_mshr_misses 59620 # number of demand (read+write) MSHR misses
+system.cpu4.l1c.fast_writes 0 # number of fast writes performed
+system.cpu4.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu4.l1c.overall_accesses 68266 # number of overall (read+write) accesses
+system.cpu4.l1c.overall_avg_miss_latency 937.394582 # average overall miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency 857.943106 # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
+system.cpu4.l1c.overall_hits 8646 # number of overall hits
+system.cpu4.l1c.overall_miss_latency 55887465 # number of overall miss cycles
+system.cpu4.l1c.overall_miss_rate 0.873348 # miss rate for overall accesses
+system.cpu4.l1c.overall_misses 59620 # number of overall misses
+system.cpu4.l1c.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu4.l1c.overall_mshr_miss_latency 51150568 # number of overall MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_rate 0.873348 # mshr miss rate for overall accesses
+system.cpu4.l1c.overall_mshr_misses 59620 # number of overall MSHR misses
+system.cpu4.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_uncacheable_misses 15137 # number of overall MSHR uncacheable misses
+system.cpu4.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu4.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu4.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu4.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu4.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu4.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu4.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu4.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu4.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu4.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
+system.cpu4.l1c.protocol.read_invalid 113154 # read misses to invalid blocks
+system.cpu4.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
+system.cpu4.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
+system.cpu4.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
+system.cpu4.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
+system.cpu4.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
+system.cpu4.l1c.protocol.snoop_read_exclusive 2804 # read snoops on exclusive blocks
+system.cpu4.l1c.protocol.snoop_read_modified 12453 # read snoops on modified blocks
+system.cpu4.l1c.protocol.snoop_read_owned 7418 # read snoops on owned blocks
+system.cpu4.l1c.protocol.snoop_read_shared 23136 # read snoops on shared blocks
+system.cpu4.l1c.protocol.snoop_readex_exclusive 1528 # readEx snoops on exclusive blocks
+system.cpu4.l1c.protocol.snoop_readex_modified 6607 # readEx snoops on modified blocks
+system.cpu4.l1c.protocol.snoop_readex_owned 3922 # readEx snoops on owned blocks
+system.cpu4.l1c.protocol.snoop_readex_shared 12524 # readEx snoops on shared blocks
+system.cpu4.l1c.protocol.snoop_upgrade_owned 843 # upgrade snoops on owned blocks
+system.cpu4.l1c.protocol.snoop_upgrade_shared 2904 # upgradee snoops on shared blocks
+system.cpu4.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
+system.cpu4.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
+system.cpu4.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
+system.cpu4.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
+system.cpu4.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
+system.cpu4.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
+system.cpu4.l1c.protocol.write_invalid 59622 # write misses to invalid blocks
+system.cpu4.l1c.protocol.write_owned 1265 # write misses to owned blocks
+system.cpu4.l1c.protocol.write_shared 4187 # write misses to shared blocks
+system.cpu4.l1c.replacements 27000 # number of replacements
+system.cpu4.l1c.sampled_refs 27346 # Sample count of references to valid blocks.
+system.cpu4.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu4.l1c.tagsinuse 342.121323 # Cycle average of tags in use
+system.cpu4.l1c.total_refs 11386 # Total number of references to valid blocks.
+system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu4.l1c.writebacks 10847 # number of writebacks
+system.cpu4.num_copies 0 # number of copy accesses completed
+system.cpu4.num_reads 98882 # number of read accesses completed
+system.cpu4.num_writes 53288 # number of write accesses completed
+system.cpu5.l1c.ReadReq_accesses 44218 # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.ReadReq_avg_miss_latency 975.652027 # average ReadReq miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 898.818359 # average ReadReq mshr miss latency
+system.cpu5.l1c.ReadReq_hits 7310 # number of ReadReq hits
+system.cpu5.l1c.ReadReq_miss_latency 36009365 # number of ReadReq miss cycles
+system.cpu5.l1c.ReadReq_miss_rate 0.834683 # miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_misses 36908 # number of ReadReq misses
+system.cpu5.l1c.ReadReq_mshr_miss_latency 33173588 # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_miss_rate 0.834683 # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_mshr_misses 36908 # number of ReadReq MSHR misses
+system.cpu5.l1c.ReadReq_mshr_uncacheable 9866 # number of ReadReq MSHR uncacheable
+system.cpu5.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
+system.cpu5.l1c.ReadResp_mshr_uncacheable_latency 17625443 # number of ReadResp MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_accesses 23923 # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_avg_miss_latency 873.308611 # average WriteReq miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 788.173188 # average WriteReq mshr miss latency
+system.cpu5.l1c.WriteReq_hits 1150 # number of WriteReq hits
+system.cpu5.l1c.WriteReq_miss_latency 19887857 # number of WriteReq miss cycles
+system.cpu5.l1c.WriteReq_miss_rate 0.951929 # miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_misses 22773 # number of WriteReq misses
+system.cpu5.l1c.WriteReq_mshr_miss_latency 17949068 # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_rate 0.951929 # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_mshr_misses 22773 # number of WriteReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_uncacheable 5207 # number of WriteReq MSHR uncacheable
+system.cpu5.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
+system.cpu5.l1c.WriteResp_mshr_uncacheable_latency 10374807 # number of WriteResp MSHR uncacheable cycles
+system.cpu5.l1c.avg_blocked_cycles_no_mshrs 82.590363 # average number of cycles each access was blocked
+system.cpu5.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu5.l1c.avg_refs 0.413664 # Average number of references to valid blocks.
+system.cpu5.l1c.blocked_no_mshrs 68944 # number of cycles access was blocked
+system.cpu5.l1c.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu5.l1c.blocked_cycles_no_mshrs 5694110 # number of cycles access was blocked
+system.cpu5.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu5.l1c.cache_copies 0 # number of cache copies performed
+system.cpu5.l1c.demand_accesses 68141 # number of demand (read+write) accesses
+system.cpu5.l1c.demand_avg_miss_latency 936.599956 # average overall miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency 856.598515 # average overall mshr miss latency
+system.cpu5.l1c.demand_hits 8460 # number of demand (read+write) hits
+system.cpu5.l1c.demand_miss_latency 55897222 # number of demand (read+write) miss cycles
+system.cpu5.l1c.demand_miss_rate 0.875846 # miss rate for demand accesses
+system.cpu5.l1c.demand_misses 59681 # number of demand (read+write) misses
+system.cpu5.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu5.l1c.demand_mshr_miss_latency 51122656 # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_rate 0.875846 # mshr miss rate for demand accesses
+system.cpu5.l1c.demand_mshr_misses 59681 # number of demand (read+write) MSHR misses
+system.cpu5.l1c.fast_writes 0 # number of fast writes performed
+system.cpu5.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu5.l1c.overall_accesses 68141 # number of overall (read+write) accesses
+system.cpu5.l1c.overall_avg_miss_latency 936.599956 # average overall miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency 856.598515 # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
+system.cpu5.l1c.overall_hits 8460 # number of overall hits
+system.cpu5.l1c.overall_miss_latency 55897222 # number of overall miss cycles
+system.cpu5.l1c.overall_miss_rate 0.875846 # miss rate for overall accesses
+system.cpu5.l1c.overall_misses 59681 # number of overall misses
+system.cpu5.l1c.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu5.l1c.overall_mshr_miss_latency 51122656 # number of overall MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_rate 0.875846 # mshr miss rate for overall accesses
+system.cpu5.l1c.overall_mshr_misses 59681 # number of overall MSHR misses
+system.cpu5.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_misses 15073 # number of overall MSHR uncacheable misses
+system.cpu5.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu5.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu5.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu5.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu5.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu5.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu5.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu5.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu5.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu5.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
+system.cpu5.l1c.protocol.read_invalid 114279 # read misses to invalid blocks
+system.cpu5.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
+system.cpu5.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
+system.cpu5.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
+system.cpu5.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
+system.cpu5.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
+system.cpu5.l1c.protocol.snoop_read_exclusive 2860 # read snoops on exclusive blocks
+system.cpu5.l1c.protocol.snoop_read_modified 12253 # read snoops on modified blocks
+system.cpu5.l1c.protocol.snoop_read_owned 7231 # read snoops on owned blocks
+system.cpu5.l1c.protocol.snoop_read_shared 23182 # read snoops on shared blocks
+system.cpu5.l1c.protocol.snoop_readex_exclusive 1499 # readEx snoops on exclusive blocks
+system.cpu5.l1c.protocol.snoop_readex_modified 6757 # readEx snoops on modified blocks
+system.cpu5.l1c.protocol.snoop_readex_owned 3896 # readEx snoops on owned blocks
+system.cpu5.l1c.protocol.snoop_readex_shared 12461 # readEx snoops on shared blocks
+system.cpu5.l1c.protocol.snoop_upgrade_owned 887 # upgrade snoops on owned blocks
+system.cpu5.l1c.protocol.snoop_upgrade_shared 3020 # upgradee snoops on shared blocks
+system.cpu5.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
+system.cpu5.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
+system.cpu5.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
+system.cpu5.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
+system.cpu5.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
+system.cpu5.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
+system.cpu5.l1c.protocol.write_invalid 60969 # write misses to invalid blocks
+system.cpu5.l1c.protocol.write_owned 1349 # write misses to owned blocks
+system.cpu5.l1c.protocol.write_shared 4191 # write misses to shared blocks
+system.cpu5.l1c.replacements 26828 # number of replacements
+system.cpu5.l1c.sampled_refs 27196 # Sample count of references to valid blocks.
+system.cpu5.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu5.l1c.tagsinuse 340.865502 # Cycle average of tags in use
+system.cpu5.l1c.total_refs 11250 # Total number of references to valid blocks.
+system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu5.l1c.writebacks 10567 # number of writebacks
+system.cpu5.num_copies 0 # number of copy accesses completed
+system.cpu5.num_reads 97882 # number of read accesses completed
+system.cpu5.num_writes 52965 # number of write accesses completed
+system.cpu6.l1c.ReadReq_accesses 44971 # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.ReadReq_avg_miss_latency 967.006541 # average ReadReq miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 890.563660 # average ReadReq mshr miss latency
+system.cpu6.l1c.ReadReq_hits 7514 # number of ReadReq hits
+system.cpu6.l1c.ReadReq_miss_latency 36221164 # number of ReadReq miss cycles
+system.cpu6.l1c.ReadReq_miss_rate 0.832915 # miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_misses 37457 # number of ReadReq misses
+system.cpu6.l1c.ReadReq_mshr_miss_latency 33357843 # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_miss_rate 0.832915 # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_mshr_misses 37457 # number of ReadReq MSHR misses
+system.cpu6.l1c.ReadReq_mshr_uncacheable 9684 # number of ReadReq MSHR uncacheable
+system.cpu6.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
+system.cpu6.l1c.ReadResp_mshr_uncacheable_latency 17275344 # number of ReadResp MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_accesses 23996 # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_avg_miss_latency 873.777515 # average WriteReq miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 790.631514 # average WriteReq mshr miss latency
+system.cpu6.l1c.WriteReq_hits 1181 # number of WriteReq hits
+system.cpu6.l1c.WriteReq_miss_latency 19935234 # number of WriteReq miss cycles
+system.cpu6.l1c.WriteReq_miss_rate 0.950783 # miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_misses 22815 # number of WriteReq misses
+system.cpu6.l1c.WriteReq_mshr_miss_latency 18038258 # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_rate 0.950783 # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_mshr_misses 22815 # number of WriteReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_uncacheable 5345 # number of WriteReq MSHR uncacheable
+system.cpu6.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
+system.cpu6.l1c.WriteResp_mshr_uncacheable_latency 10602140 # number of WriteResp MSHR uncacheable cycles
+system.cpu6.l1c.avg_blocked_cycles_no_mshrs 82.071085 # average number of cycles each access was blocked
+system.cpu6.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu6.l1c.avg_refs 0.412251 # Average number of references to valid blocks.
+system.cpu6.l1c.blocked_no_mshrs 69157 # number of cycles access was blocked
+system.cpu6.l1c.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu6.l1c.blocked_cycles_no_mshrs 5675790 # number of cycles access was blocked
+system.cpu6.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu6.l1c.cache_copies 0 # number of cache copies performed
+system.cpu6.l1c.demand_accesses 68967 # number of demand (read+write) accesses
+system.cpu6.l1c.demand_avg_miss_latency 931.716187 # average overall miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency 852.735947 # average overall mshr miss latency
+system.cpu6.l1c.demand_hits 8695 # number of demand (read+write) hits
+system.cpu6.l1c.demand_miss_latency 56156398 # number of demand (read+write) miss cycles
+system.cpu6.l1c.demand_miss_rate 0.873925 # miss rate for demand accesses
+system.cpu6.l1c.demand_misses 60272 # number of demand (read+write) misses
+system.cpu6.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu6.l1c.demand_mshr_miss_latency 51396101 # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_rate 0.873925 # mshr miss rate for demand accesses
+system.cpu6.l1c.demand_mshr_misses 60272 # number of demand (read+write) MSHR misses
+system.cpu6.l1c.fast_writes 0 # number of fast writes performed
+system.cpu6.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu6.l1c.overall_accesses 68967 # number of overall (read+write) accesses
+system.cpu6.l1c.overall_avg_miss_latency 931.716187 # average overall miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency 852.735947 # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
+system.cpu6.l1c.overall_hits 8695 # number of overall hits
+system.cpu6.l1c.overall_miss_latency 56156398 # number of overall miss cycles
+system.cpu6.l1c.overall_miss_rate 0.873925 # miss rate for overall accesses
+system.cpu6.l1c.overall_misses 60272 # number of overall misses
+system.cpu6.l1c.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu6.l1c.overall_mshr_miss_latency 51396101 # number of overall MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_rate 0.873925 # mshr miss rate for overall accesses
+system.cpu6.l1c.overall_mshr_misses 60272 # number of overall MSHR misses
+system.cpu6.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_misses 15029 # number of overall MSHR uncacheable misses
+system.cpu6.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu6.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu6.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu6.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu6.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu6.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu6.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu6.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu6.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu6.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
+system.cpu6.l1c.protocol.read_invalid 114488 # read misses to invalid blocks
+system.cpu6.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
+system.cpu6.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
+system.cpu6.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
+system.cpu6.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
+system.cpu6.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
+system.cpu6.l1c.protocol.snoop_read_exclusive 2876 # read snoops on exclusive blocks
+system.cpu6.l1c.protocol.snoop_read_modified 12371 # read snoops on modified blocks
+system.cpu6.l1c.protocol.snoop_read_owned 7223 # read snoops on owned blocks
+system.cpu6.l1c.protocol.snoop_read_shared 23305 # read snoops on shared blocks
+system.cpu6.l1c.protocol.snoop_readex_exclusive 1616 # readEx snoops on exclusive blocks
+system.cpu6.l1c.protocol.snoop_readex_modified 6693 # readEx snoops on modified blocks
+system.cpu6.l1c.protocol.snoop_readex_owned 3909 # readEx snoops on owned blocks
+system.cpu6.l1c.protocol.snoop_readex_shared 12446 # readEx snoops on shared blocks
+system.cpu6.l1c.protocol.snoop_upgrade_owned 833 # upgrade snoops on owned blocks
+system.cpu6.l1c.protocol.snoop_upgrade_shared 2948 # upgradee snoops on shared blocks
+system.cpu6.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
+system.cpu6.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
+system.cpu6.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
+system.cpu6.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
+system.cpu6.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
+system.cpu6.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
+system.cpu6.l1c.protocol.write_invalid 58413 # write misses to invalid blocks
+system.cpu6.l1c.protocol.write_owned 1374 # write misses to owned blocks
+system.cpu6.l1c.protocol.write_shared 4109 # write misses to shared blocks
+system.cpu6.l1c.replacements 27477 # number of replacements
+system.cpu6.l1c.sampled_refs 27835 # Sample count of references to valid blocks.
+system.cpu6.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu6.l1c.tagsinuse 342.134742 # Cycle average of tags in use
+system.cpu6.l1c.total_refs 11475 # Total number of references to valid blocks.
+system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu6.l1c.writebacks 10759 # number of writebacks
+system.cpu6.num_copies 0 # number of copy accesses completed
+system.cpu6.num_reads 99303 # number of read accesses completed
+system.cpu6.num_writes 53385 # number of write accesses completed
+system.cpu7.l1c.ReadReq_accesses 44438 # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.ReadReq_avg_miss_latency 975.306986 # average ReadReq miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 899.340271 # average ReadReq mshr miss latency
+system.cpu7.l1c.ReadReq_hits 7394 # number of ReadReq hits
+system.cpu7.l1c.ReadReq_miss_latency 36129272 # number of ReadReq miss cycles
+system.cpu7.l1c.ReadReq_miss_rate 0.833611 # miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_misses 37044 # number of ReadReq misses
+system.cpu7.l1c.ReadReq_mshr_miss_latency 33315161 # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate 0.833611 # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_mshr_misses 37044 # number of ReadReq MSHR misses
+system.cpu7.l1c.ReadReq_mshr_uncacheable 9861 # number of ReadReq MSHR uncacheable
+system.cpu7.l1c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
+system.cpu7.l1c.ReadResp_mshr_uncacheable_latency 17576395 # number of ReadResp MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_accesses 23999 # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_avg_miss_latency 861.568979 # average WriteReq miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 776.580264 # average WriteReq mshr miss latency
+system.cpu7.l1c.WriteReq_hits 1137 # number of WriteReq hits
+system.cpu7.l1c.WriteReq_miss_latency 19697190 # number of WriteReq miss cycles
+system.cpu7.l1c.WriteReq_miss_rate 0.952623 # miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_misses 22862 # number of WriteReq misses
+system.cpu7.l1c.WriteReq_mshr_miss_latency 17754178 # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_rate 0.952623 # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_mshr_misses 22862 # number of WriteReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_uncacheable 5386 # number of WriteReq MSHR uncacheable
+system.cpu7.l1c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
+system.cpu7.l1c.WriteResp_mshr_uncacheable_latency 10720857 # number of WriteResp MSHR uncacheable cycles
+system.cpu7.l1c.avg_blocked_cycles_no_mshrs 82.167211 # average number of cycles each access was blocked
+system.cpu7.l1c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu7.l1c.avg_refs 0.419292 # Average number of references to valid blocks.
+system.cpu7.l1c.blocked_no_mshrs 68907 # number of cycles access was blocked
+system.cpu7.l1c.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu7.l1c.blocked_cycles_no_mshrs 5661896 # number of cycles access was blocked
+system.cpu7.l1c.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.cpu7.l1c.cache_copies 0 # number of cache copies performed
+system.cpu7.l1c.demand_accesses 68437 # number of demand (read+write) accesses
+system.cpu7.l1c.demand_avg_miss_latency 931.901012 # average overall miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency 852.491220 # average overall mshr miss latency
+system.cpu7.l1c.demand_hits 8531 # number of demand (read+write) hits
+system.cpu7.l1c.demand_miss_latency 55826462 # number of demand (read+write) miss cycles
+system.cpu7.l1c.demand_miss_rate 0.875345 # miss rate for demand accesses
+system.cpu7.l1c.demand_misses 59906 # number of demand (read+write) misses
+system.cpu7.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
+system.cpu7.l1c.demand_mshr_miss_latency 51069339 # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_rate 0.875345 # mshr miss rate for demand accesses
+system.cpu7.l1c.demand_mshr_misses 59906 # number of demand (read+write) MSHR misses
+system.cpu7.l1c.fast_writes 0 # number of fast writes performed
+system.cpu7.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu7.l1c.overall_accesses 68437 # number of overall (read+write) accesses
+system.cpu7.l1c.overall_avg_miss_latency 931.901012 # average overall miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency 852.491220 # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
+system.cpu7.l1c.overall_hits 8531 # number of overall hits
+system.cpu7.l1c.overall_miss_latency 55826462 # number of overall miss cycles
+system.cpu7.l1c.overall_miss_rate 0.875345 # miss rate for overall accesses
+system.cpu7.l1c.overall_misses 59906 # number of overall misses
+system.cpu7.l1c.overall_mshr_hits 0 # number of overall MSHR hits
+system.cpu7.l1c.overall_mshr_miss_latency 51069339 # number of overall MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_rate 0.875345 # mshr miss rate for overall accesses
+system.cpu7.l1c.overall_mshr_misses 59906 # number of overall MSHR misses
+system.cpu7.l1c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_misses 15247 # number of overall MSHR uncacheable misses
+system.cpu7.l1c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.cpu7.l1c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.cpu7.l1c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.cpu7.l1c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.cpu7.l1c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.cpu7.l1c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.cpu7.l1c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.cpu7.l1c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.cpu7.l1c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu7.l1c.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blocks
+system.cpu7.l1c.protocol.read_invalid 115064 # read misses to invalid blocks
+system.cpu7.l1c.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blocks
+system.cpu7.l1c.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blocks
+system.cpu7.l1c.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blocks
+system.cpu7.l1c.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blocks
+system.cpu7.l1c.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blocks
+system.cpu7.l1c.protocol.snoop_read_exclusive 2793 # read snoops on exclusive blocks
+system.cpu7.l1c.protocol.snoop_read_modified 12588 # read snoops on modified blocks
+system.cpu7.l1c.protocol.snoop_read_owned 7412 # read snoops on owned blocks
+system.cpu7.l1c.protocol.snoop_read_shared 23048 # read snoops on shared blocks
+system.cpu7.l1c.protocol.snoop_readex_exclusive 1548 # readEx snoops on exclusive blocks
+system.cpu7.l1c.protocol.snoop_readex_modified 6593 # readEx snoops on modified blocks
+system.cpu7.l1c.protocol.snoop_readex_owned 3944 # readEx snoops on owned blocks
+system.cpu7.l1c.protocol.snoop_readex_shared 12404 # readEx snoops on shared blocks
+system.cpu7.l1c.protocol.snoop_upgrade_owned 919 # upgrade snoops on owned blocks
+system.cpu7.l1c.protocol.snoop_upgrade_shared 2959 # upgradee snoops on shared blocks
+system.cpu7.l1c.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blocks
+system.cpu7.l1c.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blocks
+system.cpu7.l1c.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blocks
+system.cpu7.l1c.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blocks
+system.cpu7.l1c.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blocks
+system.cpu7.l1c.protocol.swpf_invalid 0 # soft prefetch misses to invalid blocks
+system.cpu7.l1c.protocol.write_invalid 58173 # write misses to invalid blocks
+system.cpu7.l1c.protocol.write_owned 1351 # write misses to owned blocks
+system.cpu7.l1c.protocol.write_shared 4494 # write misses to shared blocks
+system.cpu7.l1c.replacements 27080 # number of replacements
+system.cpu7.l1c.sampled_refs 27420 # Sample count of references to valid blocks.
+system.cpu7.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu7.l1c.tagsinuse 342.061742 # Cycle average of tags in use
+system.cpu7.l1c.total_refs 11497 # Total number of references to valid blocks.
+system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu7.l1c.writebacks 10789 # number of writebacks
+system.cpu7.num_copies 0 # number of copy accesses completed
+system.cpu7.num_reads 98350 # number of read accesses completed
+system.cpu7.num_writes 53282 # number of write accesses completed
+system.l2c.ReadExReq_accesses 75399 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency 89.483714 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 6.467886 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_hits 39632 # number of ReadExReq hits
+system.l2c.ReadExReq_miss_latency 3200564 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate 0.474370 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses 35767 # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_hits 4 # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_miss_latency 231311 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate 0.474317 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_misses 35763 # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses 138997 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency 89.683271 # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 6.196645 # average ReadReq mshr miss latency
+system.l2c.ReadReq_hits 72568 # number of ReadReq hits
+system.l2c.ReadReq_miss_latency 5957570 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate 0.477917 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses 66429 # number of ReadReq misses
+system.l2c.ReadReq_mshr_hits 15 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_miss_latency 411544 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate 0.477809 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses 66414 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable 78703 # number of ReadReq MSHR uncacheable
+system.l2c.ReadResp_avg_mshr_uncacheable_latency inf # average ReadResp mshr uncacheable latency
+system.l2c.ReadResp_mshr_uncacheable_latency 420484 # number of ReadResp MSHR uncacheable cycles
+system.l2c.WriteReqNoAck|Writeback_accesses 86614 # number of WriteReqNoAck|Writeback accesses(hits+misses)
+system.l2c.WriteReqNoAck|Writeback_hits 18299 # number of WriteReqNoAck|Writeback hits
+system.l2c.WriteReqNoAck|Writeback_miss_rate 0.788729 # miss rate for WriteReqNoAck|Writeback accesses
+system.l2c.WriteReqNoAck|Writeback_misses 68315 # number of WriteReqNoAck|Writeback misses
+system.l2c.WriteReqNoAck|Writeback_mshr_miss_rate 0.788729 # mshr miss rate for WriteReqNoAck|Writeback accesses
+system.l2c.WriteReqNoAck|Writeback_mshr_misses 68315 # number of WriteReqNoAck|Writeback MSHR misses
+system.l2c.WriteReq_mshr_uncacheable 42661 # number of WriteReq MSHR uncacheable
+system.l2c.WriteResp_avg_mshr_uncacheable_latency inf # average WriteResp mshr uncacheable latency
+system.l2c.WriteResp_mshr_uncacheable_latency 298282 # number of WriteResp MSHR uncacheable cycles
+system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.l2c.avg_refs 1.277186 # Average number of references to valid blocks.
+system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_no_targets 0 # number of cycles access was blocked
+system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.demand_accesses 138997 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency 89.683271 # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency 6.196645 # average overall mshr miss latency
+system.l2c.demand_hits 72568 # number of demand (read+write) hits
+system.l2c.demand_miss_latency 5957570 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate 0.477917 # miss rate for demand accesses
+system.l2c.demand_misses 66429 # number of demand (read+write) misses
+system.l2c.demand_mshr_hits 15 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency 411544 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate 0.477809 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses 66414 # number of demand (read+write) MSHR misses
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.l2c.overall_accesses 225611 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency 44.213991 # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 6.196645 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_uncacheable_latency 0 # average overall mshr uncacheable latency
+system.l2c.overall_hits 90867 # number of overall hits
+system.l2c.overall_miss_latency 5957570 # number of overall miss cycles
+system.l2c.overall_miss_rate 0.597240 # miss rate for overall accesses
+system.l2c.overall_misses 134744 # number of overall misses
+system.l2c.overall_mshr_hits 15 # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency 411544 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate 0.294374 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses 66414 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_misses 121364 # number of overall MSHR uncacheable misses
+system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
+system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr
+system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue
+system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
+system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified
+system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued
+system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
+system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
+system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
+system.l2c.replacements 101153 # number of replacements
+system.l2c.sampled_refs 102177 # Sample count of references to valid blocks.
+system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.l2c.tagsinuse 1022.647312 # Cycle average of tags in use
+system.l2c.total_refs 130499 # Total number of references to valid blocks.
+system.l2c.warmup_cycle 31838 # Cycle when the warmup percentage was hit.
+system.l2c.writebacks 15786 # number of writebacks
+
+---------- End Simulation Statistics ----------
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr
new file mode 100644
index 0000000..1658029
--- /dev/null
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr
@@ -0,0 +1,74 @@
+warn: Entering event queue @ 0. Starting simulation...
+system.cpu2: completed 10000 read accesses @573559
+system.cpu1: completed 10000 read accesses @574452
+system.cpu4: completed 10000 read accesses @578704
+system.cpu6: completed 10000 read accesses @579414
+system.cpu0: completed 10000 read accesses @588706
+system.cpu5: completed 10000 read accesses @590846
+system.cpu7: completed 10000 read accesses @592958
+system.cpu3: completed 10000 read accesses @604807
+system.cpu2: completed 20000 read accesses @1142209
+system.cpu1: completed 20000 read accesses @1143294
+system.cpu6: completed 20000 read accesses @1150506
+system.cpu4: completed 20000 read accesses @1152288
+system.cpu0: completed 20000 read accesses @1160537
+system.cpu3: completed 20000 read accesses @1175338
+system.cpu5: completed 20000 read accesses @1175648
+system.cpu7: completed 20000 read accesses @1180960
+system.cpu6: completed 30000 read accesses @1716218
+system.cpu3: completed 30000 read accesses @1728281
+system.cpu1: completed 30000 read accesses @1735983
+system.cpu0: completed 30000 read accesses @1736422
+system.cpu2: completed 30000 read accesses @1739692
+system.cpu4: completed 30000 read accesses @1746362
+system.cpu5: completed 30000 read accesses @1766199
+system.cpu7: completed 30000 read accesses @1783424
+system.cpu6: completed 40000 read accesses @2281651
+system.cpu0: completed 40000 read accesses @2300760
+system.cpu3: completed 40000 read accesses @2312993
+system.cpu2: completed 40000 read accesses @2314026
+system.cpu4: completed 40000 read accesses @2332178
+system.cpu1: completed 40000 read accesses @2336380
+system.cpu5: completed 40000 read accesses @2349370
+system.cpu7: completed 40000 read accesses @2365352
+system.cpu6: completed 50000 read accesses @2863317
+system.cpu0: completed 50000 read accesses @2878182
+system.cpu2: completed 50000 read accesses @2884989
+system.cpu3: completed 50000 read accesses @2897940
+system.cpu4: completed 50000 read accesses @2918842
+system.cpu1: completed 50000 read accesses @2929102
+system.cpu5: completed 50000 read accesses @2938269
+system.cpu7: completed 50000 read accesses @2944872
+system.cpu6: completed 60000 read accesses @3435715
+system.cpu2: completed 60000 read accesses @3454809
+system.cpu0: completed 60000 read accesses @3462986
+system.cpu3: completed 60000 read accesses @3485243
+system.cpu4: completed 60000 read accesses @3498361
+system.cpu1: completed 60000 read accesses @3501000
+system.cpu5: completed 60000 read accesses @3516984
+system.cpu7: completed 60000 read accesses @3517323
+system.cpu6: completed 70000 read accesses @4032530
+system.cpu0: completed 70000 read accesses @4041457
+system.cpu2: completed 70000 read accesses @4043695
+system.cpu7: completed 70000 read accesses @4070977
+system.cpu1: completed 70000 read accesses @4075964
+system.cpu4: completed 70000 read accesses @4076518
+system.cpu3: completed 70000 read accesses @4082470
+system.cpu5: completed 70000 read accesses @4104778
+system.cpu0: completed 80000 read accesses @4610101
+system.cpu2: completed 80000 read accesses @4622528
+system.cpu6: completed 80000 read accesses @4627690
+system.cpu1: completed 80000 read accesses @4654033
+system.cpu4: completed 80000 read accesses @4661016
+system.cpu3: completed 80000 read accesses @4662752
+system.cpu7: completed 80000 read accesses @4668924
+system.cpu5: completed 80000 read accesses @4689767
+system.cpu2: completed 90000 read accesses @5186824
+system.cpu0: completed 90000 read accesses @5189006
+system.cpu6: completed 90000 read accesses @5214829
+system.cpu1: completed 90000 read accesses @5229787
+system.cpu3: completed 90000 read accesses @5235400
+system.cpu4: completed 90000 read accesses @5240445
+system.cpu7: completed 90000 read accesses @5254426
+system.cpu5: completed 90000 read accesses @5292462
+system.cpu2: completed 100000 read accesses @5755736
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout
new file mode 100644
index 0000000..3d3289d
--- /dev/null
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout
@@ -0,0 +1,18 @@
+M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Feb 6 2007 20:30:01
+M5 started Tue Feb 6 21:04:07 2007
+M5 executing on vm1
+command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest
+warning: overwriting port funcmem.functional value cpu1.functional with cpu2.functional
+warning: overwriting port funcmem.functional value cpu2.functional with cpu3.functional
+warning: overwriting port funcmem.functional value cpu3.functional with cpu4.functional
+warning: overwriting port funcmem.functional value cpu4.functional with cpu5.functional
+warning: overwriting port funcmem.functional value cpu5.functional with cpu6.functional
+warning: overwriting port funcmem.functional value cpu6.functional with cpu7.functional
+Exiting @ tick 5755736 because Maximum number of loads reached!
diff --git a/tests/quick/50.memtest/test.py b/tests/quick/50.memtest/test.py
index e894b8f..90beae0 100644
--- a/tests/quick/50.memtest/test.py
+++ b/tests/quick/50.memtest/test.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -26,3 +26,5 @@
#
# Authors: Ron Dreslinski
+MemTest.max_loads=1e5
+MemTest.progress_interval=1e4
diff --git a/util/tracediff b/util/tracediff
index b25efe9..3633fdb 100755
--- a/util/tracediff
+++ b/util/tracediff
@@ -1,5 +1,5 @@
#! /usr/bin/env perl
-# Copyright (c) 2003-2006 The Regents of The University of Michigan
+# Copyright (c) 2003-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -60,6 +60,8 @@
# run only).
#
+use FindBin;
+
if (@ARGV < 2) {
die "Usage: tracediff \"sim1|sim2\" [common-arg \"arg1|arg2\" ...]\n";
}
@@ -101,9 +103,9 @@
$cmd1 = "$sim1 -d $dir1 $args1 2>&1 |";
$cmd2 = "$sim2 -d $dir2 $args2 2>&1 |";
-# This only works if you have rundiff in your path. I just edit it
-# with an explicit path if necessary.
-$fullcmd = "rundiff '$cmd1' '$cmd2' 2>&1 > tracediff-$$.out";
+# Expect that rundiff is in the same dir as the tracediff script.
+# FindBin figures that out for us.
+$fullcmd = "$FindBin::Bin/rundiff '$cmd1' '$cmd2' 2>&1 > tracediff-$$.out";
print "Executing $fullcmd\n";
system($fullcmd);
