arch, cpu: Add support for flattening misc register indexes.
With ARMv8 support the same misc register id results in accessing different
registers depending on the current mode of the processor. This patch adds
the same orthogonality to the misc register file as the others (int, float, cc).
For all the othre ISAs this is currently a null-implementation.
Additionally, a system variable is added to all the ISA objects.
diff --git a/src/arch/mips/MipsISA.py b/src/arch/mips/MipsISA.py
index bc969a9..22602ff 100644
--- a/src/arch/mips/MipsISA.py
+++ b/src/arch/mips/MipsISA.py
@@ -37,11 +37,14 @@
from m5.SimObject import SimObject
from m5.params import *
+from m5.proxy import *
class MipsISA(SimObject):
type = 'MipsISA'
cxx_class = 'MipsISA::ISA'
cxx_header = "arch/mips/isa.hh"
+ system = Param.System(Parent.any, "System this ISA object belongs to")
+
num_threads = Param.UInt8(1, "Maximum number this ISA can handle")
num_vpes = Param.UInt8(1, "Maximum number of vpes this ISA can handle")
