commit 7fe9f92cfc73147a1a024c1632c9a7619c1779d1
author Timothy M. Jones <tjones1@inf.ed.ac.uk> Fri Feb 12 19:53:19 2010 +0000
committer Timothy M. Jones <tjones1@inf.ed.ac.uk> Fri Feb 12 19:53:19 2010 +0000
tree b24813482ae150b76c8ba095774f525ee0413e3c
parent dd60902152321a698682e4f53e29e4043ff321e5

BaseDynInst: Make the TLB translation timing instead of atomic.

This initiates a timing translation and passes the read or write on to the
processor before waiting for it to finish. Once the translation is finished,
the instruction's state is updated via the 'finish' function. A new
DataTranslation class is created to handle this.

The idea is taken from the implementation of timing translations in
TimingSimpleCPU by Gabe Black. This patch also separates out the timing
translations from this CPU and uses the new DataTranslation class.