commit ce00e6042d996a9255960917f99009d9826b3885
author Alec Roelke <ar4jc@virginia.edu> Sun Dec 10 14:15:51 2017 -0500
committer Alec Roelke <ar4jc@virginia.edu> Sat May 12 19:13:05 2018 +0000
tree 3edaebe9648e7083a6e8e68c008147b476cefd5b
parent e89e83529ad17bc1ae7ae23d337fd4067db01708

arch-riscv: Update CSR implementations

This patch updates the CSRs to match the RISC-V privileged specification
version 1.10. As interrupts, faults, and privilege levels are not yet
supported, there are no meaninful side effects that are implemented.
Performance counters are also not yet implemented, as they do not have
specifications. Currently they act as cycle counters.

Note that this implementation trusts software to use the registers
properly. Access protection, readability, and writeability of registers
based on privilege will come in a future patch.

Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a
Reviewed-on: https://gem5-review.googlesource.com/7441
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>