commit f6dd997ef43f52f80f5cdb43cd32614ce4169960
author Andreas Sandberg <andreas.sandberg@arm.com> Wed Jun 27 09:35:11 2018 +0100
committer Andreas Sandberg <andreas.sandberg@arm.com> Thu Jun 28 12:48:54 2018 +0000
tree 1eb4b637b996a72883956fc91fe99a9fd372ccd7
parent a77222f8d0b09497c8ce6a085c81f3960da9d5f4

arch-arm: Fix incorrect t{0,1}sz field in TTBCR

The t0sz and t1sz fields in TTBCR only are only three bits wide unlike
aarch64 which has a 6-bit wide field. The higher bits of the
aarch64-equivalent should be treated as RES0.

Change-Id: I60df73105c34500c0348a44a491c117e9b28f18f
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11589
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>