1. f54020e misc: Using smart pointers for memory Requests by Giacomo Travaglini · 7 years ago
  2. fb0f988 cpu, o3: consider split requests for LSQ checksnoop operations by Hongil Yoon · 9 years ago
  3. 341dbf2 arch: Use const StaticInstPtr references where possible by Andreas Hansson · 10 years ago
  4. 90b1775 cpu: Add support for instructions that zero cache lines. by Ali Saidi · 11 years ago
  5. 6decd70 cpu: add consistent guarding to *_impl.hh files. by Matt Horsnell · 11 years ago
  6. 6df196b O3: Clean up the O3 structures and try to pack them a bit better. by Ali Saidi · 13 years ago
  7. 043709f CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable by Geoffrey Blake · 13 years ago
  8. fd2d5ae DynInst: get rid of dead MyHash code. by Steve Reinhardt · 13 years ago
  9. af6aaf2 CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5 by Geoffrey Blake · 13 years ago
  10. 649c239 LSQ: Only trigger a memory violation with a load/load if the value changes. by Ali Saidi · 13 years ago
  11. ec204f0 O3: Add a pointer to the macroop for a microop in the dyninst. by Gabe Black · 13 years ago
  12. 6230668 O3: Get rid of the raw ExtMachInst constructor on DynInsts. by Gabe Black · 13 years ago
  13. eddac53 trace: reimplement the DTRACE function so it doesn't use a vector by Nathan Binkert · 14 years ago
  14. 39a0556 includes: sort all includes by Nathan Binkert · 14 years ago
  15. e250740 O3: Enhance data address translation by supporting hardware page table walkers. by Giacomo Gabrielli · 14 years ago
  16. cdacbe7 ARM/Alpha/Cpu: Change prefetchs to be more like normal loads. by Ali Saidi · 14 years ago
  17. 6f4bd2c ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. by Gabe Black · 14 years ago
  18. 92ae620 ARM: mark msr/mrs instructions as SerializeBefore/After by Min Kyu Jeong · 14 years ago
  19. 5f91ec3 ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate. by Min Kyu Jeong · 14 years ago
  20. d9f39c8 arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh by Nathan Binkert · 15 years ago
  21. 1adfe5c O3CPU: Make the instcount debugging stuff per-cpu. by Clint Smullen · 16 years ago
  22. 21fd15a O3CPU: Don't call dumpInsts if DEBUG is not defined by Vilas Sridharan · 17 years ago
  23. df7730b Fix compiler errors. by Gabe Black · 18 years ago
  24. c3081d9 Add support for microcode and pull out the special branch delay slot handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect. by Gabe Black · 18 years ago
  25. 31e78b0 Two fixes: by Kevin Lim · 18 years ago
  26. a6eb16a Accidently "cleaned" away the NPC parameter to the constructor. by Gabe Black · 18 years ago
  27. 4d66ddb Added a predicted NPC field, explicitly stored whether the instruction was predicted taken or not. by Gabe Black · 18 years ago
  28. 1926faa Add in support for LL/SC in the O3 CPU. Needs to be fully tested. by Kevin Lim · 18 years ago
  29. 5df93cc Replace tests of LOCKED/UNCACHEABLE flags with isLocked()/isUncacheable(). by Steve Reinhardt · 18 years ago
  30. 74546aa Cleaned up include files and got rid of many using directives in header files. by Gabe Black · 18 years ago
  31. 19ca97a This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds, runs, and gets very very close to completing the hello world by Korey Sewell · 19 years ago
  32. f3d7475 Split off instantiation into separate CC files for each of the models. This makes it easier to be able to specify only certain CPU models. by Kevin Lim · 19 years ago[Renamed (92%) from src/cpu/base_dyn_inst.cc]
  33. baba18a Two updates that got combined into one ChangeSet accidentally. They're both pretty simple so they shouldn't cause any trouble. by Kevin Lim · 19 years ago
  34. 5d11e8b Minor code cleanup of BaseDynInst. by Kevin Lim · 19 years ago
  35. 4acb283 Clean up/shift some code around. by Kevin Lim · 19 years ago
  36. c14c78f Removing of old code and adding in new comments. by Kevin Lim · 19 years ago
  37. 090496b Fixes to get new CPU model working for simple test case. The CPU does not yet support retrying accesses. by Kevin Lim · 19 years ago
  38. 984c2a4 Merge ktlim@zamp:/z/ktlim2/clean/m5-o3 by Kevin Lim · 19 years ago
  39. d2d581c Merge ktlim@zizzer:/bk/newmem by Kevin Lim · 19 years ago
  40. 7940c10 Fixes to get compiling to work. This is mainly fixing up some includes; changing functions within the XCs; changing MemReqPtrs to Requests or Packets where appropriate. by Kevin Lim · 19 years ago
  41. cb0cf2d Updated Authors from bk prs info by Ali Saidi · 19 years ago
  42. 4a5b51b Merge ktlim@zizzer:/bk/m5 into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem by Kevin Lim · 19 years ago
  43. ba2eae5 New directory structure: by Steve Reinhardt · 19 years ago[Renamed from cpu/base_dyn_inst.cc]
  44. 20eced3 Merge ktlim@zizzer:/bk/m5 into zamp.eecs.umich.edu:/z/ktlim2/m5-proxyxc by Kevin Lim · 19 years ago
  45. f15e492 Steps towards setting up the infrastructure to allow the new CPU model to work in full system mode. by Kevin Lim · 19 years ago
  46. c5dcd15 Changed targetarch to just arch. by Gabe Black · 19 years ago
  47. 444f520 MachineCheckFaults and AlignmentFaults are now generated by the ISA, rather than being created directly. by Gabe Black · 19 years ago
  48. 4b25657 Where architecture independent sources included arch/alpha/xxx.hh, they were changed to include targetarch/xxx.hh by Gabe Black · 19 years ago
  49. 08637ef Changed Fault from a FaultBase * to a RefCountingPtr, added "new"s where appropriate, and took away the constant examples of each fault which where for comparing to a fault to determine its type. by Gabe Black · 19 years ago
  50. 8d80fd1 Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed. by Gabe Black · 19 years ago
  51. 463aa6d Changes to untemplate StaticInst and StaticInstPtr, change the isa to a namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths. by Gabe Black · 19 years ago
  52. 10c79ef Changed the fault enum into a class, and fixed everything up to work with it. Next, the faults need to be pulled out of all the other code so that they are only used to communicate between the CPU and the ISA. by Gabe Black · 19 years ago
  53. c479318 Build options are set via a build_options file in the by Steve Reinhardt · 19 years ago
  54. ad8b963 Many files: Update copyright dates and author list by Steve Reinhardt · 20 years ago
  55. 13c005a shuffle files around for new directory structure by Nathan Binkert · 20 years ago
  56. 2a85931 Added copyright. by Kevin Lim · 20 years ago
  57. c2fcac7 Fix up code for initial release. The main bug that remains is properly forwarding data from stores to loads, specifically when they are of differing sizes. by Kevin Lim · 20 years ago
  58. 61d95de Large update of several parts of my code. The most notable change is the inclusion of a full-fledged load/store queue. At the moment it still has some issues running, but most of the code is hopefully close to the final version. by Kevin Lim · 20 years ago
  59. 5c4714c Initial light-weight OoO CPU checkin, along with gcc-3.4 fixes. by Kevin Lim · 20 years ago
  60. 2fb632d Check in of various updates to the CPU. Mainly adds in stats, improves by Kevin Lim · 20 years ago
  61. e3fb9af Update to make multiple instruction issue and different latencies work. by Kevin Lim · 20 years ago
  62. 0474569 Check in of new CPU. This checkin works under non-Fullsystem mode, with no caches. by Kevin Lim · 20 years ago