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gem5 / amd / gem5 / 39a055645f77e0fa7bf49406635dba6bd65e361f / src / mem / physical.cc
  1. 39a0556 includes: sort all includes by Nathan Binkert · 14 years ago
  2. 579c5f0 Spelling: Fix the a spelling error by changing mmaped to mmapped. by Gabe Black · 14 years ago
  3. 0575988 Mem: Print out memory when access > 8 bytes by Ali Saidi · 14 years ago
  4. f05f35d Includes: Don't include isa_traits.hh and use the TheISA namespace unless really needed. by Ali Saidi · 14 years ago
  5. 34a8e37 SE: Fix simulating more than 4GB of RAM in SE mode by Ali Saidi · 14 years ago
  6. a1e8225 ARM: Add checkpointing support by Ali Saidi · 14 years ago
  7. c779af4 Mem: Finish half-baked support for mmaping file in physmem. by Ali Saidi · 14 years ago
  8. d6da172 util: do checkpoint aggregation more cleanly, fix last changeset. by Lisa Hsu · 15 years ago
  9. 2c5fe6f build: fix compile problems pointed out by gcc 4.4 by Nathan Binkert · 15 years ago
  10. d9f39c8 arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh by Nathan Binkert · 15 years ago
  11. a13a706 Fix setting of INST_FETCH flag for O3 CPU. by Steve Reinhardt · 16 years ago
  12. b398b8f Registers: Add a registers.hh file as an ISA switched header. by Gabe Black · 16 years ago
  13. 6faf377 types: clean up types, especially signed vs unsigned by Nathan Binkert · 16 years ago
  14. 8d2e51c includes: sort includes again by Nathan Binkert · 16 years ago
  15. eef3a2e types: Move stuff for global types into src/base/types.hh by Nathan Binkert · 16 years ago
  16. bd6f2bb Mem: Change isLlsc to isLLSC. by Gabe Black · 16 years ago
  17. 3e5f487 Memory: Rename LOCKED for load locked store conditional to LLSC. by Gabe Black · 16 years ago
  18. d857faf Add in Context IDs to the simulator. From now on, cpuId is almost never used, by Lisa Hsu · 16 years ago
  19. e063210 eventq: convert all usage of events to use the new API. by Nathan Binkert · 16 years ago
  20. fa8f91f physmem: Add a null option to physical memory so it doesn't store data. by Nathan Binkert · 17 years ago
  21. fe12f38 PhysicalMemory: Add parameter for variance in memory delay. by Ali Saidi · 17 years ago
  22. cde5a79 Additional comments and helper functions for PrintReq. by Steve Reinhardt · 17 years ago
  23. 3952e41 Add functional PrintReq command for memory-system debugging. by Steve Reinhardt · 17 years ago
  24. 8026ecb Memory: Cache the physical memory start and size so we don't need a dynamic cast on every access. by Ali Saidi · 17 years ago
  25. bfdd2f3 remove unnecessary debug messages I added by Korey Sewell · 17 years ago
  26. 2692590 Add in files from merge-bare-iron, get them compiling in FS and SE mode by Korey Sewell · 17 years ago
  27. 2f93db6 memory system: fix functional access bug. by Steve Reinhardt · 18 years ago
  28. f0fef8f Merge python and x86 changes with cache branch by Nathan Binkert · 18 years ago
  29. abc76f2 Major changes to how SimObjects are created and initialized. Almost all by Nathan Binkert · 18 years ago
  30. 6ab5341 Get rid of Packet result field. Error responses are now encoded in cmd field. by Steve Reinhardt · 18 years ago
  31. 35cf19d More major reorg of cache. Seems to work for atomic mode now, by Steve Reinhardt · 18 years ago
  32. 41f6cbc Restructure SimpleTimingPort a bit: by Steve Reinhardt · 18 years ago
  33. 4124179 Change getDeviceAddressRanges to use bool for snoop arg. by Steve Reinhardt · 18 years ago
  34. 87adc37 Insist that PhysicalMemory object have at least one connection. by Steve Reinhardt · 18 years ago
  35. aa5b595 Oops... some places in C++ explicitly ask for a "functional" by Steve Reinhardt · 18 years ago
  36. 0305159 PhysicalMemory has vector of uniform ports instead of one special one. by Steve Reinhardt · 18 years ago
  37. f72a999 some forgotten commits by Ali Saidi · 18 years ago
  38. b5a4d95 rename store conditional stuff as extra data so it can be used for conditional swaps as well by Ali Saidi · 18 years ago
  39. 63fdabf make our code a little more standards compliant by Ali Saidi · 18 years ago
  40. b6dc902 Change MemoryAccess dprintfs to print the data as well by Ali Saidi · 18 years ago
  41. f85082e Added a parameter to set memory to zero. This is to support Legion, and once we can make our own hypervisor binary, we probably won't need it. by Gabe Black · 18 years ago
  42. 04e6a3a Fix an assert to correctly make sure a request falls entirely inside a memory. by Gabe Black · 18 years ago
  43. 5edfaef Physical memory overrides the tport version of recvFunctional, need to do the by Ron Dreslinski · 18 years ago
  44. cb172d0 Get SPARC to the point that it starts running. Add ability to load the ROM bin files, cleanup lockstep printing a bit by Ali Saidi · 18 years ago
  45. a4c6f0d Use PacketPtr everywhere by Nathan Binkert · 18 years ago
  46. 7245d45 refactor code for the packet, get rid of packet_impl.hh by Nathan Binkert · 18 years ago
  47. ba4c224 Fix problems with unCacheable addresses in timing-coherence by Ron Dreslinski · 18 years ago
  48. bdde892 Merge ktlim@zizzer:/bk/newmem by Kevin Lim · 18 years ago
  49. b9fb4d4 Make memtest work with 8 memtesters by Ron Dreslinski · 18 years ago
  50. 4167c3c Update memory assertion to check for whole range. by Kevin Lim · 18 years ago
  51. e65f0ce Only respond if the pkt needs a response. by Ron Dreslinski · 18 years ago
  52. d3fba5a Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing) by Steve Reinhardt · 18 years ago
  53. f9ae0dc Move more common functionality into SimpleTimingPort, by Steve Reinhardt · 19 years ago
  54. c7bb14a DRAM Memory doesn't crash the simulator now.. still untested. by Ali Saidi · 19 years ago
  55. 2f145ac Fix Physical Memory to allow memory sizes bigger than 128MB. by Ali Saidi · 19 years ago
  56. 851f91f Move PioPort timing code into Simple Timing Port object by Ali Saidi · 19 years ago
  57. e981a97 Move SimObject creation and Port connection loops by Steve Reinhardt · 19 years ago
  58. cb0cf2d Updated Authors from bk prs info by Ali Saidi · 19 years ago
  59. 91e3aa6 Minor further cleanup & commenting of Packet class. by Steve Reinhardt · 19 years ago
  60. e533fad Significant rework of Packet class interface: by Steve Reinhardt · 19 years ago
  61. da6a7b1 Add names to memory Port objects for tracing. by Steve Reinhardt · 19 years ago
  62. cf826ae Minor fixes for full-system timing memory. by Steve Reinhardt · 19 years ago
  63. ba2eae5 New directory structure: by Steve Reinhardt · 19 years ago[Renamed from mem/physical.cc]
  64. 86777c9 First steps toward getting full system to work with by Steve Reinhardt · 19 years ago
  65. 796fa42 Change Packet parameters on Port methods from references to pointers. by Steve Reinhardt · 19 years ago
  66. 309e1d8 Split SimpleCPU into two different models, AtomicSimpleCPU and by Steve Reinhardt · 19 years ago
  67. 2db12b3 Many files: Get rid of more unneeded includes. by Steve Reinhardt · 19 years ago
  68. 8a9d270 move code from packet.hh to packet.cc and packet_impl.hh by Ali Saidi · 19 years ago
  69. 53d93ef add a bridge object, modify bus object to be able to connect to other buses or bridges without panicing by Ali Saidi · 19 years ago
  70. 8f8d095 Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working by Ali Saidi · 19 years ago
  71. 6dc3b2f make ide disk work for newmem by Ali Saidi · 19 years ago
  72. 93b2711 Panic if physical memory isn't connected to anything by Ali Saidi · 19 years ago
  73. 2609ed2 a bit of bad code trampling on memory by Ali Saidi · 19 years ago
  74. 6240f8c fixes for newmem ALPHA_FS finally compiles again by Ali Saidi · 19 years ago
  75. e196d20 Make TranslatingPort be a type of Port rather than something special by Ali Saidi · 19 years ago
  76. c27c122 Add the bus and connector objects to scons by Ali Saidi · 19 years ago
  77. b38f67d Implement a very very simple bus requestTime -> time responseTime -> packet.time by Ali Saidi · 19 years ago
  78. e2b329d Replace Memory with MemObject; no need for two different levels of hierarchy there. by Steve Reinhardt · 19 years ago
  79. e1985e0 More memory system cleanup: by Steve Reinhardt · 19 years ago
  80. f102365 SimpleCPU compiles with merge. by Gabe Black · 19 years ago
  81. e7f442d Simple program runs with sendAtomic! by Steve Reinhardt · 19 years ago
  82. 22504f8 More progress toward actually running a program. by Steve Reinhardt · 19 years ago
  83. b6247c9 Add support for multiple ports on the memory. Hook up simple cpu to memory. by Ron Dreslinski · 19 years ago
  84. 8fc0658 Update functional memory to have a response event by Ron Dreslinski · 19 years ago
  85. ceac38e Remove unneeded functions, moving code around abit. by Ron Dreslinski · 19 years ago
  86. b403abf Move the port from base memory object into the physical memory object. by Ron Dreslinski · 19 years ago
  87. 1fff9f5 Some more changes for compilation. Since memset is now part of port and not virtual, no need for memory to define them. by Ron Dreslinski · 19 years ago
  88. 4bd11c1 Add blocksize functions to physical memory. Fix the port we were using in the process loader. by Ron Dreslinski · 19 years ago
  89. 7f114ca Many changes that make the new mem system compile. Now to convert the rest of the tree to use the new mem system. by Ron Dreslinski · 19 years ago
  90. 4e36678 Adding some more things toward having cpu->mem test in place. Still need to work on compilation issues. by Ron Dreslinski · 19 years ago