commit 1e05c299820e1e795ba1bb090ec823db90833ec7
author Giacomo Travaglini <giacomo.travaglini@arm.com> Fri Dec 15 10:03:19 2017 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Tue Dec 19 16:43:45 2017 +0000
tree e5986dc18dc2413a1b42d981960f3f184d48bacd
parent 50749b849647f132868d5022f7523530d6c711a3

arch-arm: Instruction size methods in StaticInst class

This patch is introducing some methods in StaticInst so that is possible
to get the instruction size in byte of the instruction (can be 2 bytes
in Thumb) and the correct opcode (The machInst field contains some
appended metadata)

Change-Id: I3bed4d9fd7c77feaeded40ded192afe445d306ea
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6781
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

src/arch/arm/insts/static_inst.hh

diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh
index 431e81b..4595646 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -423,6 +423,25 @@
     {
         return intWidth;
     }
+
+    /** Returns the byte size of current instruction */
+    ssize_t
+    instSize() const
+    {
+        return (!machInst.thumb || machInst.bigThumb) ? 4 : 2;
+    }
+
+    /**
+     * Returns the real encoding of the instruction:
+     * the machInst field is in fact always 64 bit wide and
+     * contains some instruction metadata, which means it differs
+     * from the real opcode.
+     */
+    MachInst
+    encoding() const
+    {
+        return static_cast<MachInst>(mask(instSize() * 8));
+    }
 };
 }