| # -*- mode:python -*- |
| |
| # Copyright (c) 2004-2005 The Regents of The University of Michigan |
| # All rights reserved. |
| # |
| # Redistribution and use in source and binary forms, with or without |
| # modification, are permitted provided that the following conditions are |
| # met: redistributions of source code must retain the above copyright |
| # notice, this list of conditions and the following disclaimer; |
| # redistributions in binary form must reproduce the above copyright |
| # notice, this list of conditions and the following disclaimer in the |
| # documentation and/or other materials provided with the distribution; |
| # neither the name of the copyright holders nor the names of its |
| # contributors may be used to endorse or promote products derived from |
| # this software without specific prior written permission. |
| # |
| # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| # |
| # Authors: Steve Reinhardt |
| # Nathan Binkert |
| |
| import os |
| Import('*') |
| |
| Source('swig/init.cc') |
| Source('swig/pyevent.cc') |
| Source('swig/pyobject.cc') |
| |
| PySource('m5', 'm5/__init__.py') |
| PySource('m5', 'm5/SimObject.py') |
| PySource('m5', 'm5/attrdict.py') |
| PySource('m5', 'm5/convert.py') |
| PySource('m5', 'm5/event.py') |
| PySource('m5', 'm5/main.py') |
| PySource('m5', 'm5/multidict.py') |
| PySource('m5', 'm5/params.py') |
| PySource('m5', 'm5/proxy.py') |
| PySource('m5', 'm5/smartdict.py') |
| PySource('m5', 'm5/stats.py') |
| PySource('m5', 'm5/ticks.py') |
| PySource('m5', 'm5/util.py') |
| |
| PySource('m5', os.path.join(env['ROOT'], 'util/pbs/jobfile.py')) |
| |
| SwigSource('m5.internal', 'swig/core.i') |
| SwigSource('m5.internal', 'swig/debug.i') |
| SwigSource('m5.internal', 'swig/event.i') |
| SwigSource('m5.internal', 'swig/random.i') |
| SwigSource('m5.internal', 'swig/sim_object.i') |
| SwigSource('m5.internal', 'swig/stats.i') |
| SwigSource('m5.internal', 'swig/trace.i') |
| PySource('m5.internal', 'm5/internal/__init__.py') |
| |
| SimObject('m5/objects/AlphaConsole.py') |
| SimObject('m5/objects/AlphaTLB.py') |
| SimObject('m5/objects/BadDevice.py') |
| SimObject('m5/objects/BaseCPU.py') |
| SimObject('m5/objects/BaseCache.py') |
| SimObject('m5/objects/BaseHier.py') |
| SimObject('m5/objects/BaseMem.py') |
| SimObject('m5/objects/BaseMemory.py') |
| SimObject('m5/objects/BranchPred.py') |
| SimObject('m5/objects/Bridge.py') |
| SimObject('m5/objects/Bus.py') |
| SimObject('m5/objects/Checker.py') |
| SimObject('m5/objects/CoherenceProtocol.py') |
| SimObject('m5/objects/DRAMMemory.py') |
| SimObject('m5/objects/Device.py') |
| SimObject('m5/objects/DiskImage.py') |
| SimObject('m5/objects/Ethernet.py') |
| SimObject('m5/objects/FUPool.py') |
| SimObject('m5/objects/FastCPU.py') |
| #SimObject('m5/objects/FreebsdSystem.py') |
| SimObject('m5/objects/FuncUnit.py') |
| SimObject('m5/objects/FuncUnitConfig.py') |
| SimObject('m5/objects/FunctionalMemory.py') |
| SimObject('m5/objects/HierParams.py') |
| SimObject('m5/objects/Ide.py') |
| SimObject('m5/objects/IntrControl.py') |
| SimObject('m5/objects/LinuxSystem.py') |
| SimObject('m5/objects/MainMemory.py') |
| SimObject('m5/objects/MemObject.py') |
| SimObject('m5/objects/MemTest.py') |
| SimObject('m5/objects/MemoryController.py') |
| SimObject('m5/objects/O3CPU.py') |
| SimObject('m5/objects/OzoneCPU.py') |
| SimObject('m5/objects/Pci.py') |
| SimObject('m5/objects/PhysicalMemory.py') |
| SimObject('m5/objects/Platform.py') |
| SimObject('m5/objects/Process.py') |
| SimObject('m5/objects/Repl.py') |
| SimObject('m5/objects/Root.py') |
| SimObject('m5/objects/Sampler.py') |
| SimObject('m5/objects/SimConsole.py') |
| SimObject('m5/objects/SimpleCPU.py') |
| SimObject('m5/objects/SimpleDisk.py') |
| #SimObject('m5/objects/SimpleOzoneCPU.py') |
| SimObject('m5/objects/SparcTLB.py') |
| SimObject('m5/objects/System.py') |
| SimObject('m5/objects/T1000.py') |
| #SimObject('m5/objects/Tru64System.py') |
| SimObject('m5/objects/Tsunami.py') |
| SimObject('m5/objects/Uart.py') |