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gem5
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arm
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gem5
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72f15d3b8926432bed4740403d85a76549abb8bb
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.
/
build_opts
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RISCV
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TARGET_ISA
=
'riscv'
CPU_MODELS
=
'AtomicSimpleCPU,TimingSimpleCPU,MinorCPU,O3CPU'
PROTOCOL
=
'MI_example'
