alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT.
This constant is, first, a #define, and second only used in one place.
In that one place, it appears that the code it guards is no longer
necessary in general. It was originally written to avoid refetching a
block of data that you're still in, even if you've moved slightly
farther in it because you're skipping the next instruction due to an
annulled branch delay slot. In reality however, in SPARC, the one ISA
I'm aware of which has this sort of branching behavior, the PC state
object will correctly determine that no branch is happening in these
cases. Code lower down in the loop will then recompute where fetching
should continue based on the next PC, automatically skipping the
annulled branch slot without misinterpretting the gap as a branch.
This change therefore also removes this block of code.
Change-Id: I820ebc9df10aeb4fcb69c12f6a784e9ec616743c
Reviewed-on: https://gem5-review.googlesource.com/6821
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
index 54b8003..61688b5 100644
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -45,9 +45,6 @@
StaticInstPtr decodeInst(ExtMachInst);
-// Alpha Does NOT have a delay slot
-#define ISA_HAS_DELAY_SLOT 0
-
const Addr PageShift = 13;
const Addr PageBytes = ULL(1) << PageShift;
const Addr PageMask = ~(PageBytes - 1);
diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index fa27795..5763e77 100644
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -57,9 +57,6 @@
StaticInstPtr decodeInst(ExtMachInst);
- // ARM DOES NOT have a delay slot
- #define ISA_HAS_DELAY_SLOT 0
-
const Addr PageShift = 12;
const Addr PageBytes = ULL(1) << PageShift;
const Addr Page_Mask = ~(PageBytes - 1);
diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index 7a16071..6e08c7e 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -47,9 +47,6 @@
StaticInstPtr decodeInst(ExtMachInst);
-// MIPS DOES have a delay slot
-#define ISA_HAS_DELAY_SLOT 1
-
const Addr PageShift = 13;
const Addr PageBytes = ULL(1) << PageShift;
const Addr Page_Mask = ~(PageBytes - 1);
diff --git a/src/arch/power/isa_traits.hh b/src/arch/power/isa_traits.hh
index 41a8d7d..9afe680 100644
--- a/src/arch/power/isa_traits.hh
+++ b/src/arch/power/isa_traits.hh
@@ -48,9 +48,6 @@
StaticInstPtr decodeInst(ExtMachInst);
-// POWER DOES NOT have a delay slot
-#define ISA_HAS_DELAY_SLOT 0
-
const Addr PageShift = 12;
const Addr PageBytes = ULL(1) << PageShift;
const Addr Page_Mask = ~(PageBytes - 1);
diff --git a/src/arch/riscv/isa_traits.hh b/src/arch/riscv/isa_traits.hh
index 21e684a..abafad2 100644
--- a/src/arch/riscv/isa_traits.hh
+++ b/src/arch/riscv/isa_traits.hh
@@ -57,9 +57,6 @@
using namespace LittleEndianGuest;
-// Riscv does NOT have a delay slot
-#define ISA_HAS_DELAY_SLOT 0
-
const Addr PageShift = 12;
const Addr PageBytes = ULL(1) << PageShift;
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 4f98f75..58d8437 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -44,9 +44,6 @@
// This makes sure the big endian versions of certain functions are used.
using namespace BigEndianGuest;
-// SPARC has a delay slot
-#define ISA_HAS_DELAY_SLOT 1
-
// real address virtual mapping
// sort of like alpha super page, but less frequently used
const Addr SegKPMEnd = ULL(0xfffffffc00000000);
diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index 2b19b1b..158e2f9 100644
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -53,9 +53,6 @@
//are used.
using namespace LittleEndianGuest;
- // X86 does not have a delay slot
-#define ISA_HAS_DELAY_SLOT 0
-
const Addr PageShift = 12;
const Addr PageBytes = ULL(1) << PageShift;
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index d879342..2e8ec67 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1277,17 +1277,6 @@
break;
}
- if (ISA_HAS_DELAY_SLOT && pcOffset == 0) {
- // Walk past any annulled delay slot instructions.
- Addr pcAddr = thisPC.instAddr() & BaseCPU::PCMask;
- while (fetchAddr != pcAddr && blkOffset < numInsts) {
- blkOffset++;
- fetchAddr += instSize;
- }
- if (blkOffset >= numInsts)
- break;
- }
-
MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]);
decoder[tid]->moreBytes(thisPC, fetchAddr, inst);
