| /* |
| * Copyright (c) 2006 The Regents of The University of Michigan |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions are |
| * met: redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer; |
| * redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution; |
| * neither the name of the copyright holders nor the names of its |
| * contributors may be used to endorse or promote products derived from |
| * this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| * |
| * Authors: Kevin Lim |
| */ |
| |
| #ifndef __CPU_OZONE_NULL_PREDICTOR_HH__ |
| #define __CPU_OZONE_NULL_PREDICTOR_HH__ |
| |
| #include "base/types.hh" |
| #include "cpu/inst_seq.hh" |
| |
| template <class Impl> |
| class NullPredictor |
| { |
| public: |
| typedef typename Impl::Params Params; |
| typedef typename Impl::DynInstPtr DynInstPtr; |
| |
| NullPredictor(Params *p) { } |
| |
| struct BPredInfo { |
| BPredInfo() |
| : PC(0), nextPC(0) |
| { } |
| |
| BPredInfo(const Addr &pc, const Addr &next_pc) |
| : PC(pc), nextPC(next_pc) |
| { } |
| |
| Addr PC; |
| Addr nextPC; |
| }; |
| |
| BPredInfo lookup(Addr &PC) { return BPredInfo(PC, PC+4); } |
| |
| void undo(BPredInfo &bp_info) { return; } |
| |
| /** |
| * Predicts whether or not the instruction is a taken branch, and the |
| * target of the branch if it is taken. |
| * @param inst The branch instruction. |
| * @param PC The predicted PC is passed back through this parameter. |
| * @param tid The thread id. |
| * @return Returns if the branch is taken or not. |
| */ |
| bool predict(DynInstPtr &inst, Addr &PC, ThreadID tid) |
| { return false; } |
| |
| /** |
| * Tells the branch predictor to commit any updates until the given |
| * sequence number. |
| * @param done_sn The sequence number to commit any older updates up until. |
| * @param tid The thread id. |
| */ |
| void update(const InstSeqNum &done_sn, ThreadID tid) { } |
| |
| /** |
| * Squashes all outstanding updates until a given sequence number. |
| * @param squashed_sn The sequence number to squash any younger updates up |
| * until. |
| * @param tid The thread id. |
| */ |
| void squash(const InstSeqNum &squashed_sn, ThreadID tid) { } |
| |
| /** |
| * Squashes all outstanding updates until a given sequence number, and |
| * corrects that sn's update with the proper address and taken/not taken. |
| * @param squashed_sn The sequence number to squash any younger updates up |
| * until. |
| * @param corr_target The correct branch target. |
| * @param actually_taken The correct branch direction. |
| * @param tid The thread id. |
| */ |
| void squash(const InstSeqNum &squashed_sn, const Addr &corr_target, |
| bool actually_taken, ThreadID tid) |
| { } |
| |
| }; |
| |
| #endif // __CPU_OZONE_NULL_PREDICTOR_HH__ |