| /* |
| * Copyright (c) 2010-2012 ARM Limited |
| * All rights reserved |
| * |
| * The license below extends only to copyright in the software and shall |
| * not be construed as granting a license to any other intellectual |
| * property including but not limited to intellectual property relating |
| * to a hardware implementation of the functionality of the software |
| * licensed hereunder. You may use the software subject to the license |
| * terms below provided that you ensure that this notice is replicated |
| * unmodified and in its entirety in all distributions of the software, |
| * modified or unmodified, in source code or in binary form. |
| * |
| * Copyright (c) 2001-2005 The Regents of The University of Michigan |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions are |
| * met: redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer; |
| * redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution; |
| * neither the name of the copyright holders nor the names of its |
| * contributors may be used to endorse or promote products derived from |
| * this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| * |
| * Authors: Ron Dreslinski |
| * Ali Saidi |
| * Andreas Hansson |
| */ |
| |
| #include "base/random.hh" |
| #include "mem/simple_mem.hh" |
| |
| using namespace std; |
| |
| SimpleMemory::SimpleMemory(const SimpleMemoryParams* p) : |
| AbstractMemory(p), |
| port(name() + ".port", *this), lat(p->latency), |
| lat_var(p->latency_var), bandwidth(p->bandwidth), |
| isBusy(false), retryReq(false), releaseEvent(this) |
| { |
| } |
| |
| void |
| SimpleMemory::init() |
| { |
| // allow unconnected memories as this is used in several ruby |
| // systems at the moment |
| if (port.isConnected()) { |
| port.sendRangeChange(); |
| } |
| } |
| |
| Tick |
| SimpleMemory::calculateLatency(PacketPtr pkt) |
| { |
| if (pkt->memInhibitAsserted()) { |
| return 0; |
| } else { |
| Tick latency = lat; |
| if (lat_var != 0) |
| latency += random_mt.random<Tick>(0, lat_var); |
| return latency; |
| } |
| } |
| |
| Tick |
| SimpleMemory::doAtomicAccess(PacketPtr pkt) |
| { |
| access(pkt); |
| return calculateLatency(pkt); |
| } |
| |
| void |
| SimpleMemory::doFunctionalAccess(PacketPtr pkt) |
| { |
| functionalAccess(pkt); |
| } |
| |
| bool |
| SimpleMemory::recvTimingReq(PacketPtr pkt) |
| { |
| /// @todo temporary hack to deal with memory corruption issues until |
| /// 4-phase transactions are complete |
| for (int x = 0; x < pendingDelete.size(); x++) |
| delete pendingDelete[x]; |
| pendingDelete.clear(); |
| |
| if (pkt->memInhibitAsserted()) { |
| // snooper will supply based on copy of packet |
| // still target's responsibility to delete packet |
| pendingDelete.push_back(pkt); |
| return true; |
| } |
| |
| // we should never get a new request after committing to retry the |
| // current one, the bus violates the rule as it simply sends a |
| // retry to the next one waiting on the retry list, so simply |
| // ignore it |
| if (retryReq) |
| return false; |
| |
| // if we are busy with a read or write, remember that we have to |
| // retry |
| if (isBusy) { |
| retryReq = true; |
| return false; |
| } |
| |
| // @todo someone should pay for this |
| pkt->busFirstWordDelay = pkt->busLastWordDelay = 0; |
| |
| // update the release time according to the bandwidth limit, and |
| // do so with respect to the time it takes to finish this request |
| // rather than long term as it is the short term data rate that is |
| // limited for any real memory |
| |
| // only look at reads and writes when determining if we are busy, |
| // and for how long, as it is not clear what to regulate for the |
| // other types of commands |
| if (pkt->isRead() || pkt->isWrite()) { |
| // calculate an appropriate tick to release to not exceed |
| // the bandwidth limit |
| Tick duration = pkt->getSize() * bandwidth; |
| |
| // only consider ourselves busy if there is any need to wait |
| // to avoid extra events being scheduled for (infinitely) fast |
| // memories |
| if (duration != 0) { |
| schedule(releaseEvent, curTick() + duration); |
| isBusy = true; |
| } |
| } |
| |
| // go ahead and deal with the packet and put the response in the |
| // queue if there is one |
| bool needsResponse = pkt->needsResponse(); |
| Tick latency = doAtomicAccess(pkt); |
| // turn packet around to go back to requester if response expected |
| if (needsResponse) { |
| // doAtomicAccess() should already have turned packet into |
| // atomic response |
| assert(pkt->isResponse()); |
| port.schedTimingResp(pkt, curTick() + latency); |
| } else { |
| pendingDelete.push_back(pkt); |
| } |
| |
| return true; |
| } |
| |
| void |
| SimpleMemory::release() |
| { |
| assert(isBusy); |
| isBusy = false; |
| if (retryReq) { |
| retryReq = false; |
| port.sendRetry(); |
| } |
| } |
| |
| BaseSlavePort & |
| SimpleMemory::getSlavePort(const std::string &if_name, PortID idx) |
| { |
| if (if_name != "port") { |
| return MemObject::getSlavePort(if_name, idx); |
| } else { |
| return port; |
| } |
| } |
| |
| unsigned int |
| SimpleMemory::drain(DrainManager *dm) |
| { |
| int count = port.drain(dm); |
| |
| if (count) |
| setDrainState(Drainable::Draining); |
| else |
| setDrainState(Drainable::Drained); |
| return count; |
| } |
| |
| SimpleMemory::MemoryPort::MemoryPort(const std::string& _name, |
| SimpleMemory& _memory) |
| : QueuedSlavePort(_name, &_memory, queueImpl), |
| queueImpl(_memory, *this), memory(_memory) |
| { } |
| |
| AddrRangeList |
| SimpleMemory::MemoryPort::getAddrRanges() const |
| { |
| AddrRangeList ranges; |
| ranges.push_back(memory.getAddrRange()); |
| return ranges; |
| } |
| |
| Tick |
| SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt) |
| { |
| return memory.doAtomicAccess(pkt); |
| } |
| |
| void |
| SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt) |
| { |
| pkt->pushLabel(memory.name()); |
| |
| if (!queue.checkFunctional(pkt)) { |
| // Default implementation of SimpleTimingPort::recvFunctional() |
| // calls recvAtomic() and throws away the latency; we can save a |
| // little here by just not calculating the latency. |
| memory.doFunctionalAccess(pkt); |
| } |
| |
| pkt->popLabel(); |
| } |
| |
| bool |
| SimpleMemory::MemoryPort::recvTimingReq(PacketPtr pkt) |
| { |
| return memory.recvTimingReq(pkt); |
| } |
| |
| SimpleMemory* |
| SimpleMemoryParams::create() |
| { |
| return new SimpleMemory(this); |
| } |