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gem5 / arm / gem5 / 9f5b6e1b74c8289050836abdfb9c2539380f9105 / . / src / mem / protocol / MOESI_AMD_Base.slicc
blob: b38145246173b51e1a53141fb215432f30edcf95 [file] [log] [blame]
protocol "MOESI_AMD_Base";
include "RubySlicc_interfaces.slicc";
include "MOESI_AMD_Base-msg.sm";
include "MOESI_AMD_Base-CorePair.sm";
include "MOESI_AMD_Base-L3cache.sm";
include "MOESI_AMD_Base-dir.sm";