commit a5ce9ead23e2da2ee9e86ab2d02828975769e44d
author Javier Setoain <javier.setoain@arm.com> Mon Feb 18 17:43:56 2019 +0000
committer Giacomo Gabrielli <giacomo.gabrielli@arm.com> Thu Feb 21 15:16:22 2019 +0000
tree 5f44f12bd1a4bc5dfc398300a254496ca1447b31
parent 98ccd8cff5d1a8a672dc82a5b5f83ddf3153f6a6

arch-arm: Added SVE LAST[AB] (SIMD&FP scalar) instructions.

Change-Id: I103288209f11a18018dd1a98b64fb5ae6ed7e892
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>

src/arch/arm/isa/formats/sve_2nd_level.isa

diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa b/src/arch/arm/isa/formats/sve_2nd_level.isa
index 7d48b0f..4f6c209 100644
--- a/src/arch/arm/isa/formats/sve_2nd_level.isa
+++ b/src/arch/arm/isa/formats/sve_2nd_level.isa
@@ -1218,7 +1218,18 @@
             break;
           case 0x1:
             if (!b13) {
-                // sve_int_perm_last_v
+                uint8_t AB = bits(machInst, 16);
+                uint8_t size = bits(machInst, 23, 22);
+                IntRegIndex pg = (IntRegIndex)(uint8_t) bits(machInst, 12, 10);
+                IntRegIndex zn = (IntRegIndex)(uint8_t) bits(machInst, 9, 5);
+                IntRegIndex vd = (IntRegIndex)(uint8_t) bits(machInst, 4, 0);
+                if (!AB) {
+                    return decodeSveUnaryPredU<SveLastaf>(size,
+                            machInst, vd, zn, pg);
+                } else {
+                    return decodeSveUnaryPredU<SveLastbf>(size,
+                            machInst, vd, zn, pg);
+                }
             }
             break;
           case 0x4:

src/arch/arm/isa/insts/sve.isa

diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index 7d5075f..cced13f 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -3867,7 +3867,9 @@
         destElem = AA64FpOp1_x[last];'''
     sveSelectInst('lasta', 'Lasta', 'SimdAluOp', unsignedTypes, lastaCode,
             isCond = False)
-    # TODO: LASTA (SIMD&FP scalar)
+    # LASTA (SIMD&FP scalar)
+    sveSelectInst('lasta', 'Lastaf', 'SimdAluOp', unsignedTypes, lastaCode,
+            isCond = False, destType = DstRegType.SimdFpScalar)
     # LASTB (scalar)
     lastbCode = '''
         if (last < 0) {
@@ -3876,7 +3878,9 @@
         destElem = AA64FpOp1_x[last];'''
     sveSelectInst('lastb', 'Lastb', 'SimdAluOp', unsignedTypes, lastbCode,
             isCond = False)
-    # TODO: LASTB (SIMD&FP scalar)
+    # LASTB (SIMD&FP scalar)
+    sveSelectInst('lastb', 'Lastbf', 'SimdAluOp', unsignedTypes, lastbCode,
+            isCond = False, destType = DstRegType.SimdFpScalar)
     # LSL (immediate, predicated)
     lslCode = '''
             if (srcElem2 == 0) {