| /* |
| * Copyright (c) 2007 The Hewlett-Packard Development Company |
| * All rights reserved. |
| * |
| * Redistribution and use of this software in source and binary forms, |
| * with or without modification, are permitted provided that the |
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| * |
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| * commercial advantage. |
| * |
| * If you wish to use this software or functionality therein that may be |
| * covered by patents for commercial use, please contact: |
| * Director of Intellectual Property Licensing |
| * Office of Strategy and Technology |
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| * notice to acknowledge the contribution from this software where |
| * applicable, this list of conditions and the disclaimer below. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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| * |
| * Authors: Gabe Black |
| */ |
| |
| #ifndef __ARCH_X86_ISATRAITS_HH__ |
| #define __ARCH_X86_ISATRAITS_HH__ |
| |
| #include "arch/x86/intregs.hh" |
| #include "arch/x86/max_inst_regs.hh" |
| #include "arch/x86/types.hh" |
| #include "arch/x86/x86_traits.hh" |
| #include "sim/host.hh" |
| |
| class StaticInstPtr; |
| |
| namespace LittleEndianGuest {} |
| |
| namespace X86ISA |
| { |
| //This makes sure the little endian version of certain functions |
| //are used. |
| using namespace LittleEndianGuest; |
| using X86ISAInst::MaxInstSrcRegs; |
| using X86ISAInst::MaxInstDestRegs; |
| |
| // X86 does not have a delay slot |
| #define ISA_HAS_DELAY_SLOT 0 |
| |
| // X86 NOP (XCHG rAX, rAX) |
| //XXX This needs to be set to an intermediate instruction struct |
| //which encodes this instruction |
| |
| // These enumerate all the registers for dependence tracking. |
| enum DependenceTags { |
| //There are 16 microcode registers at the moment. This is an |
| //unusually large constant to make sure there isn't overflow. |
| FP_Base_DepTag = 128, |
| Ctrl_Base_DepTag = |
| FP_Base_DepTag + |
| //mmx/x87 registers |
| 8 + |
| //xmm registers |
| 16 * 2 + |
| //The microcode fp registers |
| 8 + |
| //The indices that are mapped over the fp stack |
| 8 |
| }; |
| |
| // semantically meaningful register indices |
| //There is no such register in X86 |
| const int ZeroReg = NUM_INTREGS; |
| const int StackPointerReg = INTREG_RSP; |
| //X86 doesn't seem to have a link register |
| const int ReturnAddressReg = 0; |
| const int ReturnValueReg = INTREG_RAX; |
| const int FramePointerReg = INTREG_RBP; |
| const int ArgumentReg[] = { |
| INTREG_RDI, |
| INTREG_RSI, |
| INTREG_RDX, |
| //This argument register is r10 for syscalls and rcx for C. |
| INTREG_R10W, |
| //INTREG_RCX, |
| INTREG_R8W, |
| INTREG_R9W |
| }; |
| const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int); |
| |
| // Some OS syscalls use a second register (rdx) to return a second |
| // value |
| const int SyscallPseudoReturnReg = INTREG_RDX; |
| |
| //4k. This value is not constant on x86. |
| const int LogVMPageSize = 12; |
| const int VMPageSize = (1 << LogVMPageSize); |
| |
| const int PageShift = 12; |
| const int PageBytes = 1ULL << PageShift; |
| |
| const int BranchPredAddrShiftAmt = 0; |
| |
| StaticInstPtr decodeInst(ExtMachInst); |
| |
| const Addr LoadAddrMask = ULL(-1); |
| }; |
| |
| #endif // __ARCH_X86_ISATRAITS_HH__ |