commit b277ad3bdb25e2fe7d53d470a57bf48edb6299df
author Jose Marinho <jose.marinho@arm.com> Fri Jul 28 15:28:02 2017 +0100
committer Andreas Sandberg <andreas.sandberg@arm.com> Wed Aug 30 16:26:19 2017 +0000
tree 0f21f0f8e0c15f3d788c5c046aa772afa2e91312
parent 653d2ee29a09be2f9cb3b8145ca1aecb363fbd8e

arch-arm: Only increment SW PMU counters on writes to PMSWINC

When writing a bitmask of counters to PMSWINC, the PMU currently
increments the corresponding counters regardless of what they are
configured to count. According to the ARM ARM (D5.10.4), counters
should only be updated if they have been configured to count
software events (event type 0).

Change-Id: I5b2bc1fae55faa342b863721c9838342442831a9
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4285
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

src/arch/arm/pmu.cc

diff --git a/src/arch/arm/pmu.cc b/src/arch/arm/pmu.cc
index 14b1b50..f1ff6cb 100644
--- a/src/arch/arm/pmu.cc
+++ b/src/arch/arm/pmu.cc
@@ -147,8 +147,10 @@
       case MISCREG_PMSWINC:
         for (int i = 0; i < counters.size(); ++i) {
             CounterState &ctr(getCounter(i));
-            if (ctr.enabled && (val & (1 << i)))
+            if (ctr.enabled && (val & (1 << i))
+                && ctr.eventId == ARCH_EVENT_SW_INCR ) {
                 ++ctr.value;
+            }
         }
         break;