arch-arm: Fixed SVE stores of predicate registers

Fixed the size of the byteEnable vector for the stores of predicate registers

Change-Id: I4e8182b268c6ae3d1d389580894a450358451d77
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>

src/arch/arm/isa/insts/sve_mem.isa

diff --git a/src/arch/arm/isa/insts/sve_mem.isa b/src/arch/arm/isa/insts/sve_mem.isa
index a767a9d..4a332aa 100644
--- a/src/arch/arm/isa/insts/sve_mem.isa
+++ b/src/arch/arm/isa/insts/sve_mem.isa
@@ -244,6 +244,9 @@
                 memDataView[i] = byte;
             }
             '''
+            storeWrEnableCode = '''
+            auto wrEn = std::vector<bool>(eCount / 8, true);
+            '''
         else:
             loadMemAccCode = '''
             for (int i = 0; i < eCount; i++) {
@@ -255,6 +258,9 @@
                 memDataView[i] = AA64FpDest_x[i];
             }
             '''
+            storeWrEnableCode = '''
+            auto wrEn = std::vector<bool>(sizeof(MemElemType) * eCount, true);
+            '''
         loadIop = InstObjParams('ldr',
             'SveLdrPred' if isPred else 'SveLdrVec',
             'SveMemPredFillSpill' if isPred else 'SveMemVecFillSpill',
@@ -269,6 +275,7 @@
             'SveMemPredFillSpill' if isPred else 'SveMemVecFillSpill',
             {'tpl_header': '',
              'tpl_args': '',
+             'wren_code': storeWrEnableCode,
              'memacc_code': storeMemAccCode,
              'ea_code' : sveEnabledCheckCode + eaCode,
              'fa_code' : ''},
@@ -348,6 +355,9 @@
             }
         }
         '''
+        storeWrEnableCode = '''
+        auto wrEn = std::vector<bool>(sizeof(MemElemType) * eCount, true);
+        '''
         loadIop = InstObjParams('ld1',
             'SveContigLoadSI' if offsetIsImm else 'SveContigLoadSS',
             'SveContigMemSI' if offsetIsImm else 'SveContigMemSS',
@@ -362,6 +372,7 @@
             'SveContigMemSI' if offsetIsImm else 'SveContigMemSS',
             {'tpl_header': tplHeader,
              'tpl_args': tplArgs,
+             'wren_code': storeWrEnableCode,
              'memacc_code': storeMemAccCode,
              'ea_code' : sveEnabledCheckCode + eaCode,
              'fa_code' : ''},

src/arch/arm/isa/templates/sve_mem.isa

diff --git a/src/arch/arm/isa/templates/sve_mem.isa b/src/arch/arm/isa/templates/sve_mem.isa
index def26cf..2fbab70 100644
--- a/src/arch/arm/isa/templates/sve_mem.isa
+++ b/src/arch/arm/isa/templates/sve_mem.isa
@@ -239,7 +239,7 @@
         TheISA::VecRegContainer memData;
         auto memDataView = memData.as<MemElemType>();
 
-        auto wrEn = std::vector<bool>(sizeof(MemElemType) * eCount, true);
+        %(wren_code)s;
 
         if (fault == NoFault) {
             %(memacc_code)s;
@@ -276,7 +276,7 @@
         TheISA::VecRegContainer memData;
         auto memDataView = memData.as<MemElemType>();
 
-        auto wrEn = std::vector<bool>(sizeof(MemElemType) * eCount, true);
+        %(wren_code)s;
 
         if (fault == NoFault) {
             %(memacc_code)s;