src/arch/x86/registers.hh

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 * Authors: Gabe Black
 */

#ifndef __ARCH_X86_REGISTERS_HH__
#define __ARCH_X86_REGISTERS_HH__

#include "arch/x86/intregs.hh"
#include "arch/x86/max_inst_regs.hh"
#include "arch/x86/miscregs.hh"
#include "arch/x86/x86_traits.hh"

namespace X86ISA
{
using X86ISAInst::MaxInstSrcRegs;
using X86ISAInst::MaxInstDestRegs;
const int NumMiscArchRegs = NUM_MISCREGS;
const int NumMiscRegs = NUM_MISCREGS;

const int NumIntArchRegs = NUM_INTREGS;
const int NumIntRegs =
    NumIntArchRegs + NumMicroIntRegs +
    NumPseudoIntRegs + NumImplicitIntRegs;

//Each 128 bit xmm register is broken into two effective 64 bit registers.
const int NumFloatRegs =
    NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs;
const int NumFloatArchRegs = NumFloatRegs + 8;

// These enumerate all the registers for dependence tracking.
enum DependenceTags {
    //There are 16 microcode registers at the moment. This is an
    //unusually large constant to make sure there isn't overflow.
    FP_Base_DepTag = 128,
    Ctrl_Base_DepTag =
        FP_Base_DepTag +
        //mmx/x87 registers
        8 +
        //xmm registers
        16 * 2 +
        //The microcode fp registers
        8 +
        //The indices that are mapped over the fp stack
        8
};

// semantically meaningful register indices
//There is no such register in X86
const int ZeroReg = NUM_INTREGS;
const int StackPointerReg = INTREG_RSP;
//X86 doesn't seem to have a link register
const int ReturnAddressReg = 0;
const int ReturnValueReg = INTREG_RAX;
const int FramePointerReg = INTREG_RBP;

// Some OS syscalls use a second register (rdx) to return a second
// value
const int SyscallPseudoReturnReg = INTREG_RDX;

typedef uint64_t IntReg;
//XXX Should this be a 128 bit structure for XMM memory ops?
typedef uint64_t LargestRead;
typedef uint64_t MiscReg;

//These floating point types are correct for mmx, but not
//technically for x87 (80 bits) or at all for xmm (128 bits)
typedef double FloatReg;
typedef uint64_t FloatRegBits;
typedef union
{
    IntReg intReg;
    FloatReg fpReg;
    MiscReg ctrlReg;
} AnyReg;

typedef uint16_t RegIndex;

}; // namespace X86ISA

#endif // __ARCH_X86_REGFILE_HH__