| # -*- mode:python -*- |
| |
| # Copyright (c) 2007 MIPS Technologies, Inc. |
| # All rights reserved. |
| # |
| # Redistribution and use in source and binary forms, with or without |
| # modification, are permitted provided that the following conditions are |
| # met: redistributions of source code must retain the above copyright |
| # notice, this list of conditions and the following disclaimer; |
| # redistributions in binary form must reproduce the above copyright |
| # notice, this list of conditions and the following disclaimer in the |
| # documentation and/or other materials provided with the distribution; |
| # neither the name of the copyright holders nor the names of its |
| # contributors may be used to endorse or promote products derived from |
| # this software without specific prior written permission. |
| # |
| # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| # |
| # Authors: Korey Sewell |
| |
| Import('*') |
| |
| if 'InOrderCPU' in env['CPU_MODELS']: |
| SimObject('InOrderCPU.py') |
| SimObject('InOrderTrace.py') |
| |
| TraceFlag('ResReqCount') |
| TraceFlag('InOrderStage') |
| TraceFlag('InOrderStall') |
| TraceFlag('InOrderCPU') |
| TraceFlag('RegDepMap') |
| TraceFlag('InOrderDynInst') |
| TraceFlag('Resource') |
| TraceFlag('InOrderAGEN') |
| TraceFlag('InOrderFetchSeq') |
| TraceFlag('InOrderTLB') |
| TraceFlag('InOrderCachePort') |
| TraceFlag('InOrderBPred') |
| TraceFlag('InOrderDecode') |
| TraceFlag('InOrderExecute') |
| TraceFlag('InOrderInstBuffer') |
| TraceFlag('InOrderUseDef') |
| TraceFlag('InOrderMDU') |
| TraceFlag('InOrderGraduation') |
| TraceFlag('RefCount') |
| |
| CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall', 'InOrderCPU', |
| 'InOrderMDU', 'InOrderAGEN', 'InOrderFetchSeq', 'InOrderTLB', 'InOrderBPred', |
| 'InOrderDecode', 'InOrderExecute', 'InOrderInstBuffer', 'InOrderUseDef', |
| 'InOrderGraduation', 'InOrderCachePort', 'RegDepMap', 'Resource']) |
| |
| Source('pipeline_traits.cc') |
| Source('inorder_dyn_inst.cc') |
| Source('inorder_cpu_builder.cc') |
| Source('inorder_trace.cc') |
| Source('pipeline_stage.cc') |
| Source('first_stage.cc') |
| Source('resource.cc') |
| Source('resources/agen_unit.cc') |
| Source('resources/execution_unit.cc') |
| Source('resources/bpred_unit.cc') |
| Source('resources/branch_predictor.cc') |
| Source('resources/cache_unit.cc') |
| Source('resources/use_def.cc') |
| Source('resources/decode_unit.cc') |
| Source('resources/inst_buffer.cc') |
| Source('resources/graduation_unit.cc') |
| Source('resources/fetch_seq_unit.cc') |
| Source('resources/mult_div_unit.cc') |
| Source('resource_pool.cc') |
| Source('reg_dep_map.cc') |
| Source('thread_context.cc') |
| Source('cpu.cc') |
| |