src/cpu/simple/AtomicSimpleCPU.py

# Copyright (c) 2007 The Regents of The University of Michigan
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# Authors: Nathan Binkert

from m5.params import *
from m5 import build_env
from BaseSimpleCPU import BaseSimpleCPU

class AtomicSimpleCPU(BaseSimpleCPU):
    type = 'AtomicSimpleCPU'
    width = Param.Int(1, "CPU width")
    simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
    simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
    icache_port = Port("Instruction Port")
    dcache_port = Port("Data Port")
    physmem_port = Port("Physical Memory Port")
    _mem_ports = BaseSimpleCPU._mem_ports + \
                    ['icache_port', 'dcache_port', 'physmem_port']