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gem5
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arm
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gem5
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d7aef8be964b5f7eee2dace0cfc347fb23fa7ab2
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.
/
build_opts
/
RISCV
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TARGET_ISA
=
'riscv'
CPU_MODELS
=
'AtomicSimpleCPU,TimingSimpleCPU,MinorCPU,O3CPU'
PROTOCOL
=
'MI_example'
