alpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA::NoopMachInst.
It's no longer used.
Change-Id: I4a71bcb214f1bb186b92ef50841eca635e6701c5
Reviewed-on: https://gem5-review.googlesource.com/6826
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
index f1c39cb..54b8003 100644
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -111,10 +111,6 @@
const int MachineBytes = 8;
-// return a no-op instruction... used for instruction fetch faults
-// Alpha UNOP (ldq_u r31,0(r0))
-const ExtMachInst NoopMachInst = 0x2ffe0000;
-
// Memory accesses cannot be unaligned
const bool HasUnalignedMemAcc = false;
diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index 8be2bf0..fa27795 100644
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -96,9 +96,6 @@
// Max. physical address range in bits supported by the architecture
const unsigned MaxPhysAddrRange = 48;
- // return a no-op instruction... used for instruction fetch faults
- const ExtMachInst NoopMachInst = 0x01E320F000ULL;
-
const int MachineBytes = 4;
const uint32_t HighVecs = 0xFFFF0000;
diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index ca375f2..7a16071 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -142,9 +142,6 @@
mode_number // number of modes
};
-// return a no-op instruction... used for instruction fetch faults
-const ExtMachInst NoopMachInst = 0x00000000;
-
const int ANNOTE_NONE = 0;
const uint32_t ITOUCH_ANNOTE = 0xffffffff;
diff --git a/src/arch/power/isa_traits.hh b/src/arch/power/isa_traits.hh
index 3abc831..41a8d7d 100644
--- a/src/arch/power/isa_traits.hh
+++ b/src/arch/power/isa_traits.hh
@@ -63,9 +63,6 @@
const int MachineBytes = 4;
-// This is ori 0, 0, 0
-const ExtMachInst NoopMachInst = 0x60000000;
-
// Memory accesses can be unaligned
const bool HasUnalignedMemAcc = true;
diff --git a/src/arch/riscv/isa_traits.hh b/src/arch/riscv/isa_traits.hh
index 327d644..21e684a 100644
--- a/src/arch/riscv/isa_traits.hh
+++ b/src/arch/riscv/isa_traits.hh
@@ -63,8 +63,6 @@
const Addr PageShift = 12;
const Addr PageBytes = ULL(1) << PageShift;
-const ExtMachInst NoopMachInst = 0x00000013;
-
// Memory accesses can be unaligned (at least for double-word memory accesses)
const bool HasUnalignedMemAcc = true;
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index b925386..4f98f75 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -47,9 +47,6 @@
// SPARC has a delay slot
#define ISA_HAS_DELAY_SLOT 1
-// SPARC NOP (sethi %(hi(0), g0)
-const MachInst NoopMachInst = 0x01000000;
-
// real address virtual mapping
// sort of like alpha super page, but less frequently used
const Addr SegKPMEnd = ULL(0xfffffffc00000000);
diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index 88cd16e..2b19b1b 100644
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -56,10 +56,6 @@
// X86 does not have a delay slot
#define ISA_HAS_DELAY_SLOT 0
- // X86 NOP (XCHG rAX, rAX)
- //XXX This needs to be set to an intermediate instruction struct
- //which encodes this instruction
-
const Addr PageShift = 12;
const Addr PageBytes = ULL(1) << PageShift;
@@ -68,19 +64,6 @@
const bool CurThreadInfoImplemented = false;
const int CurThreadInfoReg = -1;
-
- const ExtMachInst NoopMachInst M5_VAR_USED = {
- 0x0, // No legacy prefixes.
- 0x0, // No rex prefix.
- 0x0, // No two / three byte escape sequence
- { OneByteOpcode, 0x90 }, // One opcode byte, 0x90.
- 0x0, 0x0, // No modrm or sib.
- 0, 0, // No immediate or displacement.
- 8, 8, 8, // All sizes are 8.
- 0, // Displacement size is 0.
- SixtyFourBitMode // Behave as if we're in 64 bit
- // mode (this doesn't actually matter).
- };
}
#endif // __ARCH_X86_ISATRAITS_HH__
