| // Copyright (c) 2007 The Regents of The University of Michigan |
| // All rights reserved. |
| // |
| // Redistribution and use in source and binary forms, with or without |
| // modification, are permitted provided that the following conditions are |
| // met: redistributions of source code must retain the above copyright |
| // notice, this list of conditions and the following disclaimer; |
| // redistributions in binary form must reproduce the above copyright |
| // notice, this list of conditions and the following disclaimer in the |
| // documentation and/or other materials provided with the distribution; |
| // neither the name of the copyright holders nor the names of its |
| // contributors may be used to endorse or promote products derived from |
| // this software without specific prior written permission. |
| // |
| // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| // |
| // Authors: Gabe Black |
| |
| // Copyright (c) 2007 The Hewlett-Packard Development Company |
| // All rights reserved. |
| // |
| // Redistribution and use of this software in source and binary forms, |
| // with or without modification, are permitted provided that the |
| // following conditions are met: |
| // |
| // The software must be used only for Non-Commercial Use which means any |
| // use which is NOT directed to receiving any direct monetary |
| // compensation for, or commercial advantage from such use. Illustrative |
| // examples of non-commercial use are academic research, personal study, |
| // teaching, education and corporate research & development. |
| // Illustrative examples of commercial use are distributing products for |
| // commercial advantage and providing services using the software for |
| // commercial advantage. |
| // |
| // If you wish to use this software or functionality therein that may be |
| // covered by patents for commercial use, please contact: |
| // Director of Intellectual Property Licensing |
| // Office of Strategy and Technology |
| // Hewlett-Packard Company |
| // 1501 Page Mill Road |
| // Palo Alto, California 94304 |
| // |
| // Redistributions of source code must retain the above copyright notice, |
| // this list of conditions and the following disclaimer. Redistributions |
| // in binary form must reproduce the above copyright notice, this list of |
| // conditions and the following disclaimer in the documentation and/or |
| // other materials provided with the distribution. Neither the name of |
| // the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its |
| // contributors may be used to endorse or promote products derived from |
| // this software without specific prior written permission. No right of |
| // sublicense is granted herewith. Derivatives of the software and |
| // output created using the software may be prepared, but only for |
| // Non-Commercial Uses. Derivatives of the software may be shared with |
| // others provided: (i) the others agree to abide by the list of |
| // conditions herein which includes the Non-Commercial Use restrictions; |
| // and (ii) such Derivatives of the software include the above copyright |
| // notice to acknowledge the contribution from this software where |
| // applicable, this list of conditions and the disclaimer below. |
| // |
| // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| // |
| // Authors: Gabe Black |
| |
| def operand_types {{ |
| 'sb' : ('signed int', 8), |
| 'ub' : ('unsigned int', 8), |
| 'sw' : ('signed int', 16), |
| 'uw' : ('unsigned int', 16), |
| 'sdw' : ('signed int', 32), |
| 'udw' : ('unsigned int', 32), |
| 'sqw' : ('signed int', 64), |
| 'uqw' : ('unsigned int', 64), |
| 'sf' : ('float', 32), |
| 'df' : ('float', 64), |
| }}; |
| |
| def operands {{ |
| 'SrcReg1': ('IntReg', 'uqw', 'INTREG_FOLDED(src1, foldOBit)', 'IsInteger', 1), |
| 'SSrcReg1': ('IntReg', 'uqw', 'src1', 'IsInteger', 1), |
| 'SrcReg2': ('IntReg', 'uqw', 'INTREG_FOLDED(src2, foldOBit)', 'IsInteger', 2), |
| 'SSrcReg2': ('IntReg', 'uqw', 'src2', 'IsInteger', 1), |
| 'Index': ('IntReg', 'uqw', 'INTREG_FOLDED(index, foldABit)', 'IsInteger', 3), |
| 'Base': ('IntReg', 'uqw', 'INTREG_FOLDED(base, foldABit)', 'IsInteger', 4), |
| 'DestReg': ('IntReg', 'uqw', 'INTREG_FOLDED(dest, foldOBit)', 'IsInteger', 5), |
| 'SDestReg': ('IntReg', 'uqw', 'dest', 'IsInteger', 5), |
| 'Data': ('IntReg', 'uqw', 'INTREG_FOLDED(data, foldOBit)', 'IsInteger', 6), |
| 'ProdLow': ('IntReg', 'uqw', 'INTREG_IMPLICIT(0)', 'IsInteger', 7), |
| 'ProdHi': ('IntReg', 'uqw', 'INTREG_IMPLICIT(1)', 'IsInteger', 8), |
| 'Quotient': ('IntReg', 'uqw', 'INTREG_IMPLICIT(2)', 'IsInteger', 9), |
| 'Remainder': ('IntReg', 'uqw', 'INTREG_IMPLICIT(3)', 'IsInteger', 10), |
| 'Divisor': ('IntReg', 'uqw', 'INTREG_IMPLICIT(4)', 'IsInteger', 11), |
| 'rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 12), |
| 'FpSrcReg1': ('FloatReg', 'df', 'src1', 'IsFloating', 20), |
| 'FpSrcReg2': ('FloatReg', 'df', 'src2', 'IsFloating', 21), |
| 'FpDestReg': ('FloatReg', 'df', 'dest', 'IsFloating', 22), |
| 'FpData': ('FloatReg', 'df', 'data', 'IsFloating', 23), |
| 'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 50), |
| 'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 51), |
| 'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 52), |
| 'ccFlagBits': ('IntReg', 'uqw', 'INTREG_PSEUDO(0)', None, 60), |
| # The TOP register should needs to be more protected so that later |
| # instructions don't map their indexes with an old value. |
| 'TOP': ('ControlReg', 'ub', 'MISCREG_X87_TOP', None, 61), |
| # The segment base as used by memory instructions. |
| 'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_EFF_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 70), |
| |
| # Operands to get and set registers indexed by the operands of the |
| # original instruction. |
| 'ControlDest': ('ControlReg', 'uqw', 'MISCREG_CR(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 100), |
| 'ControlSrc1': ('ControlReg', 'uqw', 'MISCREG_CR(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 101), |
| 'SegBaseDest': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 102), |
| 'SegBaseSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 103), |
| 'SegLimitDest': ('ControlReg', 'uqw', 'MISCREG_SEG_LIMIT(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 104), |
| 'SegLimitSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_LIMIT(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 105), |
| 'SegSelDest': ('ControlReg', 'uqw', 'MISCREG_SEG_SEL(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 106), |
| 'SegSelSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_SEL(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 107), |
| 'SegAttrDest': ('ControlReg', 'uqw', 'MISCREG_SEG_ATTR(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 108), |
| 'SegAttrSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_ATTR(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 109), |
| |
| # Operands to access specific control registers directly. |
| 'EferOp': ('ControlReg', 'uqw', 'MISCREG_EFER', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 200), |
| 'CR4Op': ('ControlReg', 'uqw', 'MISCREG_CR4', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 201), |
| 'LDTRBase': ('ControlReg', 'uqw', 'MISCREG_TSL_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 202), |
| 'LDTRLimit': ('ControlReg', 'uqw', 'MISCREG_TSL_LIMIT', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 203), |
| 'LDTRSel': ('ControlReg', 'uqw', 'MISCREG_TSL', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 204), |
| 'GDTRBase': ('ControlReg', 'uqw', 'MISCREG_TSG_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 205), |
| 'GDTRLimit': ('ControlReg', 'uqw', 'MISCREG_TSG_LIMIT', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 206), |
| 'CSBase': ('ControlReg', 'udw', 'MISCREG_CS_EFF_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 207), |
| 'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 300) |
| }}; |