| |
| ---------- Begin Simulation Statistics ---------- |
| sim_seconds 0.132570 # Number of seconds simulated |
| sim_ticks 132570000500 # Number of ticks simulated |
| final_tick 132570000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| sim_freq 1000000000000 # Frequency of simulated ticks |
| host_inst_rate 373440 # Simulator instruction rate (inst/s) |
| host_op_rate 393666 # Simulator op (including micro ops) rate (op/s) |
| host_tick_rate 287300012 # Simulator tick rate (ticks/s) |
| host_mem_usage 274936 # Number of bytes of host memory used |
| host_seconds 461.43 # Real time elapsed on the host |
| sim_insts 172317810 # Number of instructions simulated |
| sim_ops 181650743 # Number of ops (including micro ops) simulated |
| system.voltage_domain.voltage 1 # Voltage in Volts |
| system.clk_domain.clock 1000 # Clock period in ticks |
| system.physmem.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states |
| system.physmem.bytes_read::cpu.inst 138240 # Number of bytes read from this memory |
| system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory |
| system.physmem.bytes_read::total 247552 # Number of bytes read from this memory |
| system.physmem.bytes_inst_read::cpu.inst 138240 # Number of instructions bytes read from this memory |
| system.physmem.bytes_inst_read::total 138240 # Number of instructions bytes read from this memory |
| system.physmem.num_reads::cpu.inst 2160 # Number of read requests responded to by this memory |
| system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory |
| system.physmem.num_reads::total 3868 # Number of read requests responded to by this memory |
| system.physmem.bw_read::cpu.inst 1042770 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_read::cpu.data 824561 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_read::total 1867330 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_inst_read::cpu.inst 1042770 # Instruction read bandwidth from this memory (bytes/s) |
| system.physmem.bw_inst_read::total 1042770 # Instruction read bandwidth from this memory (bytes/s) |
| system.physmem.bw_total::cpu.inst 1042770 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.bw_total::cpu.data 824561 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.bw_total::total 1867330 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.readReqs 3868 # Number of read requests accepted |
| system.physmem.writeReqs 0 # Number of write requests accepted |
| system.physmem.readBursts 3868 # Number of DRAM read bursts, including those serviced by the write queue |
| system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| system.physmem.bytesReadDRAM 247552 # Total number of bytes read from DRAM |
| system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue |
| system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| system.physmem.bytesReadSys 247552 # Total read bytes from the system interface side |
| system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side |
| system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue |
| system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| system.physmem.perBankRdBursts::0 305 # Per bank write bursts |
| system.physmem.perBankRdBursts::1 217 # Per bank write bursts |
| system.physmem.perBankRdBursts::2 135 # Per bank write bursts |
| system.physmem.perBankRdBursts::3 313 # Per bank write bursts |
| system.physmem.perBankRdBursts::4 306 # Per bank write bursts |
| system.physmem.perBankRdBursts::5 305 # Per bank write bursts |
| system.physmem.perBankRdBursts::6 273 # Per bank write bursts |
| system.physmem.perBankRdBursts::7 222 # Per bank write bursts |
| system.physmem.perBankRdBursts::8 248 # Per bank write bursts |
| system.physmem.perBankRdBursts::9 218 # Per bank write bursts |
| system.physmem.perBankRdBursts::10 296 # Per bank write bursts |
| system.physmem.perBankRdBursts::11 200 # Per bank write bursts |
| system.physmem.perBankRdBursts::12 183 # Per bank write bursts |
| system.physmem.perBankRdBursts::13 218 # Per bank write bursts |
| system.physmem.perBankRdBursts::14 224 # Per bank write bursts |
| system.physmem.perBankRdBursts::15 205 # Per bank write bursts |
| system.physmem.perBankWrBursts::0 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::1 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::2 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::3 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::4 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::5 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::6 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::7 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::8 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::9 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::10 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::11 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::12 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::13 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::14 0 # Per bank write bursts |
| system.physmem.perBankWrBursts::15 0 # Per bank write bursts |
| system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| system.physmem.totGap 132569899500 # Total gap between requests |
| system.physmem.readPktSize::0 0 # Read request sizes (log2) |
| system.physmem.readPktSize::1 0 # Read request sizes (log2) |
| system.physmem.readPktSize::2 0 # Read request sizes (log2) |
| system.physmem.readPktSize::3 0 # Read request sizes (log2) |
| system.physmem.readPktSize::4 0 # Read request sizes (log2) |
| system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| system.physmem.readPktSize::6 3868 # Read request sizes (log2) |
| system.physmem.writePktSize::0 0 # Write request sizes (log2) |
| system.physmem.writePktSize::1 0 # Write request sizes (log2) |
| system.physmem.writePktSize::2 0 # Write request sizes (log2) |
| system.physmem.writePktSize::3 0 # Write request sizes (log2) |
| system.physmem.writePktSize::4 0 # Write request sizes (log2) |
| system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| system.physmem.rdQLenPdf::0 3619 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::1 239 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| system.physmem.bytesPerActivate::samples 928 # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::mean 265.103448 # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::gmean 174.513478 # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::stdev 277.064139 # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::0-127 273 29.42% 29.42% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::128-255 364 39.22% 68.64% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::256-383 95 10.24% 78.88% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::384-511 53 5.71% 84.59% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::512-639 24 2.59% 87.18% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::640-767 21 2.26% 89.44% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::768-895 18 1.94% 91.38% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::896-1023 18 1.94% 93.32% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::1024-1151 62 6.68% 100.00% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::total 928 # Bytes accessed per row activation |
| system.physmem.totQLat 82551750 # Total ticks spent queuing |
| system.physmem.totMemAccLat 155076750 # Total ticks spent from burst creation until serviced by the DRAM |
| system.physmem.totBusLat 19340000 # Total ticks spent in databus transfers |
| system.physmem.avgQLat 21342.23 # Average queueing delay per DRAM burst |
| system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| system.physmem.avgMemAccLat 40092.23 # Average memory access latency per DRAM burst |
| system.physmem.avgRdBW 1.87 # Average DRAM read bandwidth in MiByte/s |
| system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| system.physmem.avgRdBWSys 1.87 # Average system read bandwidth in MiByte/s |
| system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s |
| system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| system.physmem.busUtil 0.01 # Data bus utilization in percentage |
| system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads |
| system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| system.physmem.readRowHits 2935 # Number of row buffer hits during reads |
| system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| system.physmem.readRowHitRate 75.88 # Row buffer hit rate for reads |
| system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| system.physmem.avgGap 34273500.39 # Average gap between requests |
| system.physmem.pageHitRate 75.88 # Row buffer hit rate, read and write combined |
| system.physmem_0.actEnergy 2963100 # Energy for activate commands per rank (pJ) |
| system.physmem_0.preEnergy 1574925 # Energy for precharge commands per rank (pJ) |
| system.physmem_0.readEnergy 14822640 # Energy for read commands per rank (pJ) |
| system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) |
| system.physmem_0.refreshEnergy 157347840.000000 # Energy for refresh commands per rank (pJ) |
| system.physmem_0.actBackEnergy 56147850 # Energy for active background per rank (pJ) |
| system.physmem_0.preBackEnergy 6612480 # Energy for precharge background per rank (pJ) |
| system.physmem_0.actPowerDownEnergy 497768460 # Energy for active power-down per rank (pJ) |
| system.physmem_0.prePowerDownEnergy 192585120 # Energy for precharge power-down per rank (pJ) |
| system.physmem_0.selfRefreshEnergy 31420705950 # Energy for self refresh per rank (pJ) |
| system.physmem_0.totalEnergy 32350562865 # Total energy per rank (pJ) |
| system.physmem_0.averagePower 244.026270 # Core power per rank (mW) |
| system.physmem_0.totalIdleTime 132428576750 # Total Idle time Per DRAM Rank |
| system.physmem_0.memoryStateTime::IDLE 10716000 # Time in different power states |
| system.physmem_0.memoryStateTime::REF 66782000 # Time in different power states |
| system.physmem_0.memoryStateTime::SREF 130836450000 # Time in different power states |
| system.physmem_0.memoryStateTime::PRE_PDN 501553500 # Time in different power states |
| system.physmem_0.memoryStateTime::ACT 62926000 # Time in different power states |
| system.physmem_0.memoryStateTime::ACT_PDN 1091573000 # Time in different power states |
| system.physmem_1.actEnergy 3698520 # Energy for activate commands per rank (pJ) |
| system.physmem_1.preEnergy 1946835 # Energy for precharge commands per rank (pJ) |
| system.physmem_1.readEnergy 12794880 # Energy for read commands per rank (pJ) |
| system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) |
| system.physmem_1.refreshEnergy 143211120.000000 # Energy for refresh commands per rank (pJ) |
| system.physmem_1.actBackEnergy 50027190 # Energy for active background per rank (pJ) |
| system.physmem_1.preBackEnergy 5428800 # Energy for precharge background per rank (pJ) |
| system.physmem_1.actPowerDownEnergy 512852940 # Energy for active power-down per rank (pJ) |
| system.physmem_1.prePowerDownEnergy 149734560 # Energy for precharge power-down per rank (pJ) |
| system.physmem_1.selfRefreshEnergy 31437405705 # Energy for self refresh per rank (pJ) |
| system.physmem_1.totalEnergy 32317131480 # Total energy per rank (pJ) |
| system.physmem_1.averagePower 243.774090 # Core power per rank (mW) |
| system.physmem_1.totalIdleTime 132446049750 # Total Idle time Per DRAM Rank |
| system.physmem_1.memoryStateTime::IDLE 8198000 # Time in different power states |
| system.physmem_1.memoryStateTime::REF 60730000 # Time in different power states |
| system.physmem_1.memoryStateTime::SREF 130931475750 # Time in different power states |
| system.physmem_1.memoryStateTime::PRE_PDN 389968500 # Time in different power states |
| system.physmem_1.memoryStateTime::ACT 54962000 # Time in different power states |
| system.physmem_1.memoryStateTime::ACT_PDN 1124666250 # Time in different power states |
| system.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states |
| system.cpu.branchPred.lookups 49693872 # Number of BP lookups |
| system.cpu.branchPred.condPredicted 39498414 # Number of conditional branches predicted |
| system.cpu.branchPred.condIncorrect 5520434 # Number of conditional branches incorrect |
| system.cpu.branchPred.BTBLookups 24194736 # Number of BTB lookups |
| system.cpu.branchPred.BTBHits 22923274 # Number of BTB hits |
| system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| system.cpu.branchPred.BTBHitPct 94.744882 # BTB Hit Percentage |
| system.cpu.branchPred.usedRAS 1894785 # Number of times the RAS was used to get a target. |
| system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions. |
| system.cpu.branchPred.indirectLookups 213909 # Number of indirect predictor lookups. |
| system.cpu.branchPred.indirectHits 208025 # Number of indirect target hits. |
| system.cpu.branchPred.indirectMisses 5884 # Number of indirect misses. |
| system.cpu.branchPredindirectMispredicted 40447 # Number of mispredicted indirect branches. |
| system.cpu_clk_domain.clock 500 # Clock period in ticks |
| system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits |
| system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses |
| system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits |
| system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses |
| system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits |
| system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB |
| system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions |
| system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses |
| system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses |
| system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses |
| system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits |
| system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses |
| system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states |
| system.cpu.dtb.walker.walks 0 # Table walker walks requested |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.inst_hits 0 # ITB inst hits |
| system.cpu.dtb.inst_misses 0 # ITB inst misses |
| system.cpu.dtb.read_hits 0 # DTB read hits |
| system.cpu.dtb.read_misses 0 # DTB read misses |
| system.cpu.dtb.write_hits 0 # DTB write hits |
| system.cpu.dtb.write_misses 0 # DTB write misses |
| system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed |
| system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB |
| system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions |
| system.cpu.dtb.read_accesses 0 # DTB read accesses |
| system.cpu.dtb.write_accesses 0 # DTB write accesses |
| system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| system.cpu.dtb.hits 0 # DTB hits |
| system.cpu.dtb.misses 0 # DTB misses |
| system.cpu.dtb.accesses 0 # DTB accesses |
| system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states |
| system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits |
| system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses |
| system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits |
| system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses |
| system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits |
| system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB |
| system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions |
| system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses |
| system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses |
| system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses |
| system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits |
| system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses |
| system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states |
| system.cpu.itb.walker.walks 0 # Table walker walks requested |
| system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.inst_hits 0 # ITB inst hits |
| system.cpu.itb.inst_misses 0 # ITB inst misses |
| system.cpu.itb.read_hits 0 # DTB read hits |
| system.cpu.itb.read_misses 0 # DTB read misses |
| system.cpu.itb.write_hits 0 # DTB write hits |
| system.cpu.itb.write_misses 0 # DTB write misses |
| system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed |
| system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB |
| system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions |
| system.cpu.itb.read_accesses 0 # DTB read accesses |
| system.cpu.itb.write_accesses 0 # DTB write accesses |
| system.cpu.itb.inst_accesses 0 # ITB inst accesses |
| system.cpu.itb.hits 0 # DTB hits |
| system.cpu.itb.misses 0 # DTB misses |
| system.cpu.itb.accesses 0 # DTB accesses |
| system.cpu.workload.numSyscalls 400 # Number of system calls |
| system.cpu.pwrStateResidencyTicks::ON 132570000500 # Cumulative time (in ticks) in various power states |
| system.cpu.numCycles 265140001 # number of cpu cycles simulated |
| system.cpu.numWorkItemsStarted 0 # number of work items this cpu started |
| system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| system.cpu.committedInsts 172317810 # Number of instructions committed |
| system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed |
| system.cpu.discardedOps 11517797 # Number of ops (including micro ops) which were discarded before commit |
| system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| system.cpu.cpi 1.538669 # CPI: cycles per instruction |
| system.cpu.ipc 0.649913 # IPC: instructions per cycle |
| system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| system.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction |
| system.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction |
| system.cpu.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction |
| system.cpu.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction |
| system.cpu.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction |
| system.cpu.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction |
| system.cpu.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction |
| system.cpu.op_class_0::FloatMultAcc 0 0.00% 77.01% # Class of committed instruction |
| system.cpu.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction |
| system.cpu.op_class_0::FloatMisc 0 0.00% 77.01% # Class of committed instruction |
| system.cpu.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction |
| system.cpu.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction |
| system.cpu.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction |
| system.cpu.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction |
| system.cpu.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction |
| system.cpu.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction |
| system.cpu.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction |
| system.cpu.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction |
| system.cpu.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction |
| system.cpu.op_class_0::SimdShift 0 0.00% 77.01% # Class of committed instruction |
| system.cpu.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction |
| system.cpu.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction |
| system.cpu.op_class_0::MemRead 27348059 15.06% 92.74% # Class of committed instruction |
| system.cpu.op_class_0::MemWrite 12498389 6.88% 99.62% # Class of committed instruction |
| system.cpu.op_class_0::FloatMemRead 548085 0.30% 99.92% # Class of committed instruction |
| system.cpu.op_class_0::FloatMemWrite 146246 0.08% 100.00% # Class of committed instruction |
| system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction |
| system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| system.cpu.op_class_0::total 181650743 # Class of committed instruction |
| system.cpu.tickCycles 256807085 # Number of cycles that the object actually ticked |
| system.cpu.idleCycles 8332916 # Total number of cycles that the object has spent stopped |
| system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states |
| system.cpu.dcache.tags.replacements 42 # number of replacements |
| system.cpu.dcache.tags.tagsinuse 1378.592517 # Cycle average of tags in use |
| system.cpu.dcache.tags.total_refs 40754461 # Total number of references to valid blocks. |
| system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks. |
| system.cpu.dcache.tags.avg_refs 22503.843733 # Average number of references to valid blocks. |
| system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| system.cpu.dcache.tags.occ_blocks::cpu.data 1378.592517 # Average occupied blocks per requestor |
| system.cpu.dcache.tags.occ_percent::cpu.data 0.336570 # Average percentage of cache occupancy |
| system.cpu.dcache.tags.occ_percent::total 0.336570 # Average percentage of cache occupancy |
| system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id |
| system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id |
| system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id |
| system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id |
| system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id |
| system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id |
| system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id |
| system.cpu.dcache.tags.tag_accesses 81515543 # Number of tag accesses |
| system.cpu.dcache.tags.data_accesses 81515543 # Number of data accesses |
| system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states |
| system.cpu.dcache.ReadReq_hits::cpu.data 28346550 # number of ReadReq hits |
| system.cpu.dcache.ReadReq_hits::total 28346550 # number of ReadReq hits |
| system.cpu.dcache.WriteReq_hits::cpu.data 12362634 # number of WriteReq hits |
| system.cpu.dcache.WriteReq_hits::total 12362634 # number of WriteReq hits |
| system.cpu.dcache.SoftPFReq_hits::cpu.data 463 # number of SoftPFReq hits |
| system.cpu.dcache.SoftPFReq_hits::total 463 # number of SoftPFReq hits |
| system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits |
| system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits |
| system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits |
| system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits |
| system.cpu.dcache.demand_hits::cpu.data 40709184 # number of demand (read+write) hits |
| system.cpu.dcache.demand_hits::total 40709184 # number of demand (read+write) hits |
| system.cpu.dcache.overall_hits::cpu.data 40709647 # number of overall hits |
| system.cpu.dcache.overall_hits::total 40709647 # number of overall hits |
| system.cpu.dcache.ReadReq_misses::cpu.data 751 # number of ReadReq misses |
| system.cpu.dcache.ReadReq_misses::total 751 # number of ReadReq misses |
| system.cpu.dcache.WriteReq_misses::cpu.data 1653 # number of WriteReq misses |
| system.cpu.dcache.WriteReq_misses::total 1653 # number of WriteReq misses |
| system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses |
| system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses |
| system.cpu.dcache.demand_misses::cpu.data 2404 # number of demand (read+write) misses |
| system.cpu.dcache.demand_misses::total 2404 # number of demand (read+write) misses |
| system.cpu.dcache.overall_misses::cpu.data 2405 # number of overall misses |
| system.cpu.dcache.overall_misses::total 2405 # number of overall misses |
| system.cpu.dcache.ReadReq_miss_latency::cpu.data 64086500 # number of ReadReq miss cycles |
| system.cpu.dcache.ReadReq_miss_latency::total 64086500 # number of ReadReq miss cycles |
| system.cpu.dcache.WriteReq_miss_latency::cpu.data 146233500 # number of WriteReq miss cycles |
| system.cpu.dcache.WriteReq_miss_latency::total 146233500 # number of WriteReq miss cycles |
| system.cpu.dcache.demand_miss_latency::cpu.data 210320000 # number of demand (read+write) miss cycles |
| system.cpu.dcache.demand_miss_latency::total 210320000 # number of demand (read+write) miss cycles |
| system.cpu.dcache.overall_miss_latency::cpu.data 210320000 # number of overall miss cycles |
| system.cpu.dcache.overall_miss_latency::total 210320000 # number of overall miss cycles |
| system.cpu.dcache.ReadReq_accesses::cpu.data 28347301 # number of ReadReq accesses(hits+misses) |
| system.cpu.dcache.ReadReq_accesses::total 28347301 # number of ReadReq accesses(hits+misses) |
| system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) |
| system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) |
| system.cpu.dcache.SoftPFReq_accesses::cpu.data 464 # number of SoftPFReq accesses(hits+misses) |
| system.cpu.dcache.SoftPFReq_accesses::total 464 # number of SoftPFReq accesses(hits+misses) |
| system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) |
| system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) |
| system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) |
| system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) |
| system.cpu.dcache.demand_accesses::cpu.data 40711588 # number of demand (read+write) accesses |
| system.cpu.dcache.demand_accesses::total 40711588 # number of demand (read+write) accesses |
| system.cpu.dcache.overall_accesses::cpu.data 40712052 # number of overall (read+write) accesses |
| system.cpu.dcache.overall_accesses::total 40712052 # number of overall (read+write) accesses |
| system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses |
| system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses |
| system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000134 # miss rate for WriteReq accesses |
| system.cpu.dcache.WriteReq_miss_rate::total 0.000134 # miss rate for WriteReq accesses |
| system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002155 # miss rate for SoftPFReq accesses |
| system.cpu.dcache.SoftPFReq_miss_rate::total 0.002155 # miss rate for SoftPFReq accesses |
| system.cpu.dcache.demand_miss_rate::cpu.data 0.000059 # miss rate for demand accesses |
| system.cpu.dcache.demand_miss_rate::total 0.000059 # miss rate for demand accesses |
| system.cpu.dcache.overall_miss_rate::cpu.data 0.000059 # miss rate for overall accesses |
| system.cpu.dcache.overall_miss_rate::total 0.000059 # miss rate for overall accesses |
| system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 85334.886818 # average ReadReq miss latency |
| system.cpu.dcache.ReadReq_avg_miss_latency::total 85334.886818 # average ReadReq miss latency |
| system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 88465.517241 # average WriteReq miss latency |
| system.cpu.dcache.WriteReq_avg_miss_latency::total 88465.517241 # average WriteReq miss latency |
| system.cpu.dcache.demand_avg_miss_latency::cpu.data 87487.520799 # average overall miss latency |
| system.cpu.dcache.demand_avg_miss_latency::total 87487.520799 # average overall miss latency |
| system.cpu.dcache.overall_avg_miss_latency::cpu.data 87451.143451 # average overall miss latency |
| system.cpu.dcache.overall_avg_miss_latency::total 87451.143451 # average overall miss latency |
| system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| system.cpu.dcache.writebacks::writebacks 16 # number of writebacks |
| system.cpu.dcache.writebacks::total 16 # number of writebacks |
| system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits |
| system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits |
| system.cpu.dcache.WriteReq_mshr_hits::cpu.data 554 # number of WriteReq MSHR hits |
| system.cpu.dcache.WriteReq_mshr_hits::total 554 # number of WriteReq MSHR hits |
| system.cpu.dcache.demand_mshr_hits::cpu.data 594 # number of demand (read+write) MSHR hits |
| system.cpu.dcache.demand_mshr_hits::total 594 # number of demand (read+write) MSHR hits |
| system.cpu.dcache.overall_mshr_hits::cpu.data 594 # number of overall MSHR hits |
| system.cpu.dcache.overall_mshr_hits::total 594 # number of overall MSHR hits |
| system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses |
| system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses |
| system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1099 # number of WriteReq MSHR misses |
| system.cpu.dcache.WriteReq_mshr_misses::total 1099 # number of WriteReq MSHR misses |
| system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses |
| system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses |
| system.cpu.dcache.demand_mshr_misses::cpu.data 1810 # number of demand (read+write) MSHR misses |
| system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses |
| system.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses |
| system.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses |
| system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 60392000 # number of ReadReq MSHR miss cycles |
| system.cpu.dcache.ReadReq_mshr_miss_latency::total 60392000 # number of ReadReq MSHR miss cycles |
| system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 99618500 # number of WriteReq MSHR miss cycles |
| system.cpu.dcache.WriteReq_mshr_miss_latency::total 99618500 # number of WriteReq MSHR miss cycles |
| system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 77000 # number of SoftPFReq MSHR miss cycles |
| system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 77000 # number of SoftPFReq MSHR miss cycles |
| system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160010500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.dcache.demand_mshr_miss_latency::total 160010500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.dcache.overall_mshr_miss_latency::cpu.data 160087500 # number of overall MSHR miss cycles |
| system.cpu.dcache.overall_mshr_miss_latency::total 160087500 # number of overall MSHR miss cycles |
| system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses |
| system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses |
| system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses |
| system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses |
| system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002155 # mshr miss rate for SoftPFReq accesses |
| system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002155 # mshr miss rate for SoftPFReq accesses |
| system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses |
| system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses |
| system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses |
| system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84939.521800 # average ReadReq mshr miss latency |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84939.521800 # average ReadReq mshr miss latency |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 90644.676979 # average WriteReq mshr miss latency |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 90644.676979 # average WriteReq mshr miss latency |
| system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 77000 # average SoftPFReq mshr miss latency |
| system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 77000 # average SoftPFReq mshr miss latency |
| system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88403.591160 # average overall mshr miss latency |
| system.cpu.dcache.demand_avg_mshr_miss_latency::total 88403.591160 # average overall mshr miss latency |
| system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88397.294313 # average overall mshr miss latency |
| system.cpu.dcache.overall_avg_mshr_miss_latency::total 88397.294313 # average overall mshr miss latency |
| system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states |
| system.cpu.icache.tags.replacements 2861 # number of replacements |
| system.cpu.icache.tags.tagsinuse 1424.892665 # Cycle average of tags in use |
| system.cpu.icache.tags.total_refs 70991309 # Total number of references to valid blocks. |
| system.cpu.icache.tags.sampled_refs 4660 # Sample count of references to valid blocks. |
| system.cpu.icache.tags.avg_refs 15234.186481 # Average number of references to valid blocks. |
| system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| system.cpu.icache.tags.occ_blocks::cpu.inst 1424.892665 # Average occupied blocks per requestor |
| system.cpu.icache.tags.occ_percent::cpu.inst 0.695748 # Average percentage of cache occupancy |
| system.cpu.icache.tags.occ_percent::total 0.695748 # Average percentage of cache occupancy |
| system.cpu.icache.tags.occ_task_id_blocks::1024 1799 # Occupied blocks per task id |
| system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id |
| system.cpu.icache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id |
| system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id |
| system.cpu.icache.tags.age_task_id_blocks_1024::3 131 # Occupied blocks per task id |
| system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id |
| system.cpu.icache.tags.occ_task_id_percent::1024 0.878418 # Percentage of cache occupancy per task id |
| system.cpu.icache.tags.tag_accesses 141996600 # Number of tag accesses |
| system.cpu.icache.tags.data_accesses 141996600 # Number of data accesses |
| system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states |
| system.cpu.icache.ReadReq_hits::cpu.inst 70991309 # number of ReadReq hits |
| system.cpu.icache.ReadReq_hits::total 70991309 # number of ReadReq hits |
| system.cpu.icache.demand_hits::cpu.inst 70991309 # number of demand (read+write) hits |
| system.cpu.icache.demand_hits::total 70991309 # number of demand (read+write) hits |
| system.cpu.icache.overall_hits::cpu.inst 70991309 # number of overall hits |
| system.cpu.icache.overall_hits::total 70991309 # number of overall hits |
| system.cpu.icache.ReadReq_misses::cpu.inst 4661 # number of ReadReq misses |
| system.cpu.icache.ReadReq_misses::total 4661 # number of ReadReq misses |
| system.cpu.icache.demand_misses::cpu.inst 4661 # number of demand (read+write) misses |
| system.cpu.icache.demand_misses::total 4661 # number of demand (read+write) misses |
| system.cpu.icache.overall_misses::cpu.inst 4661 # number of overall misses |
| system.cpu.icache.overall_misses::total 4661 # number of overall misses |
| system.cpu.icache.ReadReq_miss_latency::cpu.inst 236001500 # number of ReadReq miss cycles |
| system.cpu.icache.ReadReq_miss_latency::total 236001500 # number of ReadReq miss cycles |
| system.cpu.icache.demand_miss_latency::cpu.inst 236001500 # number of demand (read+write) miss cycles |
| system.cpu.icache.demand_miss_latency::total 236001500 # number of demand (read+write) miss cycles |
| system.cpu.icache.overall_miss_latency::cpu.inst 236001500 # number of overall miss cycles |
| system.cpu.icache.overall_miss_latency::total 236001500 # number of overall miss cycles |
| system.cpu.icache.ReadReq_accesses::cpu.inst 70995970 # number of ReadReq accesses(hits+misses) |
| system.cpu.icache.ReadReq_accesses::total 70995970 # number of ReadReq accesses(hits+misses) |
| system.cpu.icache.demand_accesses::cpu.inst 70995970 # number of demand (read+write) accesses |
| system.cpu.icache.demand_accesses::total 70995970 # number of demand (read+write) accesses |
| system.cpu.icache.overall_accesses::cpu.inst 70995970 # number of overall (read+write) accesses |
| system.cpu.icache.overall_accesses::total 70995970 # number of overall (read+write) accesses |
| system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses |
| system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses |
| system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses |
| system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses |
| system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses |
| system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses |
| system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50633.233212 # average ReadReq miss latency |
| system.cpu.icache.ReadReq_avg_miss_latency::total 50633.233212 # average ReadReq miss latency |
| system.cpu.icache.demand_avg_miss_latency::cpu.inst 50633.233212 # average overall miss latency |
| system.cpu.icache.demand_avg_miss_latency::total 50633.233212 # average overall miss latency |
| system.cpu.icache.overall_avg_miss_latency::cpu.inst 50633.233212 # average overall miss latency |
| system.cpu.icache.overall_avg_miss_latency::total 50633.233212 # average overall miss latency |
| system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| system.cpu.icache.writebacks::writebacks 2861 # number of writebacks |
| system.cpu.icache.writebacks::total 2861 # number of writebacks |
| system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4661 # number of ReadReq MSHR misses |
| system.cpu.icache.ReadReq_mshr_misses::total 4661 # number of ReadReq MSHR misses |
| system.cpu.icache.demand_mshr_misses::cpu.inst 4661 # number of demand (read+write) MSHR misses |
| system.cpu.icache.demand_mshr_misses::total 4661 # number of demand (read+write) MSHR misses |
| system.cpu.icache.overall_mshr_misses::cpu.inst 4661 # number of overall MSHR misses |
| system.cpu.icache.overall_mshr_misses::total 4661 # number of overall MSHR misses |
| system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 231341500 # number of ReadReq MSHR miss cycles |
| system.cpu.icache.ReadReq_mshr_miss_latency::total 231341500 # number of ReadReq MSHR miss cycles |
| system.cpu.icache.demand_mshr_miss_latency::cpu.inst 231341500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.icache.demand_mshr_miss_latency::total 231341500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.icache.overall_mshr_miss_latency::cpu.inst 231341500 # number of overall MSHR miss cycles |
| system.cpu.icache.overall_mshr_miss_latency::total 231341500 # number of overall MSHR miss cycles |
| system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses |
| system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses |
| system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses |
| system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses |
| system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses |
| system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49633.447758 # average ReadReq mshr miss latency |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49633.447758 # average ReadReq mshr miss latency |
| system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49633.447758 # average overall mshr miss latency |
| system.cpu.icache.demand_avg_mshr_miss_latency::total 49633.447758 # average overall mshr miss latency |
| system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49633.447758 # average overall mshr miss latency |
| system.cpu.icache.overall_avg_mshr_miss_latency::total 49633.447758 # average overall mshr miss latency |
| system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states |
| system.cpu.l2cache.tags.replacements 0 # number of replacements |
| system.cpu.l2cache.tags.tagsinuse 2835.344855 # Cycle average of tags in use |
| system.cpu.l2cache.tags.total_refs 5154 # Total number of references to valid blocks. |
| system.cpu.l2cache.tags.sampled_refs 3868 # Sample count of references to valid blocks. |
| system.cpu.l2cache.tags.avg_refs 1.332472 # Average number of references to valid blocks. |
| system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.641960 # Average occupied blocks per requestor |
| system.cpu.l2cache.tags.occ_blocks::cpu.data 1327.702895 # Average occupied blocks per requestor |
| system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046010 # Average percentage of cache occupancy |
| system.cpu.l2cache.tags.occ_percent::cpu.data 0.040518 # Average percentage of cache occupancy |
| system.cpu.l2cache.tags.occ_percent::total 0.086528 # Average percentage of cache occupancy |
| system.cpu.l2cache.tags.occ_task_id_blocks::1024 3868 # Occupied blocks per task id |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::2 534 # Occupied blocks per task id |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::3 367 # Occupied blocks per task id |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2841 # Occupied blocks per task id |
| system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118042 # Percentage of cache occupancy per task id |
| system.cpu.l2cache.tags.tag_accesses 76180 # Number of tag accesses |
| system.cpu.l2cache.tags.data_accesses 76180 # Number of data accesses |
| system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states |
| system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits |
| system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits |
| system.cpu.l2cache.WritebackClean_hits::writebacks 2531 # number of WritebackClean hits |
| system.cpu.l2cache.WritebackClean_hits::total 2531 # number of WritebackClean hits |
| system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits |
| system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits |
| system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2499 # number of ReadCleanReq hits |
| system.cpu.l2cache.ReadCleanReq_hits::total 2499 # number of ReadCleanReq hits |
| system.cpu.l2cache.ReadSharedReq_hits::cpu.data 80 # number of ReadSharedReq hits |
| system.cpu.l2cache.ReadSharedReq_hits::total 80 # number of ReadSharedReq hits |
| system.cpu.l2cache.demand_hits::cpu.inst 2499 # number of demand (read+write) hits |
| system.cpu.l2cache.demand_hits::cpu.data 88 # number of demand (read+write) hits |
| system.cpu.l2cache.demand_hits::total 2587 # number of demand (read+write) hits |
| system.cpu.l2cache.overall_hits::cpu.inst 2499 # number of overall hits |
| system.cpu.l2cache.overall_hits::cpu.data 88 # number of overall hits |
| system.cpu.l2cache.overall_hits::total 2587 # number of overall hits |
| system.cpu.l2cache.ReadExReq_misses::cpu.data 1091 # number of ReadExReq misses |
| system.cpu.l2cache.ReadExReq_misses::total 1091 # number of ReadExReq misses |
| system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2162 # number of ReadCleanReq misses |
| system.cpu.l2cache.ReadCleanReq_misses::total 2162 # number of ReadCleanReq misses |
| system.cpu.l2cache.ReadSharedReq_misses::cpu.data 632 # number of ReadSharedReq misses |
| system.cpu.l2cache.ReadSharedReq_misses::total 632 # number of ReadSharedReq misses |
| system.cpu.l2cache.demand_misses::cpu.inst 2162 # number of demand (read+write) misses |
| system.cpu.l2cache.demand_misses::cpu.data 1723 # number of demand (read+write) misses |
| system.cpu.l2cache.demand_misses::total 3885 # number of demand (read+write) misses |
| system.cpu.l2cache.overall_misses::cpu.inst 2162 # number of overall misses |
| system.cpu.l2cache.overall_misses::cpu.data 1723 # number of overall misses |
| system.cpu.l2cache.overall_misses::total 3885 # number of overall misses |
| system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 97884500 # number of ReadExReq miss cycles |
| system.cpu.l2cache.ReadExReq_miss_latency::total 97884500 # number of ReadExReq miss cycles |
| system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 197728500 # number of ReadCleanReq miss cycles |
| system.cpu.l2cache.ReadCleanReq_miss_latency::total 197728500 # number of ReadCleanReq miss cycles |
| system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 58476500 # number of ReadSharedReq miss cycles |
| system.cpu.l2cache.ReadSharedReq_miss_latency::total 58476500 # number of ReadSharedReq miss cycles |
| system.cpu.l2cache.demand_miss_latency::cpu.inst 197728500 # number of demand (read+write) miss cycles |
| system.cpu.l2cache.demand_miss_latency::cpu.data 156361000 # number of demand (read+write) miss cycles |
| system.cpu.l2cache.demand_miss_latency::total 354089500 # number of demand (read+write) miss cycles |
| system.cpu.l2cache.overall_miss_latency::cpu.inst 197728500 # number of overall miss cycles |
| system.cpu.l2cache.overall_miss_latency::cpu.data 156361000 # number of overall miss cycles |
| system.cpu.l2cache.overall_miss_latency::total 354089500 # number of overall miss cycles |
| system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses) |
| system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses) |
| system.cpu.l2cache.WritebackClean_accesses::writebacks 2531 # number of WritebackClean accesses(hits+misses) |
| system.cpu.l2cache.WritebackClean_accesses::total 2531 # number of WritebackClean accesses(hits+misses) |
| system.cpu.l2cache.ReadExReq_accesses::cpu.data 1099 # number of ReadExReq accesses(hits+misses) |
| system.cpu.l2cache.ReadExReq_accesses::total 1099 # number of ReadExReq accesses(hits+misses) |
| system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4661 # number of ReadCleanReq accesses(hits+misses) |
| system.cpu.l2cache.ReadCleanReq_accesses::total 4661 # number of ReadCleanReq accesses(hits+misses) |
| system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712 # number of ReadSharedReq accesses(hits+misses) |
| system.cpu.l2cache.ReadSharedReq_accesses::total 712 # number of ReadSharedReq accesses(hits+misses) |
| system.cpu.l2cache.demand_accesses::cpu.inst 4661 # number of demand (read+write) accesses |
| system.cpu.l2cache.demand_accesses::cpu.data 1811 # number of demand (read+write) accesses |
| system.cpu.l2cache.demand_accesses::total 6472 # number of demand (read+write) accesses |
| system.cpu.l2cache.overall_accesses::cpu.inst 4661 # number of overall (read+write) accesses |
| system.cpu.l2cache.overall_accesses::cpu.data 1811 # number of overall (read+write) accesses |
| system.cpu.l2cache.overall_accesses::total 6472 # number of overall (read+write) accesses |
| system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992721 # miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadExReq_miss_rate::total 0.992721 # miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.463849 # miss rate for ReadCleanReq accesses |
| system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.463849 # miss rate for ReadCleanReq accesses |
| system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.887640 # miss rate for ReadSharedReq accesses |
| system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.887640 # miss rate for ReadSharedReq accesses |
| system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463849 # miss rate for demand accesses |
| system.cpu.l2cache.demand_miss_rate::cpu.data 0.951408 # miss rate for demand accesses |
| system.cpu.l2cache.demand_miss_rate::total 0.600278 # miss rate for demand accesses |
| system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463849 # miss rate for overall accesses |
| system.cpu.l2cache.overall_miss_rate::cpu.data 0.951408 # miss rate for overall accesses |
| system.cpu.l2cache.overall_miss_rate::total 0.600278 # miss rate for overall accesses |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89719.981668 # average ReadExReq miss latency |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89719.981668 # average ReadExReq miss latency |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 91456.290472 # average ReadCleanReq miss latency |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 91456.290472 # average ReadCleanReq miss latency |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92526.107595 # average ReadSharedReq miss latency |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92526.107595 # average ReadSharedReq miss latency |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 91456.290472 # average overall miss latency |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90749.274521 # average overall miss latency |
| system.cpu.l2cache.demand_avg_miss_latency::total 91142.728443 # average overall miss latency |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 91456.290472 # average overall miss latency |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90749.274521 # average overall miss latency |
| system.cpu.l2cache.overall_avg_miss_latency::total 91142.728443 # average overall miss latency |
| system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits |
| system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits |
| system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 15 # number of ReadSharedReq MSHR hits |
| system.cpu.l2cache.ReadSharedReq_mshr_hits::total 15 # number of ReadSharedReq MSHR hits |
| system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits |
| system.cpu.l2cache.demand_mshr_hits::cpu.data 15 # number of demand (read+write) MSHR hits |
| system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits |
| system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits |
| system.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits |
| system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits |
| system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1091 # number of ReadExReq MSHR misses |
| system.cpu.l2cache.ReadExReq_mshr_misses::total 1091 # number of ReadExReq MSHR misses |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2161 # number of ReadCleanReq MSHR misses |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2161 # number of ReadCleanReq MSHR misses |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 617 # number of ReadSharedReq MSHR misses |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::total 617 # number of ReadSharedReq MSHR misses |
| system.cpu.l2cache.demand_mshr_misses::cpu.inst 2161 # number of demand (read+write) MSHR misses |
| system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses |
| system.cpu.l2cache.demand_mshr_misses::total 3869 # number of demand (read+write) MSHR misses |
| system.cpu.l2cache.overall_mshr_misses::cpu.inst 2161 # number of overall MSHR misses |
| system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses |
| system.cpu.l2cache.overall_mshr_misses::total 3869 # number of overall MSHR misses |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 86974500 # number of ReadExReq MSHR miss cycles |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 86974500 # number of ReadExReq MSHR miss cycles |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 176055000 # number of ReadCleanReq MSHR miss cycles |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 176055000 # number of ReadCleanReq MSHR miss cycles |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 50639500 # number of ReadSharedReq MSHR miss cycles |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 50639500 # number of ReadSharedReq MSHR miss cycles |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176055000 # number of demand (read+write) MSHR miss cycles |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137614000 # number of demand (read+write) MSHR miss cycles |
| system.cpu.l2cache.demand_mshr_miss_latency::total 313669000 # number of demand (read+write) MSHR miss cycles |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176055000 # number of overall MSHR miss cycles |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137614000 # number of overall MSHR miss cycles |
| system.cpu.l2cache.overall_mshr_miss_latency::total 313669000 # number of overall MSHR miss cycles |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for ReadCleanReq accesses |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.463634 # mshr miss rate for ReadCleanReq accesses |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.866573 # mshr miss rate for ReadSharedReq accesses |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.866573 # mshr miss rate for ReadSharedReq accesses |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for demand accesses |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for demand accesses |
| system.cpu.l2cache.demand_mshr_miss_rate::total 0.597806 # mshr miss rate for demand accesses |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for overall accesses |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses |
| system.cpu.l2cache.overall_mshr_miss_rate::total 0.597806 # mshr miss rate for overall accesses |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79719.981668 # average ReadExReq mshr miss latency |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79719.981668 # average ReadExReq mshr miss latency |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 81469.227210 # average ReadCleanReq mshr miss latency |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 81469.227210 # average ReadCleanReq mshr miss latency |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82073.743922 # average ReadSharedReq mshr miss latency |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82073.743922 # average ReadSharedReq mshr miss latency |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 81469.227210 # average overall mshr miss latency |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80570.257611 # average overall mshr miss latency |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81072.370121 # average overall mshr miss latency |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 81469.227210 # average overall mshr miss latency |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80570.257611 # average overall mshr miss latency |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81072.370121 # average overall mshr miss latency |
| system.cpu.toL2Bus.snoop_filter.tot_requests 9375 # Total number of requests made to the snoop filter. |
| system.cpu.toL2Bus.snoop_filter.hit_single_requests 3038 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| system.cpu.toL2Bus.snoop_filter.hit_multi_requests 336 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. |
| system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states |
| system.cpu.toL2Bus.trans_dist::ReadResp 5372 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::WritebackClean 2861 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::ReadExReq 1099 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::ReadExResp 1099 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::ReadCleanReq 4661 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution |
| system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12182 # Packet count per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3664 # Packet count per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_count::total 15846 # Packet count per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481344 # Cumulative packet size per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116928 # Cumulative packet size per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_size::total 598272 # Cumulative packet size per connected master and slave (bytes) |
| system.cpu.toL2Bus.snoops 0 # Total snoops (count) |
| system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) |
| system.cpu.toL2Bus.snoop_fanout::samples 6472 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::mean 0.072775 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::stdev 0.259787 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::0 6001 92.72% 92.72% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::1 471 7.28% 100.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::total 6472 # Request fanout histogram |
| system.cpu.toL2Bus.reqLayer0.occupancy 7564500 # Layer occupancy (ticks) |
| system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| system.cpu.toL2Bus.respLayer0.occupancy 6990499 # Layer occupancy (ticks) |
| system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| system.cpu.toL2Bus.respLayer1.occupancy 2723985 # Layer occupancy (ticks) |
| system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| system.membus.snoop_filter.tot_requests 3868 # Total number of requests made to the snoop filter. |
| system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. |
| system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| system.membus.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states |
| system.membus.trans_dist::ReadResp 2777 # Transaction distribution |
| system.membus.trans_dist::ReadExReq 1091 # Transaction distribution |
| system.membus.trans_dist::ReadExResp 1091 # Transaction distribution |
| system.membus.trans_dist::ReadSharedReq 2777 # Transaction distribution |
| system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7736 # Packet count per connected master and slave (bytes) |
| system.membus.pkt_count::total 7736 # Packet count per connected master and slave (bytes) |
| system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247552 # Cumulative packet size per connected master and slave (bytes) |
| system.membus.pkt_size::total 247552 # Cumulative packet size per connected master and slave (bytes) |
| system.membus.snoops 0 # Total snoops (count) |
| system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| system.membus.snoop_fanout::samples 3868 # Request fanout histogram |
| system.membus.snoop_fanout::mean 0 # Request fanout histogram |
| system.membus.snoop_fanout::stdev 0 # Request fanout histogram |
| system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| system.membus.snoop_fanout::0 3868 100.00% 100.00% # Request fanout histogram |
| system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram |
| system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| system.membus.snoop_fanout::min_value 0 # Request fanout histogram |
| system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| system.membus.snoop_fanout::total 3868 # Request fanout histogram |
| system.membus.reqLayer0.occupancy 4525000 # Layer occupancy (ticks) |
| system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| system.membus.respLayer1.occupancy 20564500 # Layer occupancy (ticks) |
| system.membus.respLayer1.utilization 0.0 # Layer utilization (%) |
| |
| ---------- End Simulation Statistics ---------- |
