x86, mem: Get rid of PageTableOps::getBasePtr.

Pass this constant into the page table constructor.

Change-Id: Icbf730f18d9dfcfebd10a196f7f799514728b0fb
Reviewed-on: https://gem5-review.googlesource.com/7345
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>

src/arch/x86/pagetable.hh

diff --git a/src/arch/x86/pagetable.hh b/src/arch/x86/pagetable.hh
index 354fb5a..490a259 100644
--- a/src/arch/x86/pagetable.hh
+++ b/src/arch/x86/pagetable.hh
@@ -179,14 +179,6 @@
             PTE.u   = flags & PTE_Supervisor  ? 0 : 1;
         }
 
-        /** returns the physical memory address of the page table */
-        Addr getBasePtr(ThreadContext* tc)
-        {
-            CR3 cr3 = pageTablePhysAddr;
-            DPRINTF(MMU, "CR3: %d\n", cr3);
-            return cr3.longPdtb;
-        }
-
         /** returns the page number out of a page table entry */
         Addr getPnum(PageTableEntry PTE)
         {

src/arch/x86/process.cc

diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index 627750c..0a94ac4 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -100,9 +100,11 @@
                        SyscallDesc *_syscallDescs, int _numSyscallDescs)
     : Process(params, params->useArchPT ?
                       static_cast<EmulationPageTable *>(
-                              new ArchPageTable(params->name, params->pid,
-                                                params->system, PageBytes,
-                                                PageTableLayout)) :
+                              new ArchPageTable(
+                                      params->name, params->pid,
+                                      params->system, PageBytes,
+                                      PageTableLayout,
+                                      pageTablePhysAddr >> PageShift)) :
                       new EmulationPageTable(params->name, params->pid,
                                              PageBytes),
               objFile),

src/mem/multi_level_page_table.hh

diff --git a/src/mem/multi_level_page_table.hh b/src/mem/multi_level_page_table.hh
index f71dc0d..7cbbd8c 100644
--- a/src/mem/multi_level_page_table.hh
+++ b/src/mem/multi_level_page_table.hh
@@ -140,7 +140,8 @@
 public:
     MultiLevelPageTable(const std::string &__name, uint64_t _pid,
                         System *_sys, Addr pageSize,
-                        const std::vector<uint8_t> &layout);
+                        const std::vector<uint8_t> &layout,
+                        Addr _basePtr);
     ~MultiLevelPageTable();
 
     void initState(ThreadContext* tc) override;

src/mem/multi_level_page_table_impl.hh

diff --git a/src/mem/multi_level_page_table_impl.hh b/src/mem/multi_level_page_table_impl.hh
index 2d7ddc4..3356c9e 100644
--- a/src/mem/multi_level_page_table_impl.hh
+++ b/src/mem/multi_level_page_table_impl.hh
@@ -47,10 +47,9 @@
 template <class ISAOps>
 MultiLevelPageTable<ISAOps>::MultiLevelPageTable(
         const std::string &__name, uint64_t _pid, System *_sys,
-        Addr pageSize, const std::vector<uint8_t> &layout)
+        Addr pageSize, const std::vector<uint8_t> &layout, Addr _basePtr)
     : EmulationPageTable(__name, _pid, pageSize), system(_sys),
-    logLevelSize(layout),
-    numLevels(logLevelSize.size())
+    basePtr(_basePtr), logLevelSize(layout), numLevels(logLevelSize.size())
 {
 }
 
@@ -63,11 +62,6 @@
 void
 MultiLevelPageTable<ISAOps>::initState(ThreadContext* tc)
 {
-    basePtr = pTableISAOps.getBasePtr(tc);
-    if (basePtr == 0)
-        basePtr++;
-    DPRINTF(MMU, "basePtr: %d\n", basePtr);
-
     system->pagePtr = basePtr;
 
     /* setting first level of the page table */