commit b618e733bd580391702a844404417f9723b94588
author Kevin Lim <ktlim@umich.edu> Wed Dec 06 14:23:31 2006 -0500
committer Kevin Lim <ktlim@umich.edu> Wed Dec 06 14:23:31 2006 -0500
tree 806c1b04918416d5e88c80e99a58b1164e9f2a68
parent 54a946604b2fa81c0d58fc41bfe1d82840f44793

Fix for MIPS_SE/m5.fast compile.

--HG--
extra : convert_revision : dbb893250974ac6db7b6c1ba67263fd35098ca43

src/cpu/o3/commit_impl.hh

diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 43305f9..f400d75 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -1197,16 +1197,16 @@
              rename_idx < fromRename->size;
              rename_idx++) {
             DynInstPtr inst = fromRename->insts[rename_idx];
-            int tid = inst->threadNumber;
 
             if (!inst->isSquashed()) {
                 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
-                        "skidBuffer.\n", inst->readPC(), inst->seqNum, tid);
+                        "skidBuffer.\n", inst->readPC(), inst->seqNum,
+                        inst->threadNumber);
                 skidBuffer.push(inst);
             } else {
                 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
                         "squashed, skipping.\n",
-                        inst->readPC(), inst->seqNum, tid);
+                        inst->readPC(), inst->seqNum, inst->threadNumber);
             }
         }
     }