| // -*- mode:c++ -*- |
| |
| // Copyright (c) 2006 The Regents of The University of Michigan |
| // All rights reserved. |
| // |
| // Redistribution and use in source and binary forms, with or without |
| // modification, are permitted provided that the following conditions are |
| // met: redistributions of source code must retain the above copyright |
| // notice, this list of conditions and the following disclaimer; |
| // redistributions in binary form must reproduce the above copyright |
| // notice, this list of conditions and the following disclaimer in the |
| // documentation and/or other materials provided with the distribution; |
| // neither the name of the copyright holders nor the names of its |
| // contributors may be used to endorse or promote products derived from |
| // this software without specific prior written permission. |
| // |
| // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| // |
| // Authors: Korey Sewell |
| |
| def operand_types {{ |
| 'sb' : ('signed int', 8), |
| 'ub' : ('unsigned int', 8), |
| 'sh' : ('signed int', 16), |
| 'uh' : ('unsigned int', 16), |
| 'sw' : ('signed int', 32), |
| 'uw' : ('unsigned int', 32), |
| 'sd' : ('signed int', 64), |
| 'ud' : ('unsigned int', 64), |
| 'sf' : ('float', 32), |
| 'df' : ('float', 64), |
| 'qf' : ('float', 128) |
| }}; |
| |
| def operands {{ |
| #General Purpose Integer Reg Operands |
| 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1), |
| 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2), |
| 'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3), |
| |
| #Operands used for Link or Syscall Insts |
| 'R31': ('IntReg', 'uw','31','IsInteger', 4), |
| 'R2': ('IntReg', 'uw','2', 'IsInteger', 5), |
| |
| #Special Integer Reg operands |
| 'HI': ('IntReg', 'uw','MipsISA::HI', 'IsInteger', 6), |
| 'LO': ('IntReg', 'uw','MipsISA::LO', 'IsInteger', 7), |
| |
| #Immediate Value operand |
| 'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3), |
| |
| #Floating Point Reg Operands |
| 'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1), |
| 'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2), |
| 'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3), |
| 'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3), |
| |
| #Special Floating Point Control Reg Operands |
| 'FIR': ('FloatReg', 'uw', 'MipsISA::FIR', 'IsFloating', 1), |
| 'FCCR': ('FloatReg', 'uw', 'MipsISA::FCCR', 'IsFloating', 2), |
| 'FEXR': ('FloatReg', 'uw', 'MipsISA::FEXR', 'IsFloating', 3), |
| 'FENR': ('FloatReg', 'uw', 'MipsISA::FENR', 'IsFloating', 3), |
| 'FCSR': ('FloatReg', 'uw', 'MipsISA::FCSR', 'IsFloating', 3), |
| |
| #Operands For Paired Singles FP Operations |
| 'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4), |
| 'Fd2': ('FloatReg', 'sf', 'FD+1', 'IsFloating', 4), |
| 'Fs1': ('FloatReg', 'sf', 'FS', 'IsFloating', 5), |
| 'Fs2': ('FloatReg', 'sf', 'FS+1', 'IsFloating', 5), |
| 'Ft1': ('FloatReg', 'sf', 'FT', 'IsFloating', 6), |
| 'Ft2': ('FloatReg', 'sf', 'FT+1', 'IsFloating', 6), |
| 'Fr1': ('FloatReg', 'sf', 'FR', 'IsFloating', 7), |
| 'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7), |
| |
| #Memory Operand |
| 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), |
| |
| #Program Counter Operands |
| 'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4), |
| 'NNPC':('NNPC', 'uw', None, ( None, None, 'IsControl' ), 4) |
| }}; |