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# Copyright (c) 2012 ARM Limited
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# Copyright (c) 2005 The Regents of The University of Michigan
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# Authors: Ron Dreslinski
from ClockedObject import ClockedObject
from m5.params import *
from m5.proxy import *
class BasePrefetcher(ClockedObject):
type = 'BasePrefetcher'
abstract = True
cxx_header = "mem/cache/prefetch/base.hh"
size = Param.Int(100,
"Number of entries in the hardware prefetch queue")
cross_pages = Param.Bool(False,
"Allow prefetches to cross virtual page boundaries")
serial_squash = Param.Bool(False,
"Squash prefetches with a later time on a subsequent miss")
degree = Param.Int(1,
"Degree of the prefetch depth")
latency = Param.Cycles('1', "Latency of the prefetcher")
use_master_id = Param.Bool(True,
"Use the master id to separate calculations of prefetches")
data_accesses_only = Param.Bool(False,
"Only prefetch on data not on instruction accesses")
on_miss_only = Param.Bool(False,
"Only prefetch on miss (as opposed to always)")
on_read_only = Param.Bool(False,
"Only prefetch on read requests (write requests ignored)")
on_prefetch = Param.Bool(True,
"Let lower cache prefetcher train on prefetch requests")
inst_tagged = Param.Bool(True,
"Perform a tagged prefetch for instruction fetches always")
sys = Param.System(Parent.any, "System this device belongs to")
class StridePrefetcher(BasePrefetcher):
type = 'StridePrefetcher'
cxx_class = 'StridePrefetcher'
cxx_header = "mem/cache/prefetch/stride.hh"
class TaggedPrefetcher(BasePrefetcher):
type = 'TaggedPrefetcher'
cxx_class = 'TaggedPrefetcher'
cxx_header = "mem/cache/prefetch/tagged.hh"