| # Copyright (c) 2012 ARM Limited | |
| # All rights reserved. | |
| # | |
| # The license below extends only to copyright in the software and shall | |
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| # to a hardware implementation of the functionality of the software | |
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| # unmodified and in its entirety in all distributions of the software, | |
| # modified or unmodified, in source code or in binary form. | |
| # | |
| # Redistribution and use in source and binary forms, with or without | |
| # modification, are permitted provided that the following conditions are | |
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| # neither the name of the copyright holders nor the names of its | |
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| # this software without specific prior written permission. | |
| # | |
| # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
| # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
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| # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| # | |
| # Authors: Thomas Grass | |
| # Andreas Hansson | |
| # Sascha Bischoff | |
| from m5.params import * | |
| from m5.proxy import * | |
| from MemObject import MemObject | |
| # The traffic generator is a master module that generates stimuli for | |
| # the memory system, based on a collection of simple behaviours that | |
| # are either probabilistic or based on traces. It can be used stand | |
| # alone for creating test cases for interconnect and memory | |
| # controllers, or function as a black-box replacement for system | |
| # components that are not yet modelled in detail, e.g. a video engine | |
| # or baseband subsystem in an SoC. | |
| # | |
| # The traffic generator has a single master port that is used to send | |
| # requests, independent of the specific behaviour. The behaviour of | |
| # the traffic generator is specified in a configuration file, and this | |
| # file describes a state transition graph where each state is a | |
| # specific generator behaviour. Examples include idling, generating | |
| # linear address sequences, random sequences and replay of captured | |
| # traces. By describing these behaviours as states, it is straight | |
| # forward to create very complex behaviours, simply by arranging them | |
| # in graphs. The graph transitions can also be annotated with | |
| # probabilities, effectively making it a Markov Chain. | |
| class TrafficGen(MemObject): | |
| type = 'TrafficGen' | |
| cxx_header = "cpu/testers/traffic_gen/traffic_gen.hh" | |
| # Port used for sending requests and receiving responses | |
| port = MasterPort("Master port") | |
| # Config file to parse for the state descriptions | |
| config_file = Param.String("Configuration file describing the behaviour") | |
| # System used to determine the mode of the memory system | |
| system = Param.System(Parent.any, "System this generator is part of") | |
| # Should requests respond to back-pressure or not, if true, the | |
| # rate of the traffic generator will be slowed down if requests | |
| # are not immediately accepted | |
| elastic_req = Param.Bool(False, | |
| "Slow down requests in case of backpressure") |