| # Copyright (c) 2012 ARM Limited | |
| # All rights reserved | |
| # | |
| # The license below extends only to copyright in the software and shall | |
| # not be construed as granting a license to any other intellectual | |
| # property including but not limited to intellectual property relating | |
| # to a hardware implementation of the functionality of the software | |
| # licensed hereunder. You may use the software subject to the license | |
| # terms below provided that you ensure that this notice is replicated | |
| # unmodified and in its entirety in all distributions of the software, | |
| # modified or unmodified, in source code or in binary form. | |
| # | |
| # Redistribution and use in source and binary forms, with or without | |
| # modification, are permitted provided that the following conditions are | |
| # met: redistributions of source code must retain the above copyright | |
| # notice, this list of conditions and the following disclaimer; | |
| # redistributions in binary form must reproduce the above copyright | |
| # notice, this list of conditions and the following disclaimer in the | |
| # documentation and/or other materials provided with the distribution; | |
| # neither the name of the copyright holders nor the names of its | |
| # contributors may be used to endorse or promote products derived from | |
| # this software without specific prior written permission. | |
| # | |
| # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
| # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
| # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
| # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
| # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
| # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
| # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
| # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
| # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
| # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
| # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| # | |
| # Author: Dam Sunwoo | |
| # | |
| # Sample stats config file (AtomicSimpleCPU) for m5stats2streamline.py | |
| # | |
| # Stats grouped together will show as grouped in Streamline. | |
| # E.g., | |
| # | |
| # commit_inst_count = | |
| # system.cluster.cpu#.commit.committedInsts | |
| # system.cluster.cpu#.commit.commitSquashedInsts | |
| # | |
| # will display the inst counts (committed/squashed) as a stacked line chart. | |
| # Charts will still be configurable in Streamline. | |
| [PER_CPU_STATS] | |
| # '#' will be automatically replaced with the correct CPU id. | |
| commit_inst_count = | |
| system.cluster.cpu#.committedInsts | |
| cycles = | |
| system.cluster.cpu#.num_busy_cycles | |
| system.cluster.cpu#.num_idle_cycles | |
| register_access = | |
| system.cluster.cpu#.num_int_register_reads | |
| system.cluster.cpu#.num_int_register_writes | |
| mem_refs = | |
| system.cluster.cpu#.num_mem_refs | |
| inst_breakdown = | |
| system.cluster.cpu#.num_conditional_control_insts | |
| system.cluster.cpu#.num_int_insts | |
| system.cluster.cpu#.num_fp_insts | |
| system.cluster.cpu#.num_load_insts | |
| system.cluster.cpu#.num_store_insts | |
| icache = | |
| system.cluster.il1_cache#.overall_hits::total | |
| system.cluster.il1_cache#.overall_misses::total | |
| dcache = | |
| system.cluster.dl1_cache#.overall_hits::total | |
| system.cluster.dl1_cache#.overall_misses::total | |
| [PER_L2_STATS] | |
| # '#' will be automatically replaced with the correct L2 id. | |
| l2_cache = | |
| system.cluster.l2_cache#.overall_hits::total | |
| system.cluster.l2_cache#.overall_misses::total | |
| [OTHER_STATS] | |
| # Anything that doesn't belong to CPU or L2 caches | |
| physmem = | |
| system.memsys.mem_ctrls.bytes_read::total | |
| system.memsys.mem_ctrls.bytes_written::total |