Google Git
Sign in
gem5 / arm / gem5 / eddac53ff60c579eff28134bde84783fe36d6214 / src / mem / cache / base.cc
  1. eddac53 trace: reimplement the DTRACE function so it doesn't use a vector by Nathan Binkert · 14 years ago
  2. a432d8e Mem: Fix issue with dirty block being lost when entire block transferred to non-cache. by Ali Saidi · 14 years ago
  3. 6f11879 Replace curTick global variable with accessor functions. by Steve Reinhardt · 14 years ago
  4. 1d32284 cache: Make caches sharing aware and add occupancy stats. by Lisa Hsu · 15 years ago
  5. 6faf377 types: clean up types, especially signed vs unsigned by Nathan Binkert · 16 years ago
  6. 6629d9b mem: use single BadAddr responder per system. by Steve Reinhardt · 17 years ago
  7. e063210 eventq: convert all usage of events to use the new API. by Nathan Binkert · 16 years ago
  8. 9d7a69c Fix #include lines for renamed cache files. by Steve Reinhardt · 17 years ago
  9. d56e77c Rename cache files for brevity and consistency with rest of tree. by Steve Reinhardt · 17 years ago[Renamed from src/mem/cache/base_cache.cc]
  10. 3952e41 Add functional PrintReq command for memory-system debugging. by Steve Reinhardt · 17 years ago
  11. 54cc005 params: Deprecate old-style constructors; update most SimObject constructors. by Miles Kaufmann · 18 years ago
  12. 06a9f58 DMA: Add IOCache and fix bus bridge to optionally only send requests one by Ali Saidi · 18 years ago
  13. 2f93db6 memory system: fix functional access bug. by Steve Reinhardt · 18 years ago
  14. 6babda7 Fix up a few statistics problems. by Steve Reinhardt · 18 years ago
  15. 6ab5341 Get rid of Packet result field. Error responses are now encoded in cmd field. by Steve Reinhardt · 18 years ago
  16. 529f12a Get rid of requestCauses. Use timestamped queue to make by Steve Reinhardt · 18 years ago
  17. 47bce8e Better handling of deferred targets. by Steve Reinhardt · 18 years ago
  18. bdd5fd2 Fixes to hitLatency, blocking, buffer allocation. by Steve Reinhardt · 18 years ago
  19. 83af0fd Getting closer... by Steve Reinhardt · 18 years ago
  20. 35cf19d More major reorg of cache. Seems to work for atomic mode now, by Steve Reinhardt · 18 years ago
  21. da46364 Fix getDeviceAddressRanges() to get snooping right. by Steve Reinhardt · 18 years ago
  22. 0484867 Merge vm1.(none):/home/stever/bk/newmem-head by Steve Reinhardt · 18 years ago
  23. 4124179 Change getDeviceAddressRanges to use bool for snoop arg. by Steve Reinhardt · 18 years ago
  24. 792d5b9 First set of changes for reorganized cache coherence support. by Steve Reinhardt · 18 years ago
  25. fecae03 Eliminate unused PacketPtr from BaseCache's by Steve Reinhardt · 18 years ago
  26. df3fc36 Split BaseCache::CacheEvent into RequestEvent and ResponseEvent. by Steve Reinhardt · 18 years ago
  27. 997fc50 Make memory commands dense again to avoid cache stat table explosion. by Steve Reinhardt · 18 years ago
  28. 51e54f5 Minor DPRINTF fixes. by Steve Reinhardt · 18 years ago
  29. d172e15 Split CachePort class into CpuSidePort and MemSidePort by Steve Reinhardt · 18 years ago
  30. 903a618 Fix a bug to handle the fact that a CPU can send Functional accesses while a sendTiming has not returned in the call stack. by Ron Dreslinski · 18 years ago
  31. c577665 Fix functional access errors related to delayed respnoses in cachePort by Ron Dreslinski · 18 years ago
  32. f876bc2 More fixes for functional accesses. It now makes the writeback memory leak to crash all configs. by Ron Dreslinski · 18 years ago
  33. 8ba73da Fix up bus draining and add draining to the caches. by Kevin Lim · 18 years ago
  34. 8d53f29 Caches return a new functional port whenever asked for one. by Kevin Lim · 18 years ago
  35. b26355d Ports now have a pointer to the MemObject that owns it (can be NULL). by Kevin Lim · 18 years ago
  36. e321a21 Clean up cache DPRINTFs by Steve Reinhardt · 18 years ago
  37. 54ed57c Merge zizzer:/bk/newmem by Ron Dreslinski · 18 years ago
  38. 28e9641 Use fixPacket function everywhere. by Ron Dreslinski · 18 years ago
  39. a4c6f0d Use PacketPtr everywhere by Nathan Binkert · 18 years ago
  40. 7245d45 refactor code for the packet, get rid of packet_impl.hh by Nathan Binkert · 18 years ago
  41. 780aa0a Fix corner case on assertion. by Ron Dreslinski · 18 years ago
  42. 63c2a78 Merge zizzer:/bk/newmem by Ron Dreslinski · 18 years ago
  43. f735399 Include packet_impl.hh (need this on my laptop, by Steve Reinhardt · 18 years ago
  44. 9c582c7 Fixes for uni-coherence in timing mode for FS. by Ron Dreslinski · 18 years ago
  45. 4fff6d4 Fixes to cache eliminating the assumption that the Packet is still valid after sending out a request. by Ron Dreslinski · 18 years ago
  46. 288b98e Fix it so that the cache does not assume to gave the packet it sent out via sendTiming. by Ron Dreslinski · 18 years ago
  47. a17afb1 Fix for DMA's in FS caches. by Ron Dreslinski · 18 years ago
  48. eddbb68 Fix CSHR retrys by Ron Dreslinski · 18 years ago
  49. f89b56b Check the response queue on functional accesses. by Ron Dreslinski · 18 years ago
  50. c201260 Use bus response time paramteres Fix bug with deadlocking by Ron Dreslinski · 18 years ago
  51. 04f71f1 When turning asserts into if's don't forget to invert. by Ron Dreslinski · 18 years ago
  52. 23bbd14 Writebacks can be pulled out from under the BusRequest when snoops of uprgades to owned blocks hit in the WB buffer by Ron Dreslinski · 18 years ago
  53. c9102b0 Only issue responses if we aren;t already blocked by Ron Dreslinski · 18 years ago
  54. 1de8eae Debugging info by Ron Dreslinski · 18 years ago
  55. aff3d92 Some more code cleanup by Ron Dreslinski · 18 years ago
  56. 995146e Fix some more mem leaks, still some left Update retry mechanism by Ron Dreslinski · 18 years ago
  57. 9e008d7 Fix cshr Retry's Fix Upgrades being blocked by slave by Ron Dreslinski · 18 years ago
  58. a0472af Merge zizzer:/z/m5/Bitkeeper/newmem by Ron Dreslinski · 18 years ago
  59. cc78d86 Fix several bugs pertaining to upgrades/mem leaks. by Ron Dreslinski · 18 years ago
  60. 843888c Merge zizzer.eecs.umich.edu:/bk/newmem by Gabe Black · 18 years ago
  61. 13ac9a4 One step closet to having NACK's work. by Ron Dreslinski · 18 years ago
  62. a23c6a7 Merge zizzer.eecs.umich.edu:/bk/newmem by Gabe Black · 18 years ago
  63. afce51d Set size properly on uncache accesses by Ron Dreslinski · 18 years ago
  64. 4f93c43 Don't block responses even if the cache is blocked. by Ron Dreslinski · 18 years ago
  65. 0c574f1 missing else by Gabe Black · 18 years ago
  66. 467c17f Fix a missing pointer by Ron Dreslinski · 18 years ago
  67. fdaed2c No need to keep trying to request the data bus if we are already waiting. by Ron Dreslinski · 18 years ago
  68. df3014a Add mechanism for caches to handle failure of the fast path on responses. by Ron Dreslinski · 18 years ago
  69. 45f881a First pass at snooping stuff that compiles and doesn't break. by Ron Dreslinski · 18 years ago
  70. 2b70b74 Changes to build m5.fast by Steve Reinhardt · 19 years ago
  71. 8a82553 Fixes for blocking in the caches that needed to be pulled by Ron Dreslinski · 19 years ago
  72. dc375e4 Some changes to support blocking in the caches by Ron Dreslinski · 19 years ago
  73. 6592045 Some fixes so that MSHR's are matched and we don't issue overlapping requests with detailed cpu by Ron Dreslinski · 19 years ago
  74. 7811500 Fix address range calculation. Still need bus to handle snoop ranges. by Ron Dreslinski · 19 years ago
  75. ea11c7bd Update cpus to use the getPort function to use a connector object to connect the I/D cache ports to memory by Ron Dreslinski · 19 years ago
  76. 1ccfdb4 Timing cache works for hello world test. by Ron Dreslinski · 19 years ago
  77. 329e32f Now timing reads work in single level of cache with simple cpu by Ron Dreslinski · 19 years ago
  78. 1bdc65b First pass, now compiles with current head of tree. by Ron Dreslinski · 19 years ago
  79. dea1a19 Fix the packet data allocation methods. Small fixes from changesets after my initial work. by Ron Dreslinski · 19 years ago
  80. fc281d0 Backing in more changsets, getting closer to compile by Ron Dreslinski · 19 years ago
  81. ed8564a Was having difficulty with merging the cache, reverted to an early version and will add back in the patches to make it work soon. by Ron Dreslinski · 19 years ago