- 6a98856 arm, base: Generalize and move the BitUnion hash struct. by Gabe Black · 5 years ago
- 039d914 sim: Use the new BitUnion templates in serialize.hh. by Gabe Black · 5 years ago
- 0d56fde base: Enable specializing templates on BitUnion types. by Gabe Black · 5 years ago
- cd9450c base: Rework bitunions so they can be more flexible. by Gabe Black · 5 years ago
- ecec887 sim, arch, base: Refactor the base remote GDB class. by Gabe Black · 5 years ago
- 372adea arch, mem, sim: Consolidate and rename the SE mode page table classes. by Gabe Black · 5 years ago
- d76798c util: Add an option to specify paths in list_changes.py by Andreas Sandberg · 5 years ago
- be5f483 mem: Change the multilevel page table to inherit from FuncPageTable. by Gabe Black · 5 years ago
- 096cdd5 arch-riscv: Fix floating-poing op classes by Alec Roelke · 5 years ago
- 34364ff arch-riscv: Fix floating-point conversion bugs by Alec Roelke · 5 years ago
- 6946720 sim: Simplify registerThreadContext a little bit. by Gabe Black · 5 years ago
- b8b1320 mem: Track TLB entries in the lookup cache as pointers. by Gabe Black · 5 years ago
- 3e8d76e arch: Fix a fatal_if in most of the arch's process classes. by Gabe Black · 5 years ago
- 5320a97 sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy(). by Xiaoyu Ma · 5 years ago
- cc51037 util/m5: add Android.mk by Earl Ou · 5 years ago
- b622601 arch-riscv: Don't crash when printing unknown CSRs by Alec Roelke · 5 years ago
- 1437a24 mem-ruby: Fix wakeup timeouts for the MOESI_CMP_token protocol by Nikos Nikoleris · 5 years ago
- 9737d93 mem-ruby: Remove function that maps responses to a DMA engine by Nikos Nikoleris · 5 years ago
- c6c2227 mem-ruby: Add support for multiple DMA engines in MESI_Two_Level by Nikos Nikoleris · 5 years ago
- f3d4d6f cpu: Make the CPU's TLB parameter a BaseTLB. by Gabe Black · 5 years ago
- f96e542 arm, power: Make the python TLB simobjects inherit from BaseTLB. by Gabe Black · 5 years ago
- ad0056d arch,mem: Remove the default value for page size. by Gabe Black · 5 years ago
- 54a9d47 arch,mem: Move page table construction into the arch classes. by Gabe Black · 5 years ago
- c2f3f6d configs: Fill in the cpu.isa field in etrace_replay.py since no default are provided now by Chen Zou · 5 years ago
- 1246617 style: change C/C++ source permissions to noexec by BKP · 5 years ago
- e228943 arch-riscv: Make use of ImmOp's polymorphism by Alec Roelke · 5 years ago
- 78524bd alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT. by Gabe Black · 5 years ago
- 3fb4d59 arch-riscv,sim: Support clone syscall in RISC-V by Tuan Ta · 6 years ago
- e823650 mem-cache: Prune unnecessary writebacks in exclusive caches by Nikos Nikoleris · 6 years ago
- 50f9ef0 util: Add the missing wakecpu m5op in X86. by Hanhwi Jang · 5 years ago
- f4ac367 util: resolve m5op name mismatching in m5op headers. by Hanhwi Jang · 5 years ago
- 3cc77c9 cpu: Use the NotAnInst flag to avoid passing an inst to fetch faults. by Gabe Black · 5 years ago
- ed8b7f2 cpu: Add a NotAnInst flag to the BaseDynInst class. by Gabe Black · 5 years ago
- b52ea6e cpu, power: Get rid of the remnants of the EA computation insts. by Gabe Black · 5 years ago
- 7221a00 arm: Make translateFunctional override the base implementation. by Gabe Black · 5 years ago
- 9fef867 gpu-compute: call createThreads() on cpu objs in apu_se.py by Tony Gutierrez · 5 years ago
- 954bd6b arch-riscv: Ignore sched_yield syscall in SE mode by Tuan Ta · 5 years ago
- d1f665a sim: Fix a bug in prlimit syscall in SE mode by Tuan Ta · 5 years ago
- ba4d3df arch-riscv: Ignore set_robust_list and get_robust_list syscalls by Tuan Ta · 5 years ago
- 0d100c3 arch-riscv: Add an implementation of set_tid_address syscall in RISCV by Tuan Ta · 5 years ago
- b001475 arch-riscv: Correct syscall argument reg count by Alec Roelke · 5 years ago
- 0d9f837 arch-riscv: Remove "magic" syscall number constant by Alec Roelke · 5 years ago
- 33ca06a config: Handle NULL simobject parameters in read_config.py. by Gabe Black · 5 years ago
- 8d68297 config: Fix parsing AddrRange parameters in read_config.py. by Gabe Black · 5 years ago
- c64c6c9 config: Add a --checkpoint-dir argument to read_config.py. by Gabe Black · 5 years ago
- da79d6c alpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA::NoopMachInst. by Gabe Black · 5 years ago
- 87eb9a3 riscv,x86: Stop using the arch Nop machine instruction unnecessarily. by Gabe Black · 5 years ago
- b7618c6 arch,cpu: "virtualize" the TLB interface. by Gabe Black · 5 years ago
- 4ac0a01 cpu: Use the generic nop static inst instead of decoding the arch version. by Gabe Black · 5 years ago
- 3742cc9 cpu: Add a pointer to a generic Nop StaticInst. by Gabe Black · 5 years ago
- 7df83c9 arch-arm: Fixed WFE/WFI trapping behaviour by Giacomo Travaglini · 5 years ago
- 0049df1 arch-arm: Hyp routed undef fault need to change its syndrome by Giacomo Travaglini · 5 years ago
- f9d6cf7 arch-arm: Fix StaticInst encoding() method by Giacomo Travaglini · 5 years ago
- de43751 cpu: Fix exit_gen.cc which used misc.hh instead of logging.hh. by Gabe Black · 5 years ago
- 1e05c29 arch-arm: Instruction size methods in StaticInst class by Giacomo Travaglini · 5 years ago
- 50749b8 arch-arm: Change casting type from reinterpret to static by Giacomo Travaglini · 5 years ago
- d17e77f cpu-tester: Added ExitGen to TrafficGen by Riken Gohil · 6 years ago
- 2a8e7a9 cpu-tester: Refactoring traffic generators into separate files. by Riken Gohil · 6 years ago
- 6ab6c52 mem-ruby: Support atomic_noncaching acceses in ruby by Swapnil Haria · 5 years ago
- c5095c7 arch-riscv: Define AT_RANDOM properly by Alec Roelke · 5 years ago
- e43d245 arch-riscv: Increase maximum stack size by Alec Roelke · 5 years ago
- 5c41076 misc: Updates for gcc7.2 for x86 by Jason Lowe-Power · 5 years ago
- f07d506 ext: Upgrade PyBind11 to version 2.2.1 by Jason Lowe-Power · 5 years ago
- 3f64b37 x86: Use operand size 4 when it would be 2 for cmpxchg8b. by Gabe Black · 5 years ago
- a45289d scons, tests: Fix occasional linking error by Andreas Sandberg · 5 years ago
- ed371e0 scons, tests: Add support for GTest XML generation by Andreas Sandberg · 5 years ago
- bace877 scons: Make sure GTests have the right environment variables by Andreas Sandberg · 5 years ago
- f6486a1 arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with. by Gabe Black · 5 years ago
- 93a168c cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst. by Gabe Black · 5 years ago
- 36d5e89 x86: Rework how "split" loads/stores are handled. by Gabe Black · 5 years ago
- a8f82f5 base: Add endianness conversion functions for std::array types. by Gabe Black · 5 years ago
- 5a4b143 tests: Turn fbtest into a gtest and move it to src/base. by Gabe Black · 5 years ago
- c849dd8 tests: Move the cprintftest unit test into src/base. by Gabe Black · 5 years ago
- 260c23f tests: Convert the cprintf unit test into a gtest. by Gabe Black · 5 years ago
- 4e5f5e6 tests: Move the trietest unit test into base. by Gabe Black · 5 years ago
- b031ded tests: Plumb dumps of the test trie into the gtest macros. by Gabe Black · 5 years ago
- 3297cd0 tests: Convert the trie unit test into a gtest. by Gabe Black · 5 years ago
- 364a80f tests: Add an implementation of the Logger interface for use gtests. by Gabe Black · 5 years ago
- 211124a misc: Rework the logging functions. by Gabe Black · 5 years ago
- a51576e config: Fix need to set ISA of switch cpus. by Austin Harris · 5 years ago
- 5b17040 arm: Change access permission in TPIDRURO and TPIDRURW by Giacomo Travaglini · 5 years ago
- bd7eadb x86,misc: add additional info on faulting X86 instruction, fetched PC by Matt Sinclair · 5 years ago
- 66a55ce tests: Accept SourceFilters as sources for GTest. by Gabe Black · 5 years ago
- 08fc1d5 tests: Add a pseudo target to run all the unit tests for build/variant. by Gabe Black · 5 years ago
- 12e646e arch-riscv: Move compressed ops out of ISA by Alec Roelke · 5 years ago
- 7f163ca x86: Split apart x87's FSW and TOP, and add a missing break. by Gabe Black · 5 years ago
- cba3719 misc: Update MAINTAINERS with learning-gem5 tag by Jason Lowe-Power · 5 years ago
- 7eb8d00 base: Split out the pixel class in framebuffer.(cc|hh). by Gabe Black · 5 years ago
- 3017314 base: Handle zero fill in cprintf when printing floats. by Gabe Black · 5 years ago
- 6e2829f tests: Fix the source file for the cprintftime test. by Gabe Black · 5 years ago
- 71accb5 scons: Several fixes having to do with tags and sets. by Gabe Black · 5 years ago
- 0b11c2e scons: Track and reuse object nodes for a given source file. by Gabe Black · 5 years ago
- 855660f x86: LOOP's operand size defaults to 64 bits in 64 bit mode. by Gabe Black · 5 years ago
- f19bb4e learning-gem5: Fix missing misc.hh in hello_object.cc by Hanhwi Jang · 5 years ago
- 0c0ccad arm: Add support for the dc {civac, cvac, cvau, ivac} instr by Nikos Nikoleris · 6 years ago
- eeb36e5 arm: Add support for the mcr dc{ic,i,c}mvac, dccmvau instructions by Nikos Nikoleris · 6 years ago
- b9edb35 mem-ruby: Prevent ruby from crashing on CMOs by Nikos Nikoleris · 5 years ago
- 7d70967 arm: Add CMO support for Non-Cacheable memory by Nikos Nikoleris · 6 years ago
- 099cb03 cpu: Add support for CMOs in the cpu models by Nikos Nikoleris · 6 years ago
- 3deff78 mem: Ignore clean requests in the abstract memory by Nikos Nikoleris · 6 years ago
