commit 05a7a7788fcbb05171285944e13c350973009a15
author Haojian Zhuang <haojian.zhuang@linaro.org> Mon Feb 10 18:05:25 2014 +0800
committer Andrey Konovalov <andrey.konovalov@linaro.org> Wed Apr 16 23:52:22 2014 +0400
tree 811ede6a4f3bd32aafdf91653716f386dae04bab
parent 3026427c42e0ac55403950402e1f43e98a5380de

ARM: dts: correct L2 register address of Hi3620

Correct the register address of L2 controller in Hi3620 DTS file.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

arch/arm/boot/dts/hi3620.dtsi

diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi
index c227a22..6836795 100644
--- a/arch/arm/boot/dts/hi3620.dtsi
+++ b/arch/arm/boot/dts/hi3620.dtsi
@@ -73,7 +73,7 @@
 
 		L2: l2-cache {
 			compatible = "arm,pl310-cache";
-			reg = <0xfc10000 0x100000>;
+			reg = <0x100000 0x100000>;
 			interrupts = <0 15 4>;
 			cache-unified;
 			cache-level = <2>;