| /* |
| * ARM Ltd. Fast Models |
| * |
| * Versatile Express (VE) system model |
| * ARMCortexA15x2CT |
| * |
| * RTSM_VE_Cortex_A15x2.lisa |
| */ |
| |
| /dts-v1/; |
| |
| / { |
| model = "RTSM_VE_CortexA15x2"; |
| arm,vexpress,site = <0xf>; |
| compatible = "arm,rtsm_ve,cortex_a15x2", "arm,vexpress"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| chosen { }; |
| |
| aliases { |
| serial0 = &v2m_serial0; |
| serial1 = &v2m_serial1; |
| serial2 = &v2m_serial2; |
| serial3 = &v2m_serial3; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a15"; |
| reg = <0>; |
| }; |
| |
| cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a15"; |
| reg = <1>; |
| }; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| reg = <0 0x80000000 0 0x80000000>; |
| }; |
| |
| gic: interrupt-controller@2c001000 { |
| compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; |
| #interrupt-cells = <3>; |
| #address-cells = <0>; |
| interrupt-controller; |
| reg = <0 0x2c001000 0 0x1000>, |
| <0 0x2c002000 0 0x1000>, |
| <0 0x2c004000 0 0x2000>, |
| <0 0x2c006000 0 0x2000>; |
| interrupts = <1 9 0xf04>; |
| }; |
| |
| timer { |
| compatible = "arm,armv7-timer"; |
| interrupts = <1 13 0xf08>, |
| <1 14 0xf08>, |
| <1 11 0xf08>, |
| <1 10 0xf08>; |
| }; |
| |
| dcc { |
| compatible = "arm,vexpress,config-bus"; |
| arm,vexpress,config-bridge = <&v2m_sysreg>; |
| |
| osc@0 { |
| /* ACLK clock to the AXI master port on the test chip */ |
| compatible = "arm,vexpress-osc"; |
| arm,vexpress-sysreg,func = <1 0>; |
| freq-range = <30000000 50000000>; |
| #clock-cells = <0>; |
| clock-output-names = "extsaxiclk"; |
| }; |
| |
| oscclk1: osc@1 { |
| /* Reference clock for the CLCD */ |
| compatible = "arm,vexpress-osc"; |
| arm,vexpress-sysreg,func = <1 1>; |
| freq-range = <10000000 80000000>; |
| #clock-cells = <0>; |
| clock-output-names = "clcdclk"; |
| }; |
| |
| smbclk: oscclk2: osc@2 { |
| /* Reference clock for the test chip internal PLLs */ |
| compatible = "arm,vexpress-osc"; |
| arm,vexpress-sysreg,func = <1 2>; |
| freq-range = <33000000 100000000>; |
| #clock-cells = <0>; |
| clock-output-names = "tcrefclk"; |
| }; |
| }; |
| |
| smb { |
| compatible = "simple-bus"; |
| |
| #address-cells = <2>; |
| #size-cells = <1>; |
| ranges = <0 0 0 0x08000000 0x04000000>, |
| <1 0 0 0x14000000 0x04000000>, |
| <2 0 0 0x18000000 0x04000000>, |
| <3 0 0 0x1c000000 0x04000000>, |
| <4 0 0 0x0c000000 0x04000000>, |
| <5 0 0 0x10000000 0x04000000>; |
| |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 63>; |
| interrupt-map = <0 0 0 &gic 0 0 4>, |
| <0 0 1 &gic 0 1 4>, |
| <0 0 2 &gic 0 2 4>, |
| <0 0 3 &gic 0 3 4>, |
| <0 0 4 &gic 0 4 4>, |
| <0 0 5 &gic 0 5 4>, |
| <0 0 6 &gic 0 6 4>, |
| <0 0 7 &gic 0 7 4>, |
| <0 0 8 &gic 0 8 4>, |
| <0 0 9 &gic 0 9 4>, |
| <0 0 10 &gic 0 10 4>, |
| <0 0 11 &gic 0 11 4>, |
| <0 0 12 &gic 0 12 4>, |
| <0 0 13 &gic 0 13 4>, |
| <0 0 14 &gic 0 14 4>, |
| <0 0 15 &gic 0 15 4>, |
| <0 0 16 &gic 0 16 4>, |
| <0 0 17 &gic 0 17 4>, |
| <0 0 18 &gic 0 18 4>, |
| <0 0 19 &gic 0 19 4>, |
| <0 0 20 &gic 0 20 4>, |
| <0 0 21 &gic 0 21 4>, |
| <0 0 22 &gic 0 22 4>, |
| <0 0 23 &gic 0 23 4>, |
| <0 0 24 &gic 0 24 4>, |
| <0 0 25 &gic 0 25 4>, |
| <0 0 26 &gic 0 26 4>, |
| <0 0 27 &gic 0 27 4>, |
| <0 0 28 &gic 0 28 4>, |
| <0 0 29 &gic 0 29 4>, |
| <0 0 30 &gic 0 30 4>, |
| <0 0 31 &gic 0 31 4>, |
| <0 0 32 &gic 0 32 4>, |
| <0 0 33 &gic 0 33 4>, |
| <0 0 34 &gic 0 34 4>, |
| <0 0 35 &gic 0 35 4>, |
| <0 0 36 &gic 0 36 4>, |
| <0 0 37 &gic 0 37 4>, |
| <0 0 38 &gic 0 38 4>, |
| <0 0 39 &gic 0 39 4>, |
| <0 0 40 &gic 0 40 4>, |
| <0 0 41 &gic 0 41 4>, |
| <0 0 42 &gic 0 42 4>; |
| |
| /include/ "rtsm_ve-motherboard.dtsi" |
| }; |
| }; |
| |
| /include/ "clcd-panels.dtsi" |