commit 1e847a47af8d885e84cd278e037677677b7bde74
author Zhangfei Gao <zhangfei.gao@linaro.org> Fri Apr 11 20:46:52 2014 +0800
committer Andrey Konovalov <andrey.konovalov@linaro.org> Wed Apr 16 23:52:33 2014 +0400
tree 6105c58a33a52fe377cef7aaaa5a1597bde4cd93
parent 2c2d3514946fd44ad37c3f5639115ee3c405ba05

ARM: dts: hip04: enable only 1 core

workaround

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>

arch/arm/boot/dts/hip04.dtsi

diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi
index df10aad..5b7e319 100644
--- a/arch/arm/boot/dts/hip04.dtsi
+++ b/arch/arm/boot/dts/hip04.dtsi
@@ -26,42 +26,11 @@
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu-map {
-			cluster0 {
-				core0 {
-					cpu = <&CPU0>;
-				};
-				core1 {
-					cpu = <&CPU1>;
-				};
-				core2 {
-					cpu = <&CPU2>;
-				};
-				core3 {
-					cpu = <&CPU3>;
-				};
-			};
-		};
-		CPU0: cpu@0 {
+		cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <0>;
 		};
-		CPU1: cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a15";
-			reg = <1>;
-		};
-		CPU2: cpu@2 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a15";
-			reg = <2>;
-		};
-		CPU3: cpu@3 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a15";
-			reg = <3>;
-		};
 	};
 
 	soc {
@@ -74,7 +43,7 @@
 		ranges = <0 0 0xe0000000 0x10000000>;
 
 		gic: interrupt-controller@c01000 {
-			compatible = "hisilicon,hip04-gic";
+			compatible = "arm,cortex-a15-gic";
 			#interrupt-cells = <3>;
 			#address-cells = <0>;
 			interrupt-controller;