| * Samsung Exynos4 Clock Controller | |
| The Exynos4 clock controller generates and supplies clock to various controllers | |
| within the Exynos4 SoC. The clock binding described here is applicable to all | |
| SoC's in the Exynos4 family. | |
| Required Properties: | |
| - compatible: should be one of the following. | |
| - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC. | |
| - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC. | |
| - reg: physical base address of the controller and length of memory mapped | |
| region. | |
| - #clock-cells: should be 1. | |
| The following is the list of clocks generated by the controller. Each clock is | |
| assigned an identifier and client nodes use this identifier to specify the | |
| clock which they consume. Some of the clocks are available only on a particular | |
| Exynos4 SoC and this is specified where applicable. | |
| [Core Clocks] | |
| Clock ID SoC (if specific) | |
| ----------------------------------------------- | |
| xxti 1 | |
| xusbxti 2 | |
| fin_pll 3 | |
| fout_apll 4 | |
| fout_mpll 5 | |
| fout_epll 6 | |
| fout_vpll 7 | |
| sclk_apll 8 | |
| sclk_mpll 9 | |
| sclk_epll 10 | |
| sclk_vpll 11 | |
| arm_clk 12 | |
| aclk200 13 | |
| aclk100 14 | |
| aclk160 15 | |
| aclk133 16 | |
| mout_mpll_user_t 17 Exynos4x12 | |
| mout_mpll_user_c 18 Exynos4x12 | |
| mout_core 19 | |
| mout_apll 20 | |
| [Clock Gate for Special Clocks] | |
| Clock ID SoC (if specific) | |
| ----------------------------------------------- | |
| sclk_fimc0 128 | |
| sclk_fimc1 129 | |
| sclk_fimc2 130 | |
| sclk_fimc3 131 | |
| sclk_cam0 132 | |
| sclk_cam1 133 | |
| sclk_csis0 134 | |
| sclk_csis1 135 | |
| sclk_hdmi 136 | |
| sclk_mixer 137 | |
| sclk_dac 138 | |
| sclk_pixel 139 | |
| sclk_fimd0 140 | |
| sclk_mdnie0 141 Exynos4412 | |
| sclk_mdnie_pwm0 12 142 Exynos4412 | |
| sclk_mipi0 143 | |
| sclk_audio0 144 | |
| sclk_mmc0 145 | |
| sclk_mmc1 146 | |
| sclk_mmc2 147 | |
| sclk_mmc3 148 | |
| sclk_mmc4 149 | |
| sclk_sata 150 Exynos4210 | |
| sclk_uart0 151 | |
| sclk_uart1 152 | |
| sclk_uart2 153 | |
| sclk_uart3 154 | |
| sclk_uart4 155 | |
| sclk_audio1 156 | |
| sclk_audio2 157 | |
| sclk_spdif 158 | |
| sclk_spi0 159 | |
| sclk_spi1 160 | |
| sclk_spi2 161 | |
| sclk_slimbus 162 | |
| sclk_fimd1 163 Exynos4210 | |
| sclk_mipi1 164 Exynos4210 | |
| sclk_pcm1 165 | |
| sclk_pcm2 166 | |
| sclk_i2s1 167 | |
| sclk_i2s2 168 | |
| sclk_mipihsi 169 Exynos4412 | |
| sclk_mfc 170 | |
| sclk_pcm0 171 | |
| sclk_g3d 172 | |
| sclk_pwm_isp 173 Exynos4x12 | |
| sclk_spi0_isp 174 Exynos4x12 | |
| sclk_spi1_isp 175 Exynos4x12 | |
| sclk_uart_isp 176 Exynos4x12 | |
| sclk_fimg2d 177 | |
| [Peripheral Clock Gates] | |
| Clock ID SoC (if specific) | |
| ----------------------------------------------- | |
| fimc0 256 | |
| fimc1 257 | |
| fimc2 258 | |
| fimc3 259 | |
| csis0 260 | |
| csis1 261 | |
| jpeg 262 | |
| smmu_fimc0 263 | |
| smmu_fimc1 264 | |
| smmu_fimc2 265 | |
| smmu_fimc3 266 | |
| smmu_jpeg 267 | |
| vp 268 | |
| mixer 269 | |
| tvenc 270 Exynos4210 | |
| hdmi 271 | |
| smmu_tv 272 | |
| mfc 273 | |
| smmu_mfcl 274 | |
| smmu_mfcr 275 | |
| g3d 276 | |
| g2d 277 | |
| rotator 278 Exynos4210 | |
| mdma 279 Exynos4210 | |
| smmu_g2d 280 Exynos4210 | |
| smmu_rotator 281 Exynos4210 | |
| smmu_mdma 282 Exynos4210 | |
| fimd0 283 | |
| mie0 284 | |
| mdnie0 285 Exynos4412 | |
| dsim0 286 | |
| smmu_fimd0 287 | |
| fimd1 288 Exynos4210 | |
| mie1 289 Exynos4210 | |
| dsim1 290 Exynos4210 | |
| smmu_fimd1 291 Exynos4210 | |
| pdma0 292 | |
| pdma1 293 | |
| pcie_phy 294 | |
| sata_phy 295 Exynos4210 | |
| tsi 296 | |
| sdmmc0 297 | |
| sdmmc1 298 | |
| sdmmc2 299 | |
| sdmmc3 300 | |
| sdmmc4 301 | |
| sata 302 Exynos4210 | |
| sromc 303 | |
| usb_host 304 | |
| usb_device 305 | |
| pcie 306 | |
| onenand 307 | |
| nfcon 308 | |
| smmu_pcie 309 | |
| gps 310 | |
| smmu_gps 311 | |
| uart0 312 | |
| uart1 313 | |
| uart2 314 | |
| uart3 315 | |
| uart4 316 | |
| i2c0 317 | |
| i2c1 318 | |
| i2c2 319 | |
| i2c3 320 | |
| i2c4 321 | |
| i2c5 322 | |
| i2c6 323 | |
| i2c7 324 | |
| i2c_hdmi 325 | |
| tsadc 326 | |
| spi0 327 | |
| spi1 328 | |
| spi2 329 | |
| i2s1 330 | |
| i2s2 331 | |
| pcm0 332 | |
| i2s0 333 | |
| pcm1 334 | |
| pcm2 335 | |
| pwm 336 | |
| slimbus 337 | |
| spdif 338 | |
| ac97 339 | |
| modemif 340 | |
| chipid 341 | |
| sysreg 342 | |
| hdmi_cec 343 | |
| mct 344 | |
| wdt 345 | |
| rtc 346 | |
| keyif 347 | |
| audss 348 | |
| mipi_hsi 349 Exynos4210 | |
| mdma2 350 Exynos4210 | |
| pixelasyncm0 351 | |
| pixelasyncm1 352 | |
| fimc_lite0 353 Exynos4x12 | |
| fimc_lite1 354 Exynos4x12 | |
| ppmuispx 355 Exynos4x12 | |
| ppmuispmx 356 Exynos4x12 | |
| fimc_isp 357 Exynos4x12 | |
| fimc_drc 358 Exynos4x12 | |
| fimc_fd 359 Exynos4x12 | |
| mcuisp 360 Exynos4x12 | |
| gicisp 361 Exynos4x12 | |
| smmu_isp 362 Exynos4x12 | |
| smmu_drc 363 Exynos4x12 | |
| smmu_fd 364 Exynos4x12 | |
| smmu_lite0 365 Exynos4x12 | |
| smmu_lite1 366 Exynos4x12 | |
| mcuctl_isp 367 Exynos4x12 | |
| mpwm_isp 368 Exynos4x12 | |
| i2c0_isp 369 Exynos4x12 | |
| i2c1_isp 370 Exynos4x12 | |
| mtcadc_isp 371 Exynos4x12 | |
| pwm_isp 372 Exynos4x12 | |
| wdt_isp 373 Exynos4x12 | |
| uart_isp 374 Exynos4x12 | |
| asyncaxim 375 Exynos4x12 | |
| smmu_ispcx 376 Exynos4x12 | |
| spi0_isp 377 Exynos4x12 | |
| spi1_isp 378 Exynos4x12 | |
| pwm_isp_sclk 379 Exynos4x12 | |
| spi0_isp_sclk 380 Exynos4x12 | |
| spi1_isp_sclk 381 Exynos4x12 | |
| uart_isp_sclk 382 Exynos4x12 | |
| tmu_apbif 383 | |
| [Mux Clocks] | |
| Clock ID SoC (if specific) | |
| ----------------------------------------------- | |
| mout_fimc0 384 | |
| mout_fimc1 385 | |
| mout_fimc2 386 | |
| mout_fimc3 387 | |
| mout_cam0 388 | |
| mout_cam1 389 | |
| mout_csis0 390 | |
| mout_csis1 391 | |
| mout_g3d0 392 | |
| mout_g3d1 393 | |
| mout_g3d 394 | |
| aclk400_mcuisp 395 Exynos4x12 | |
| [Div Clocks] | |
| Clock ID SoC (if specific) | |
| ----------------------------------------------- | |
| div_isp0 450 Exynos4x12 | |
| div_isp1 451 Exynos4x12 | |
| div_mcuisp0 452 Exynos4x12 | |
| div_mcuisp1 453 Exynos4x12 | |
| div_aclk200 454 Exynos4x12 | |
| div_aclk400_mcuisp 455 Exynos4x12 | |
| Example 1: An example of a clock controller node is listed below. | |
| clock: clock-controller@0x10030000 { | |
| compatible = "samsung,exynos4210-clock"; | |
| reg = <0x10030000 0x20000>; | |
| #clock-cells = <1>; | |
| }; | |
| Example 2: UART controller node that consumes the clock generated by the clock | |
| controller. Refer to the standard clock bindings for information | |
| about 'clocks' and 'clock-names' property. | |
| serial@13820000 { | |
| compatible = "samsung,exynos4210-uart"; | |
| reg = <0x13820000 0x100>; | |
| interrupts = <0 54 0>; | |
| clocks = <&clock 314>, <&clock 153>; | |
| clock-names = "uart", "clk_uart_baud0"; | |
| }; |