| * Freescale MPIC timers | |
| Required properties: | |
| - compatible: "fsl,mpic-global-timer" | |
| - reg : Contains two regions. The first is the main timer register bank | |
| (GTCCRxx, GTBCRxx, GTVPRxx, GTDRxx). The second is the timer control | |
| register (TCRx) for the group. | |
| - fsl,available-ranges: use <start count> style section to define which | |
| timer interrupts can be used. This property is optional; without this, | |
| all timers within the group can be used. | |
| - interrupts: one interrupt per timer in the group, in order, starting | |
| with timer zero. If timer-available-ranges is present, only the | |
| interrupts that correspond to available timers shall be present. | |
| Example: | |
| /* Note that this requires #interrupt-cells to be 4 */ | |
| timer0: timer@41100 { | |
| compatible = "fsl,mpic-global-timer"; | |
| reg = <0x41100 0x100 0x41300 4>; | |
| /* Another AMP partition is using timers 0 and 1 */ | |
| fsl,available-ranges = <2 2>; | |
| interrupts = <2 0 3 0 | |
| 3 0 3 0>; | |
| }; | |
| timer1: timer@42100 { | |
| compatible = "fsl,mpic-global-timer"; | |
| reg = <0x42100 0x100 0x42300 4>; | |
| interrupts = <4 0 3 0 | |
| 5 0 3 0 | |
| 6 0 3 0 | |
| 7 0 3 0>; | |
| }; |