exynos: driver raw read and write endian fix
Need to use endian neutral functions to read/write LE h/w registers. I.e
instead of __raw_read[lw] and _raw_write[lw] functions code need to use
read[lw]_relaxed and write[lw]_relaxed functions. If the first just
read/write register with memory barrier, the second will byteswap it if host
operates in BE mode.
This patch covers drivers used by arndale board where all changes are trivial,
sed like replacement of __raw_xxx functions with xxx_relaxed variant.
Literally this sed program was used to make the change:
s|__raw_readl|readl_relaxed|g
s|__raw_writel|writel_relaxed|g
s|__raw_readw|readw_relaxed|g
s|__raw_writew|writew_relaxed|g
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 92034a7..5f7077d 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -274,7 +274,7 @@
void exynos4_restart(enum reboot_mode mode, const char *cmd)
{
- __raw_writel(0x1, S5P_SWRESET);
+ writel_relaxed(0x1, S5P_SWRESET);
}
void exynos5_restart(enum reboot_mode mode, const char *cmd)
@@ -291,15 +291,15 @@
np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
addr = of_iomap(np, 0) + 0xbc;
- status = __raw_readl(addr);
+ status = readl_relaxed(addr);
addr = of_iomap(np, 0) + 0xcc;
- val = __raw_readl(addr);
+ val = readl_relaxed(addr);
val = (val & 0xffff0000) | (status & 0xffff);
}
- __raw_writel(val, addr);
+ writel_relaxed(val, addr);
}
static struct platform_device exynos_cpuidle = {
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index f57cb91..45aef49 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -87,7 +87,7 @@
/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
static void exynos4_set_wakeupmask(void)
{
- __raw_writel(0x0000ff3e, S5P_WAKEUP_MASK);
+ writel_relaxed(0x0000ff3e, S5P_WAKEUP_MASK);
}
static unsigned int g_pwr_ctrl, g_diag_reg;
@@ -127,15 +127,15 @@
/* Set value of power down register for aftr mode */
exynos_sys_powerdown_conf(SYS_AFTR);
- __raw_writel(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
- __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
+ writel_relaxed(virt_to_phys(s3c_cpu_resume), REG_DIRECTGO_ADDR);
+ writel_relaxed(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
save_cpu_arch_register();
/* Setting Central Sequence Register for power down mode */
- tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ tmp = readl_relaxed(S5P_CENTRAL_SEQ_CONFIGURATION);
tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
- __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+ writel_relaxed(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
cpu_pm_enter();
cpu_suspend(0, idle_finisher);
@@ -154,14 +154,14 @@
* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
* in this situation.
*/
- tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ tmp = readl_relaxed(S5P_CENTRAL_SEQ_CONFIGURATION);
if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
tmp |= S5P_CENTRAL_LOWPWR_CFG;
- __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+ writel_relaxed(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
}
/* Clear wakeup state register */
- __raw_writel(0x0, S5P_WAKEUP_STAT);
+ writel_relaxed(0x0, S5P_WAKEUP_STAT);
return index;
}
@@ -198,7 +198,7 @@
PWR_CTRL1_USE_CORE0_WFE | \
PWR_CTRL1_USE_CORE1_WFI | \
PWR_CTRL1_USE_CORE0_WFI;
- __raw_writel(tmp, EXYNOS5_PWR_CTRL1);
+ writel_relaxed(tmp, EXYNOS5_PWR_CTRL1);
/*
* Enable arm clock up (on exiting idle). Set arm divider
@@ -211,7 +211,7 @@
PWR_CTRL2_DUR_STANDBY1_VAL | \
PWR_CTRL2_CORE2_UP_RATIO | \
PWR_CTRL2_CORE1_UP_RATIO;
- __raw_writel(tmp, EXYNOS5_PWR_CTRL2);
+ writel_relaxed(tmp, EXYNOS5_PWR_CTRL2);
}
static int exynos_cpuidle_probe(struct platform_device *pdev)
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index 4711f29..e61df85 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -40,7 +40,7 @@
if (!soc_is_exynos5420())
boot_reg += 4 * cpu;
- __raw_writel(boot_addr, boot_reg);
+ writel_relaxed(boot_addr, boot_reg);
return 0;
}
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 03cdcd3..5a96c1b 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -96,7 +96,7 @@
/* make cpu1 to be turned off at next WFI command */
if (cpu == 1)
- __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
+ writel_relaxed(0, S5P_ARM_CORE1_CONFIGURATION);
wfi();
diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h
index dc0697c..a12caa6 100644
--- a/arch/arm/mach-exynos/include/mach/pm-core.h
+++ b/arch/arm/mach-exynos/include/mach/pm-core.h
@@ -37,8 +37,8 @@
static inline void s3c_pm_arch_prepare_irqs(void)
{
- __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
- __raw_writel(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
+ writel_relaxed(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
+ writel_relaxed(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
}
static inline void s3c_pm_arch_stop_clocks(void)
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 98d862c..9e6fb03 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -109,14 +109,14 @@
*/
write_pen_release(phys_cpu);
- if (!(__raw_readl(S5P_ARM_CORE1_STATUS + (0x80 * cpu) - 0x80) & S5P_CORE_LOCAL_PWR_EN)) {
- __raw_writel(S5P_CORE_LOCAL_PWR_EN,
+ if (!(readl_relaxed(S5P_ARM_CORE1_STATUS + (0x80 * cpu) - 0x80) & S5P_CORE_LOCAL_PWR_EN)) {
+ writel_relaxed(S5P_CORE_LOCAL_PWR_EN,
S5P_ARM_CORE1_CONFIGURATION + (0x80 * cpu) - 0x80);
timeout = 10;
/* wait max 10 ms until cpu1 is on */
- while ((__raw_readl(S5P_ARM_CORE1_STATUS + (0x80 * cpu) - 0x80)
+ while ((readl_relaxed(S5P_ARM_CORE1_STATUS + (0x80 * cpu) - 0x80)
& S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
if (timeout-- == 0)
break;
@@ -149,7 +149,7 @@
* and fall back to boot register if it fails.
*/
if (call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr))
- __raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
+ writel_relaxed(boot_addr, cpu_boot_reg(phys_cpu));
call_firmware_op(cpu_boot, phys_cpu);
@@ -224,7 +224,7 @@
boot_addr = virt_to_phys(exynos4_secondary_startup);
if (call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr))
- __raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
+ writel_relaxed(boot_addr, cpu_boot_reg(phys_cpu));
}
}
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index e00025b..f429e34 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -130,19 +130,19 @@
} else {
s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
/* Disable USE_RETENTION of JPEG_MEM_OPTION */
- tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
+ tmp = readl_relaxed(EXYNOS5_JPEG_MEM_OPTION);
tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
- __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
+ writel_relaxed(tmp, EXYNOS5_JPEG_MEM_OPTION);
}
/* Set value of power down register for sleep mode */
exynos_sys_powerdown_conf(SYS_SLEEP);
- __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
+ writel_relaxed(S5P_CHECK_SLEEP, S5P_INFORM1);
/* ensure at least INFORM0 has the resume address */
- __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
+ writel_relaxed(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
/* Before enter central sequence mode, clock src register have to set */
@@ -187,7 +187,7 @@
locktime = (3000 / pll_in_rate) * p_div;
lockcnt = locktime * 10000 / (10000 / pll_in_rate);
- __raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
+ writel_relaxed(lockcnt, EXYNOS4_EPLL_LOCK);
s3c_pm_do_restore_core(exynos4_epll_save,
ARRAY_SIZE(exynos4_epll_save));
@@ -205,7 +205,7 @@
locktime = 750;
lockcnt = locktime * 10000 / (10000 / pll_in_rate);
- __raw_writel(lockcnt, EXYNOS4_VPLL_LOCK);
+ writel_relaxed(lockcnt, EXYNOS4_VPLL_LOCK);
s3c_pm_do_restore_core(exynos4_vpll_save,
ARRAY_SIZE(exynos4_vpll_save));
@@ -216,13 +216,13 @@
do {
if (epll_wait) {
- pll_con = __raw_readl(EXYNOS4_EPLL_CON0);
+ pll_con = readl_relaxed(EXYNOS4_EPLL_CON0);
if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT))
epll_wait = 0;
}
if (vpll_wait) {
- pll_con = __raw_readl(EXYNOS4_VPLL_CON0);
+ pll_con = readl_relaxed(EXYNOS4_VPLL_CON0);
if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT))
vpll_wait = 0;
}
@@ -247,9 +247,9 @@
/* All wakeup disable */
- tmp = __raw_readl(S5P_WAKEUP_MASK);
+ tmp = readl_relaxed(S5P_WAKEUP_MASK);
tmp |= ((0xFF << 8) | (0x1F << 1));
- __raw_writel(tmp, S5P_WAKEUP_MASK);
+ writel_relaxed(tmp, S5P_WAKEUP_MASK);
if (!soc_is_exynos5250()) {
pll_base = clk_get(NULL, "xtal");
@@ -270,14 +270,14 @@
/* Setting Central Sequence Register for power down mode */
- tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ tmp = readl_relaxed(S5P_CENTRAL_SEQ_CONFIGURATION);
tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
- __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+ writel_relaxed(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
/* Setting SEQ_OPTION register */
tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
- __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
+ writel_relaxed(tmp, S5P_CENTRAL_SEQ_OPTION);
if (!soc_is_exynos5250()) {
/* Save Power control register */
@@ -304,12 +304,12 @@
* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
* in this situation.
*/
- tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ tmp = readl_relaxed(S5P_CENTRAL_SEQ_CONFIGURATION);
if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
tmp |= S5P_CENTRAL_LOWPWR_CFG;
- __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+ writel_relaxed(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
/* clear the wakeup state register */
- __raw_writel(0x0, S5P_WAKEUP_STAT);
+ writel_relaxed(0x0, S5P_WAKEUP_STAT);
/* No need to perform below restore code */
goto early_wakeup;
}
@@ -329,13 +329,13 @@
/* For release retention */
- __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
- __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
- __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
- __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
- __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
- __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
- __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
+ writel_relaxed((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
+ writel_relaxed((1 << 28), S5P_PAD_RET_GPIO_OPTION);
+ writel_relaxed((1 << 28), S5P_PAD_RET_UART_OPTION);
+ writel_relaxed((1 << 28), S5P_PAD_RET_MMCA_OPTION);
+ writel_relaxed((1 << 28), S5P_PAD_RET_MMCB_OPTION);
+ writel_relaxed((1 << 28), S5P_PAD_RET_EBIA_OPTION);
+ writel_relaxed((1 << 28), S5P_PAD_RET_EBIB_OPTION);
if (soc_is_exynos5250())
s3c_pm_do_restore(exynos5_sys_save,
@@ -354,7 +354,7 @@
early_wakeup:
/* Clear SLEEP mode set in INFORM1 */
- __raw_writel(0x0, S5P_INFORM1);
+ writel_relaxed(0x0, S5P_INFORM1);
return;
}
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index 8fd2488..10b14d0 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -47,12 +47,12 @@
base = pd->base;
pwr = power_on ? S5P_INT_LOCAL_PWR_EN : 0;
- __raw_writel(pwr, base);
+ writel_relaxed(pwr, base);
/* Wait max 1ms */
timeout = 10;
- while ((__raw_readl(base + 0x4) & S5P_INT_LOCAL_PWR_EN) != pwr) {
+ while ((readl_relaxed(base + 0x4) & S5P_INT_LOCAL_PWR_EN) != pwr) {
if (!timeout) {
op = (power_on) ? "enable" : "disable";
pr_err("Power domain %s %s failed\n", domain->name, op);
@@ -174,7 +174,7 @@
platform_set_drvdata(pdev, pd);
- on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN;
+ on = readl_relaxed(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN;
pm_genpd_init(&pd->pd, NULL, !on);
}
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 05c7ce1..d667b15 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -347,27 +347,27 @@
* Enable both SC_FEEDBACK and SC_COUNTER
*/
for (i = 0 ; i < ARRAY_SIZE(exynos5_list_both_cnt_feed) ; i++) {
- tmp = __raw_readl(exynos5_list_both_cnt_feed[i]);
+ tmp = readl_relaxed(exynos5_list_both_cnt_feed[i]);
tmp |= (EXYNOS5_USE_SC_FEEDBACK |
EXYNOS5_USE_SC_COUNTER);
- __raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
+ writel_relaxed(tmp, exynos5_list_both_cnt_feed[i]);
}
/*
* SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable
*/
- tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION);
+ tmp = readl_relaxed(EXYNOS5_ARM_COMMON_OPTION);
tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
- __raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
+ writel_relaxed(tmp, EXYNOS5_ARM_COMMON_OPTION);
/*
* Disable WFI/WFE on XXX_OPTION
*/
for (i = 0 ; i < ARRAY_SIZE(exynos5_list_diable_wfi_wfe) ; i++) {
- tmp = __raw_readl(exynos5_list_diable_wfi_wfe[i]);
+ tmp = readl_relaxed(exynos5_list_diable_wfi_wfe[i]);
tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE |
EXYNOS5_OPTION_USE_STANDBYWFI);
- __raw_writel(tmp, exynos5_list_diable_wfi_wfe[i]);
+ writel_relaxed(tmp, exynos5_list_diable_wfi_wfe[i]);
}
}
@@ -379,12 +379,12 @@
exynos5_init_pmu();
for (i = 0; (exynos_pmu_config[i].reg != PMU_TABLE_END) ; i++)
- __raw_writel(exynos_pmu_config[i].val[mode],
+ writel_relaxed(exynos_pmu_config[i].val[mode],
exynos_pmu_config[i].reg);
if (soc_is_exynos4412()) {
for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++)
- __raw_writel(exynos4412_pmu_config[i].val[mode],
+ writel_relaxed(exynos4412_pmu_config[i].val[mode],
exynos4412_pmu_config[i].reg);
}
}
@@ -406,13 +406,13 @@
* When SYS_WDTRESET is set, watchdog timer reset request
* is ignored by power management unit.
*/
- value = __raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
+ value = readl_relaxed(EXYNOS5_AUTO_WDTRESET_DISABLE);
value &= ~EXYNOS5_SYS_WDTRESET;
- __raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
+ writel_relaxed(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
- value = __raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
+ value = readl_relaxed(EXYNOS5_MASK_WDTRESET_REQUEST);
value &= ~EXYNOS5_SYS_WDTRESET;
- __raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
+ writel_relaxed(value, EXYNOS5_MASK_WDTRESET_REQUEST);
exynos_pmu_config = exynos5250_pmu_config;
pr_info("EXYNOS5250 PMU Initialize\n");
diff --git a/arch/arm/plat-samsung/cpu.c b/arch/arm/plat-samsung/cpu.c
index 46b426e..699fce1 100644
--- a/arch/arm/plat-samsung/cpu.c
+++ b/arch/arm/plat-samsung/cpu.c
@@ -37,14 +37,14 @@
void __init s3c64xx_init_cpu(void)
{
- samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0x118);
+ samsung_cpu_id = readl_relaxed(S3C_VA_SYS + 0x118);
if (!samsung_cpu_id) {
/*
* S3C6400 has the ID register in a different place,
* and needs a write before it can be read.
*/
- __raw_writel(0x0, S3C_VA_SYS + 0xA1C);
- samsung_cpu_id = __raw_readl(S3C_VA_SYS + 0xA1C);
+ writel_relaxed(0x0, S3C_VA_SYS + 0xA1C);
+ samsung_cpu_id = readl_relaxed(S3C_VA_SYS + 0xA1C);
}
samsung_cpu_rev = 0;
@@ -52,6 +52,6 @@
void __init s5p_init_cpu(void __iomem *cpuid_addr)
{
- samsung_cpu_id = __raw_readl(cpuid_addr);
+ samsung_cpu_id = readl_relaxed(cpuid_addr);
samsung_cpu_rev = samsung_cpu_id & 0xFF;
}
diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c
index dd4c15d0..a178922 100644
--- a/arch/arm/plat-samsung/pm-gpio.c
+++ b/arch/arm/plat-samsung/pm-gpio.c
@@ -34,15 +34,15 @@
static void samsung_gpio_pm_1bit_save(struct samsung_gpio_chip *chip)
{
- chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
- chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
+ chip->pm_save[0] = readl_relaxed(chip->base + OFFS_CON);
+ chip->pm_save[1] = readl_relaxed(chip->base + OFFS_DAT);
}
static void samsung_gpio_pm_1bit_resume(struct samsung_gpio_chip *chip)
{
void __iomem *base = chip->base;
- u32 old_gpcon = __raw_readl(base + OFFS_CON);
- u32 old_gpdat = __raw_readl(base + OFFS_DAT);
+ u32 old_gpcon = readl_relaxed(base + OFFS_CON);
+ u32 old_gpdat = readl_relaxed(base + OFFS_DAT);
u32 gps_gpcon = chip->pm_save[0];
u32 gps_gpdat = chip->pm_save[1];
u32 gpcon;
@@ -53,12 +53,12 @@
/* first set all SFN bits to SFN */
gpcon = old_gpcon | gps_gpcon;
- __raw_writel(gpcon, base + OFFS_CON);
+ writel_relaxed(gpcon, base + OFFS_CON);
/* now set all the other bits */
- __raw_writel(gps_gpdat, base + OFFS_DAT);
- __raw_writel(gps_gpcon, base + OFFS_CON);
+ writel_relaxed(gps_gpdat, base + OFFS_DAT);
+ writel_relaxed(gps_gpcon, base + OFFS_CON);
S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
@@ -71,9 +71,9 @@
static void samsung_gpio_pm_2bit_save(struct samsung_gpio_chip *chip)
{
- chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON);
- chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT);
- chip->pm_save[2] = __raw_readl(chip->base + OFFS_UP);
+ chip->pm_save[0] = readl_relaxed(chip->base + OFFS_CON);
+ chip->pm_save[1] = readl_relaxed(chip->base + OFFS_DAT);
+ chip->pm_save[2] = readl_relaxed(chip->base + OFFS_UP);
}
/* Test whether the given masked+shifted bits of an GPIO configuration
@@ -128,8 +128,8 @@
static void samsung_gpio_pm_2bit_resume(struct samsung_gpio_chip *chip)
{
void __iomem *base = chip->base;
- u32 old_gpcon = __raw_readl(base + OFFS_CON);
- u32 old_gpdat = __raw_readl(base + OFFS_DAT);
+ u32 old_gpcon = readl_relaxed(base + OFFS_CON);
+ u32 old_gpdat = readl_relaxed(base + OFFS_DAT);
u32 gps_gpcon = chip->pm_save[0];
u32 gps_gpdat = chip->pm_save[1];
u32 gpcon, old, new, mask;
@@ -137,7 +137,7 @@
int nr;
/* restore GPIO pull-up settings */
- __raw_writel(chip->pm_save[2], base + OFFS_UP);
+ writel_relaxed(chip->pm_save[2], base + OFFS_UP);
/* Create a change_mask of all the items that need to have
* their CON value changed before their DAT value, so that
@@ -180,12 +180,12 @@
gpcon = old_gpcon & ~change_mask;
gpcon |= gps_gpcon & change_mask;
- __raw_writel(gpcon, base + OFFS_CON);
+ writel_relaxed(gpcon, base + OFFS_CON);
/* Now change any items that require DAT,CON */
- __raw_writel(gps_gpdat, base + OFFS_DAT);
- __raw_writel(gps_gpcon, base + OFFS_CON);
+ writel_relaxed(gps_gpdat, base + OFFS_DAT);
+ writel_relaxed(gps_gpcon, base + OFFS_CON);
S3C_PMDBG("%s: CON %08x => %08x, DAT %08x => %08x\n",
chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
@@ -200,12 +200,12 @@
|| defined(CONFIG_ARCH_EXYNOS)
static void samsung_gpio_pm_4bit_save(struct samsung_gpio_chip *chip)
{
- chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
- chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT);
- chip->pm_save[3] = __raw_readl(chip->base + OFFS_UP);
+ chip->pm_save[1] = readl_relaxed(chip->base + OFFS_CON);
+ chip->pm_save[2] = readl_relaxed(chip->base + OFFS_DAT);
+ chip->pm_save[3] = readl_relaxed(chip->base + OFFS_UP);
if (chip->chip.ngpio > 8)
- chip->pm_save[0] = __raw_readl(chip->base - 4);
+ chip->pm_save[0] = readl_relaxed(chip->base - 4);
}
static u32 samsung_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon)
@@ -250,7 +250,7 @@
static void samsung_gpio_pm_4bit_con(struct samsung_gpio_chip *chip, int index)
{
void __iomem *con = chip->base + (index * 4);
- u32 old_gpcon = __raw_readl(con);
+ u32 old_gpcon = readl_relaxed(con);
u32 gps_gpcon = chip->pm_save[index + 1];
u32 gpcon, mask;
@@ -259,47 +259,47 @@
gpcon = old_gpcon & ~mask;
gpcon |= gps_gpcon & mask;
- __raw_writel(gpcon, con);
+ writel_relaxed(gpcon, con);
}
static void samsung_gpio_pm_4bit_resume(struct samsung_gpio_chip *chip)
{
void __iomem *base = chip->base;
u32 old_gpcon[2];
- u32 old_gpdat = __raw_readl(base + OFFS_DAT);
+ u32 old_gpdat = readl_relaxed(base + OFFS_DAT);
u32 gps_gpdat = chip->pm_save[2];
/* First, modify the CON settings */
old_gpcon[0] = 0;
- old_gpcon[1] = __raw_readl(base + OFFS_CON);
+ old_gpcon[1] = readl_relaxed(base + OFFS_CON);
samsung_gpio_pm_4bit_con(chip, 0);
if (chip->chip.ngpio > 8) {
- old_gpcon[0] = __raw_readl(base - 4);
+ old_gpcon[0] = readl_relaxed(base - 4);
samsung_gpio_pm_4bit_con(chip, -1);
}
/* Now change the configurations that require DAT,CON */
- __raw_writel(chip->pm_save[2], base + OFFS_DAT);
- __raw_writel(chip->pm_save[1], base + OFFS_CON);
+ writel_relaxed(chip->pm_save[2], base + OFFS_DAT);
+ writel_relaxed(chip->pm_save[1], base + OFFS_CON);
if (chip->chip.ngpio > 8)
- __raw_writel(chip->pm_save[0], base - 4);
+ writel_relaxed(chip->pm_save[0], base - 4);
- __raw_writel(chip->pm_save[2], base + OFFS_DAT);
- __raw_writel(chip->pm_save[3], base + OFFS_UP);
+ writel_relaxed(chip->pm_save[2], base + OFFS_DAT);
+ writel_relaxed(chip->pm_save[3], base + OFFS_UP);
if (chip->chip.ngpio > 8) {
S3C_PMDBG("%s: CON4 %08x,%08x => %08x,%08x, DAT %08x => %08x\n",
chip->chip.label, old_gpcon[0], old_gpcon[1],
- __raw_readl(base - 4),
- __raw_readl(base + OFFS_CON),
+ readl_relaxed(base - 4),
+ readl_relaxed(base + OFFS_CON),
old_gpdat, gps_gpdat);
} else
S3C_PMDBG("%s: CON4 %08x => %08x, DAT %08x => %08x\n",
chip->chip.label, old_gpcon[1],
- __raw_readl(base + OFFS_CON),
+ readl_relaxed(base + OFFS_CON),
old_gpdat, gps_gpdat);
}
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index e5b0f2c..4a9223b 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -88,14 +88,14 @@
{
void __iomem *regs = S3C_VA_UARTx(uart);
- save->ulcon = __raw_readl(regs + S3C2410_ULCON);
- save->ucon = __raw_readl(regs + S3C2410_UCON);
- save->ufcon = __raw_readl(regs + S3C2410_UFCON);
- save->umcon = __raw_readl(regs + S3C2410_UMCON);
- save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);
+ save->ulcon = readl_relaxed(regs + S3C2410_ULCON);
+ save->ucon = readl_relaxed(regs + S3C2410_UCON);
+ save->ufcon = readl_relaxed(regs + S3C2410_UFCON);
+ save->umcon = readl_relaxed(regs + S3C2410_UMCON);
+ save->ubrdiv = readl_relaxed(regs + S3C2410_UBRDIV);
if (pm_uart_udivslot)
- save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT);
+ save->udivslot = readl_relaxed(regs + S3C2443_DIVSLOT);
S3C_PMDBG("UART[%d]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
uart, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
@@ -112,14 +112,14 @@
s3c_pm_arch_update_uart(regs, save);
- __raw_writel(save->ulcon, regs + S3C2410_ULCON);
- __raw_writel(save->ucon, regs + S3C2410_UCON);
- __raw_writel(save->ufcon, regs + S3C2410_UFCON);
- __raw_writel(save->umcon, regs + S3C2410_UMCON);
- __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV);
+ writel_relaxed(save->ulcon, regs + S3C2410_ULCON);
+ writel_relaxed(save->ucon, regs + S3C2410_UCON);
+ writel_relaxed(save->ufcon, regs + S3C2410_UFCON);
+ writel_relaxed(save->umcon, regs + S3C2410_UMCON);
+ writel_relaxed(save->ubrdiv, regs + S3C2410_UBRDIV);
if (pm_uart_udivslot)
- __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT);
+ writel_relaxed(save->udivslot, regs + S3C2443_DIVSLOT);
}
static void s3c_pm_restore_uarts(void)
@@ -168,7 +168,7 @@
void s3c_pm_do_save(struct sleep_save *ptr, int count)
{
for (; count > 0; count--, ptr++) {
- ptr->val = __raw_readl(ptr->reg);
+ ptr->val = readl_relaxed(ptr->reg);
S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val);
}
}
@@ -188,9 +188,9 @@
{
for (; count > 0; count--, ptr++) {
printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
- ptr->reg, ptr->val, __raw_readl(ptr->reg));
+ ptr->reg, ptr->val, readl_relaxed(ptr->reg));
- __raw_writel(ptr->val, ptr->reg);
+ writel_relaxed(ptr->val, ptr->reg);
}
}
@@ -208,7 +208,7 @@
void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count)
{
for (; count > 0; count--, ptr++)
- __raw_writel(ptr->val, ptr->reg);
+ writel_relaxed(ptr->val, ptr->reg);
}
/* s3c2410_pm_show_resume_irqs
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 81e6d2f..cc64478 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -80,7 +80,7 @@
u32 mdiv, pdiv, sdiv, pll_con;
u64 fvco = parent_rate;
- pll_con = __raw_readl(pll->con_reg);
+ pll_con = readl_relaxed(pll->con_reg);
mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK;
pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK;
sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK;
@@ -117,19 +117,19 @@
return -EINVAL;
}
- tmp = __raw_readl(pll->con_reg);
+ tmp = readl_relaxed(pll->con_reg);
if (!(samsung_pll35xx_mp_change(rate, tmp))) {
/* If only s change, change just s value only*/
tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT);
tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT;
- __raw_writel(tmp, pll->con_reg);
+ writel_relaxed(tmp, pll->con_reg);
return 0;
}
/* Set PLL lock time. */
- __raw_writel(rate->pdiv * PLL35XX_LOCK_FACTOR,
+ writel_relaxed(rate->pdiv * PLL35XX_LOCK_FACTOR,
pll->lock_reg);
/* Change PLL PMS values */
@@ -139,12 +139,12 @@
tmp |= (rate->mdiv << PLL35XX_MDIV_SHIFT) |
(rate->pdiv << PLL35XX_PDIV_SHIFT) |
(rate->sdiv << PLL35XX_SDIV_SHIFT);
- __raw_writel(tmp, pll->con_reg);
+ writel_relaxed(tmp, pll->con_reg);
/* wait_lock_time */
do {
cpu_relax();
- tmp = __raw_readl(pll->con_reg);
+ tmp = readl_relaxed(pll->con_reg);
} while (!(tmp & (PLL35XX_LOCK_STAT_MASK
<< PLL35XX_LOCK_STAT_SHIFT)));
return 0;
@@ -184,8 +184,8 @@
s16 kdiv;
u64 fvco = parent_rate;
- pll_con0 = __raw_readl(pll->con_reg);
- pll_con1 = __raw_readl(pll->con_reg + 4);
+ pll_con0 = readl_relaxed(pll->con_reg);
+ pll_con1 = readl_relaxed(pll->con_reg + 4);
mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK;
pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK;
sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK;
@@ -225,20 +225,20 @@
return -EINVAL;
}
- pll_con0 = __raw_readl(pll->con_reg);
- pll_con1 = __raw_readl(pll->con_reg + 4);
+ pll_con0 = readl_relaxed(pll->con_reg);
+ pll_con1 = readl_relaxed(pll->con_reg + 4);
if (!(samsung_pll36xx_mpk_change(rate, pll_con0, pll_con1))) {
/* If only s change, change just s value only*/
pll_con0 &= ~(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT);
pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT);
- __raw_writel(pll_con0, pll->con_reg);
+ writel_relaxed(pll_con0, pll->con_reg);
return 0;
}
/* Set PLL lock time. */
- __raw_writel(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg);
+ writel_relaxed(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg);
/* Change PLL PMS values */
pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) |
@@ -247,16 +247,16 @@
pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) |
(rate->pdiv << PLL36XX_PDIV_SHIFT) |
(rate->sdiv << PLL36XX_SDIV_SHIFT);
- __raw_writel(pll_con0, pll->con_reg);
+ writel_relaxed(pll_con0, pll->con_reg);
pll_con1 &= ~(PLL36XX_KDIV_MASK << PLL36XX_KDIV_SHIFT);
pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT;
- __raw_writel(pll_con1, pll->con_reg + 4);
+ writel_relaxed(pll_con1, pll->con_reg + 4);
/* wait_lock_time */
do {
cpu_relax();
- tmp = __raw_readl(pll->con_reg);
+ tmp = readl_relaxed(pll->con_reg);
} while (!(tmp & (1 << PLL36XX_LOCK_STAT_SHIFT)));
return 0;
@@ -297,7 +297,7 @@
u32 mdiv, pdiv, sdiv, pll_con;
u64 fvco = parent_rate;
- pll_con = __raw_readl(pll->con_reg);
+ pll_con = readl_relaxed(pll->con_reg);
mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK;
pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK;
sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK;
@@ -340,14 +340,14 @@
return -EINVAL;
}
- con0 = __raw_readl(pll->con_reg);
- con1 = __raw_readl(pll->con_reg + 0x4);
+ con0 = readl_relaxed(pll->con_reg);
+ con1 = readl_relaxed(pll->con_reg + 0x4);
if (!(samsung_pll45xx_mp_change(con0, con1, rate))) {
/* If only s change, change just s value only*/
con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT);
con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT;
- __raw_writel(con0, pll->con_reg);
+ writel_relaxed(con0, pll->con_reg);
return 0;
}
@@ -361,29 +361,29 @@
(rate->sdiv << PLL45XX_SDIV_SHIFT);
/* Set PLL AFC value. */
- con1 = __raw_readl(pll->con_reg + 0x4);
+ con1 = readl_relaxed(pll->con_reg + 0x4);
con1 &= ~(PLL45XX_AFC_MASK << PLL45XX_AFC_SHIFT);
con1 |= (rate->afc << PLL45XX_AFC_SHIFT);
/* Set PLL lock time. */
switch (pll->type) {
case pll_4502:
- __raw_writel(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg);
+ writel_relaxed(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg);
break;
case pll_4508:
- __raw_writel(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg);
+ writel_relaxed(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg);
break;
default:
break;
}
/* Set new configuration. */
- __raw_writel(con1, pll->con_reg + 0x4);
- __raw_writel(con0, pll->con_reg);
+ writel_relaxed(con1, pll->con_reg + 0x4);
+ writel_relaxed(con0, pll->con_reg);
/* Wait for locking. */
start = ktime_get();
- while (!(__raw_readl(pll->con_reg) & PLL45XX_LOCKED)) {
+ while (!(readl_relaxed(pll->con_reg) & PLL45XX_LOCKED)) {
ktime_t delta = ktime_sub(ktime_get(), start);
if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) {
@@ -442,8 +442,8 @@
u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift;
u64 fvco = parent_rate;
- pll_con0 = __raw_readl(pll->con_reg);
- pll_con1 = __raw_readl(pll->con_reg + 4);
+ pll_con0 = readl_relaxed(pll->con_reg);
+ pll_con1 = readl_relaxed(pll->con_reg + 4);
mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
@@ -487,14 +487,14 @@
return -EINVAL;
}
- con0 = __raw_readl(pll->con_reg);
- con1 = __raw_readl(pll->con_reg + 0x4);
+ con0 = readl_relaxed(pll->con_reg);
+ con1 = readl_relaxed(pll->con_reg + 0x4);
if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) {
/* If only s change, change just s value only*/
con0 &= ~(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT;
- __raw_writel(con0, pll->con_reg);
+ writel_relaxed(con0, pll->con_reg);
return 0;
}
@@ -516,7 +516,7 @@
(rate->vsel << PLL46XX_VSEL_SHIFT);
/* Set PLL K, MFR and MRR values. */
- con1 = __raw_readl(pll->con_reg + 0x4);
+ con1 = readl_relaxed(pll->con_reg + 0x4);
con1 &= ~((PLL46XX_KDIV_MASK << PLL46XX_KDIV_SHIFT) |
(PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT) |
(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT));
@@ -525,13 +525,13 @@
(rate->mrr << PLL46XX_MRR_SHIFT);
/* Write configuration to PLL */
- __raw_writel(lock, pll->lock_reg);
- __raw_writel(con0, pll->con_reg);
- __raw_writel(con1, pll->con_reg + 0x4);
+ writel_relaxed(lock, pll->lock_reg);
+ writel_relaxed(con0, pll->con_reg);
+ writel_relaxed(con1, pll->con_reg + 0x4);
/* Wait for locking. */
start = ktime_get();
- while (!(__raw_readl(pll->con_reg) & PLL46XX_LOCKED)) {
+ while (!(readl_relaxed(pll->con_reg) & PLL46XX_LOCKED)) {
ktime_t delta = ktime_sub(ktime_get(), start);
if (ktime_to_ms(delta) > PLL_TIMEOUT_MS) {
@@ -574,7 +574,7 @@
u32 mdiv, pdiv, sdiv, pll_con;
u64 fvco = parent_rate;
- pll_con = __raw_readl(pll->con_reg);
+ pll_con = readl_relaxed(pll->con_reg);
mdiv = (pll_con >> PLL6552_MDIV_SHIFT) & PLL6552_MDIV_MASK;
pdiv = (pll_con >> PLL6552_PDIV_SHIFT) & PLL6552_PDIV_MASK;
sdiv = (pll_con >> PLL6552_SDIV_SHIFT) & PLL6552_SDIV_MASK;
@@ -609,8 +609,8 @@
u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1;
u64 fvco = parent_rate;
- pll_con0 = __raw_readl(pll->con_reg);
- pll_con1 = __raw_readl(pll->con_reg + 0x4);
+ pll_con0 = readl_relaxed(pll->con_reg);
+ pll_con1 = readl_relaxed(pll->con_reg + 0x4);
mdiv = (pll_con0 >> PLL6553_MDIV_SHIFT) & PLL6553_MDIV_MASK;
pdiv = (pll_con0 >> PLL6553_PDIV_SHIFT) & PLL6553_PDIV_MASK;
sdiv = (pll_con0 >> PLL6553_SDIV_SHIFT) & PLL6553_SDIV_MASK;
@@ -655,7 +655,7 @@
u32 r, p, m, s, pll_stat;
u64 fvco = parent_rate;
- pll_stat = __raw_readl(pll->reg_base + pll->offset * 3);
+ pll_stat = readl_relaxed(pll->reg_base + pll->offset * 3);
r = (pll_stat >> PLL2550X_R_SHIFT) & PLL2550X_R_MASK;
if (!r)
return 0;
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index f503f32..afad1c8 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -31,7 +31,7 @@
unsigned long i;
for (i = 0; i < nr_reg_dump; i++, rd++)
- rd->value = __raw_readl(reg_base + rd->offset);
+ rd->value = readl_relaxed(reg_base + rd->offset);
return 0;
}
@@ -42,7 +42,7 @@
unsigned long i;
for (i = 0; i < nr_reg_dump; i++, rd++)
- __raw_writel(rd->value, reg_base + rd->offset);
+ writel_relaxed(rd->value, reg_base + rd->offset);
}
static struct syscore_ops samsung_clk_syscore_ops = {
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 8cc5040..1283262 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -97,7 +97,7 @@
u32 mask;
u32 i;
- __raw_writel(value, reg_base + offset);
+ writel_relaxed(value, reg_base + offset);
if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
@@ -147,8 +147,8 @@
/* Wait maximum 1 ms until written values are applied */
for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
- if (__raw_readl(reg_base + stat_addr) & mask) {
- __raw_writel(mask, reg_base + stat_addr);
+ if (readl_relaxed(reg_base + stat_addr) & mask) {
+ writel_relaxed(mask, reg_base + stat_addr);
return;
}
@@ -163,7 +163,7 @@
exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
- reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
+ reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
reg |= MCT_G_TCON_START;
exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
}
@@ -171,12 +171,12 @@
static cycle_t exynos4_frc_read(struct clocksource *cs)
{
unsigned int lo, hi;
- u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
+ u32 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
do {
hi = hi2;
- lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
- hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
+ lo = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L);
+ hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U);
} while (hi != hi2);
return ((cycle_t)hi << 32) | lo;
@@ -212,7 +212,7 @@
{
unsigned int tcon;
- tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
+ tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
@@ -225,7 +225,7 @@
unsigned int tcon;
cycle_t comp_cycle;
- tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
+ tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON);
if (mode == CLOCK_EVT_MODE_PERIODIC) {
tcon |= MCT_G_TCON_COMP0_AUTO_INC;
@@ -314,7 +314,7 @@
unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
- tmp = __raw_readl(reg_base + offset);
+ tmp = readl_relaxed(reg_base + offset);
if (tmp & mask) {
tmp &= ~mask;
exynos4_mct_write(tmp, offset);
@@ -336,7 +336,7 @@
/* enable MCT tick interrupt */
exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
- tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
+ tmp = readl_relaxed(reg_base + mevt->base + MCT_L_TCON_OFFSET);
tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
MCT_L_TCON_INTERVAL_MODE;
exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
@@ -388,7 +388,7 @@
exynos4_mct_tick_stop(mevt);
/* Clear the MCT tick interrupt */
- if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
+ if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
return 1;
} else {
diff --git a/drivers/clocksource/samsung_pwm_timer.c b/drivers/clocksource/samsung_pwm_timer.c
index 5645cfc..19aaddd 100644
--- a/drivers/clocksource/samsung_pwm_timer.c
+++ b/drivers/clocksource/samsung_pwm_timer.c
@@ -130,9 +130,9 @@
spin_lock_irqsave(&samsung_pwm_lock, flags);
- tcon = __raw_readl(pwm.base + REG_TCON);
+ tcon = readl_relaxed(pwm.base + REG_TCON);
tcon &= ~TCON_START(channel);
- __raw_writel(tcon, pwm.base + REG_TCON);
+ writel_relaxed(tcon, pwm.base + REG_TCON);
spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}
@@ -148,14 +148,14 @@
spin_lock_irqsave(&samsung_pwm_lock, flags);
- tcon = __raw_readl(pwm.base + REG_TCON);
+ tcon = readl_relaxed(pwm.base + REG_TCON);
tcon &= ~(TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan));
tcon |= TCON_MANUALUPDATE(tcon_chan);
- __raw_writel(tcnt, pwm.base + REG_TCNTB(channel));
- __raw_writel(tcnt, pwm.base + REG_TCMPB(channel));
- __raw_writel(tcon, pwm.base + REG_TCON);
+ writel_relaxed(tcnt, pwm.base + REG_TCNTB(channel));
+ writel_relaxed(tcnt, pwm.base + REG_TCMPB(channel));
+ writel_relaxed(tcon, pwm.base + REG_TCON);
spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}
@@ -170,7 +170,7 @@
spin_lock_irqsave(&samsung_pwm_lock, flags);
- tcon = __raw_readl(pwm.base + REG_TCON);
+ tcon = readl_relaxed(pwm.base + REG_TCON);
tcon &= ~TCON_MANUALUPDATE(channel);
tcon |= TCON_START(channel);
@@ -180,7 +180,7 @@
else
tcon &= ~TCON_AUTORELOAD(channel);
- __raw_writel(tcon, pwm.base + REG_TCON);
+ writel_relaxed(tcon, pwm.base + REG_TCON);
spin_unlock_irqrestore(&samsung_pwm_lock, flags);
}
diff --git a/drivers/cpufreq/exynos4210-cpufreq.c b/drivers/cpufreq/exynos4210-cpufreq.c
index 40d84c4..df4f5cf 100644
--- a/drivers/cpufreq/exynos4210-cpufreq.c
+++ b/drivers/cpufreq/exynos4210-cpufreq.c
@@ -60,20 +60,20 @@
tmp = apll_freq_4210[div_index].clk_div_cpu0;
- __raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
+ writel_relaxed(tmp, EXYNOS4_CLKDIV_CPU);
do {
- tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU);
+ tmp = readl_relaxed(EXYNOS4_CLKDIV_STATCPU);
} while (tmp & 0x1111111);
/* Change Divider - CPU1 */
tmp = apll_freq_4210[div_index].clk_div_cpu1;
- __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
+ writel_relaxed(tmp, EXYNOS4_CLKDIV_CPU1);
do {
- tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1);
+ tmp = readl_relaxed(EXYNOS4_CLKDIV_STATCPU1);
} while (tmp & 0x11);
}
@@ -85,7 +85,7 @@
clk_set_parent(moutcore, mout_mpll);
do {
- tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
+ tmp = (readl_relaxed(EXYNOS4_CLKMUX_STATCPU)
>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
tmp &= 0x7;
} while (tmp != 0x2);
@@ -96,7 +96,7 @@
clk_set_parent(moutcore, mout_apll);
do {
- tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
+ tmp = readl_relaxed(EXYNOS4_CLKMUX_STATCPU);
tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
}
diff --git a/drivers/cpufreq/exynos4x12-cpufreq.c b/drivers/cpufreq/exynos4x12-cpufreq.c
index 7c11ace..972d0b1 100644
--- a/drivers/cpufreq/exynos4x12-cpufreq.c
+++ b/drivers/cpufreq/exynos4x12-cpufreq.c
@@ -106,21 +106,21 @@
tmp = apll_freq_4x12[div_index].clk_div_cpu0;
- __raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
+ writel_relaxed(tmp, EXYNOS4_CLKDIV_CPU);
- while (__raw_readl(EXYNOS4_CLKDIV_STATCPU) & 0x11111111)
+ while (readl_relaxed(EXYNOS4_CLKDIV_STATCPU) & 0x11111111)
cpu_relax();
/* Change Divider - CPU1 */
tmp = apll_freq_4x12[div_index].clk_div_cpu1;
- __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
+ writel_relaxed(tmp, EXYNOS4_CLKDIV_CPU1);
if (soc_is_exynos4212())
stat_cpu1 = 0x11;
else
stat_cpu1 = 0x111;
- while (__raw_readl(EXYNOS4_CLKDIV_STATCPU1) & stat_cpu1)
+ while (readl_relaxed(EXYNOS4_CLKDIV_STATCPU1) & stat_cpu1)
cpu_relax();
}
@@ -133,7 +133,7 @@
do {
cpu_relax();
- tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
+ tmp = (readl_relaxed(EXYNOS4_CLKMUX_STATCPU)
>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
tmp &= 0x7;
} while (tmp != 0x2);
@@ -145,7 +145,7 @@
do {
cpu_relax();
- tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
+ tmp = readl_relaxed(EXYNOS4_CLKMUX_STATCPU);
tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
}
diff --git a/drivers/cpufreq/exynos5250-cpufreq.c b/drivers/cpufreq/exynos5250-cpufreq.c
index 5f90b82..d212a72 100644
--- a/drivers/cpufreq/exynos5250-cpufreq.c
+++ b/drivers/cpufreq/exynos5250-cpufreq.c
@@ -87,17 +87,17 @@
tmp = apll_freq_5250[div_index].clk_div_cpu0;
- __raw_writel(tmp, EXYNOS5_CLKDIV_CPU0);
+ writel_relaxed(tmp, EXYNOS5_CLKDIV_CPU0);
- while (__raw_readl(EXYNOS5_CLKDIV_STATCPU0) & 0x11111111)
+ while (readl_relaxed(EXYNOS5_CLKDIV_STATCPU0) & 0x11111111)
cpu_relax();
/* Change Divider - CPU1 */
tmp = apll_freq_5250[div_index].clk_div_cpu1;
- __raw_writel(tmp, EXYNOS5_CLKDIV_CPU1);
+ writel_relaxed(tmp, EXYNOS5_CLKDIV_CPU1);
- while (__raw_readl(EXYNOS5_CLKDIV_STATCPU1) & 0x11)
+ while (readl_relaxed(EXYNOS5_CLKDIV_STATCPU1) & 0x11)
cpu_relax();
}
@@ -111,7 +111,7 @@
do {
cpu_relax();
- tmp = (__raw_readl(EXYNOS5_CLKMUX_STATCPU) >> 16);
+ tmp = (readl_relaxed(EXYNOS5_CLKMUX_STATCPU) >> 16);
tmp &= 0x7;
} while (tmp != 0x2);
@@ -122,7 +122,7 @@
do {
cpu_relax();
- tmp = __raw_readl(EXYNOS5_CLKMUX_STATCPU);
+ tmp = readl_relaxed(EXYNOS5_CLKMUX_STATCPU);
tmp &= (0x7 << 16);
} while (tmp != (0x1 << 16));
}
diff --git a/drivers/cpufreq/exynos5440-cpufreq.c b/drivers/cpufreq/exynos5440-cpufreq.c
index 49b75601..8478ca7 100644
--- a/drivers/cpufreq/exynos5440-cpufreq.c
+++ b/drivers/cpufreq/exynos5440-cpufreq.c
@@ -157,7 +157,7 @@
tmp = (clk_div | ema_div | (volt_id << P0_7_VDD_SHIFT)
| ((freq / FREQ_UNIT) << P0_7_FREQ_SHIFT));
- __raw_writel(tmp, dvfs_info->base + XMU_PMU_P0_7 + 4 * i);
+ writel_relaxed(tmp, dvfs_info->base + XMU_PMU_P0_7 + 4 * i);
}
rcu_read_unlock();
@@ -169,17 +169,17 @@
unsigned int tmp, i, cpu;
struct cpufreq_frequency_table *freq_table = dvfs_info->freq_table;
/* Disable DVFS */
- __raw_writel(0, dvfs_info->base + XMU_DVFS_CTRL);
+ writel_relaxed(0, dvfs_info->base + XMU_DVFS_CTRL);
/* Enable PSTATE Change Event */
- tmp = __raw_readl(dvfs_info->base + XMU_PMUEVTEN);
+ tmp = readl_relaxed(dvfs_info->base + XMU_PMUEVTEN);
tmp |= (1 << PSTATE_CHANGED_EVTEN_SHIFT);
- __raw_writel(tmp, dvfs_info->base + XMU_PMUEVTEN);
+ writel_relaxed(tmp, dvfs_info->base + XMU_PMUEVTEN);
/* Enable PSTATE Change IRQ */
- tmp = __raw_readl(dvfs_info->base + XMU_PMUIRQEN);
+ tmp = readl_relaxed(dvfs_info->base + XMU_PMUIRQEN);
tmp |= (1 << PSTATE_CHANGED_IRQEN_SHIFT);
- __raw_writel(tmp, dvfs_info->base + XMU_PMUIRQEN);
+ writel_relaxed(tmp, dvfs_info->base + XMU_PMUIRQEN);
/* Set initial performance index */
for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
@@ -197,14 +197,14 @@
cur_frequency);
for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++) {
- tmp = __raw_readl(dvfs_info->base + XMU_C0_3_PSTATE + cpu * 4);
+ tmp = readl_relaxed(dvfs_info->base + XMU_C0_3_PSTATE + cpu * 4);
tmp &= ~(P_VALUE_MASK << C0_3_PSTATE_NEW_SHIFT);
tmp |= (i << C0_3_PSTATE_NEW_SHIFT);
- __raw_writel(tmp, dvfs_info->base + XMU_C0_3_PSTATE + cpu * 4);
+ writel_relaxed(tmp, dvfs_info->base + XMU_C0_3_PSTATE + cpu * 4);
}
/* Enable DVFS */
- __raw_writel(1 << XMU_DVFS_CTRL_EN_SHIFT,
+ writel_relaxed(1 << XMU_DVFS_CTRL_EN_SHIFT,
dvfs_info->base + XMU_DVFS_CTRL);
}
@@ -223,11 +223,11 @@
/* Set the target frequency in all C0_3_PSTATE register */
for_each_cpu(i, policy->cpus) {
- tmp = __raw_readl(dvfs_info->base + XMU_C0_3_PSTATE + i * 4);
+ tmp = readl_relaxed(dvfs_info->base + XMU_C0_3_PSTATE + i * 4);
tmp &= ~(P_VALUE_MASK << C0_3_PSTATE_NEW_SHIFT);
tmp |= (index << C0_3_PSTATE_NEW_SHIFT);
- __raw_writel(tmp, dvfs_info->base + XMU_C0_3_PSTATE + i * 4);
+ writel_relaxed(tmp, dvfs_info->base + XMU_C0_3_PSTATE + i * 4);
}
mutex_unlock(&cpufreq_lock);
return 0;
@@ -246,7 +246,7 @@
mutex_lock(&cpufreq_lock);
freqs.old = policy->cur;
- cur_pstate = __raw_readl(dvfs_info->base + XMU_P_STATUS);
+ cur_pstate = readl_relaxed(dvfs_info->base + XMU_P_STATUS);
if (cur_pstate >> C0_3_PSTATE_VALID_SHIFT & 0x1)
index = (cur_pstate >> C0_3_PSTATE_CURR_SHIFT) & P_VALUE_MASK;
else
@@ -270,9 +270,9 @@
{
unsigned int tmp;
- tmp = __raw_readl(dvfs_info->base + XMU_PMUIRQ);
+ tmp = readl_relaxed(dvfs_info->base + XMU_PMUIRQ);
if (tmp >> PSTATE_CHANGED_SHIFT & 0x1) {
- __raw_writel(tmp, dvfs_info->base + XMU_PMUIRQ);
+ writel_relaxed(tmp, dvfs_info->base + XMU_PMUIRQ);
disable_irq_nosync(irq);
schedule_work(&dvfs_info->irq_work);
}
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index a85e00b..81e6c83 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -50,10 +50,10 @@
int shift = off * 2;
u32 pup;
- pup = __raw_readl(reg);
+ pup = readl_relaxed(reg);
pup &= ~(3 << shift);
pup |= pull << shift;
- __raw_writel(pup, reg);
+ writel_relaxed(pup, reg);
return 0;
}
@@ -63,7 +63,7 @@
{
void __iomem *reg = chip->base + 0x08;
int shift = off * 2;
- u32 pup = __raw_readl(reg);
+ u32 pup = readl_relaxed(reg);
pup >>= shift;
pup &= 0x3;
@@ -116,7 +116,7 @@
samsung_gpio_pull_t updown)
{
void __iomem *reg = chip->base + 0x08;
- u32 pup = __raw_readl(reg);
+ u32 pup = readl_relaxed(reg);
if (pull == updown)
pup &= ~(1 << off);
@@ -125,7 +125,7 @@
else
return -EINVAL;
- __raw_writel(pup, reg);
+ writel_relaxed(pup, reg);
return 0;
}
@@ -134,7 +134,7 @@
samsung_gpio_pull_t updown)
{
void __iomem *reg = chip->base + 0x08;
- u32 pup = __raw_readl(reg);
+ u32 pup = readl_relaxed(reg);
pup &= (1 << off);
return pup ? S3C_GPIO_PULL_NONE : updown;
@@ -193,10 +193,10 @@
cfg <<= shift;
}
- con = __raw_readl(reg);
+ con = readl_relaxed(reg);
con &= ~(0x3 << shift);
con |= cfg;
- __raw_writel(con, reg);
+ writel_relaxed(con, reg);
return 0;
}
@@ -216,7 +216,7 @@
{
u32 con;
- con = __raw_readl(chip->base);
+ con = readl_relaxed(chip->base);
con >>= off * 2;
con &= 3;
@@ -256,10 +256,10 @@
cfg <<= shift;
}
- con = __raw_readl(reg);
+ con = readl_relaxed(reg);
con &= ~(0xf << shift);
con |= cfg;
- __raw_writel(con, reg);
+ writel_relaxed(con, reg);
return 0;
}
@@ -286,7 +286,7 @@
if (off < 8 && chip->chip.ngpio > 8)
reg -= 4;
- con = __raw_readl(reg);
+ con = readl_relaxed(reg);
con >>= shift;
con &= 0xf;
@@ -324,10 +324,10 @@
cfg <<= shift;
}
- con = __raw_readl(reg);
+ con = readl_relaxed(reg);
con &= ~(0x1 << shift);
con |= cfg;
- __raw_writel(con, reg);
+ writel_relaxed(con, reg);
return 0;
}
@@ -349,7 +349,7 @@
{
u32 con;
- con = __raw_readl(chip->base);
+ con = readl_relaxed(chip->base);
con >>= off;
con &= 1;
con++;
@@ -389,10 +389,10 @@
cfg <<= shift;
}
- con = __raw_readl(reg);
+ con = readl_relaxed(reg);
con &= ~(0xf << shift);
con |= cfg;
- __raw_writel(con, reg);
+ writel_relaxed(con, reg);
return 0;
}
@@ -490,10 +490,10 @@
samsung_gpio_lock(ourchip, flags);
- con = __raw_readl(base + 0x00);
+ con = readl_relaxed(base + 0x00);
con &= ~(3 << (offset * 2));
- __raw_writel(con, base + 0x00);
+ writel_relaxed(con, base + 0x00);
samsung_gpio_unlock(ourchip, flags);
return 0;
@@ -510,18 +510,18 @@
samsung_gpio_lock(ourchip, flags);
- dat = __raw_readl(base + 0x04);
+ dat = readl_relaxed(base + 0x04);
dat &= ~(1 << offset);
if (value)
dat |= 1 << offset;
- __raw_writel(dat, base + 0x04);
+ writel_relaxed(dat, base + 0x04);
- con = __raw_readl(base + 0x00);
+ con = readl_relaxed(base + 0x00);
con &= ~(3 << (offset * 2));
con |= 1 << (offset * 2);
- __raw_writel(con, base + 0x00);
- __raw_writel(dat, base + 0x04);
+ writel_relaxed(con, base + 0x00);
+ writel_relaxed(dat, base + 0x04);
samsung_gpio_unlock(ourchip, flags);
return 0;
@@ -550,12 +550,12 @@
void __iomem *base = ourchip->base;
unsigned long con;
- con = __raw_readl(base + GPIOCON_OFF);
+ con = readl_relaxed(base + GPIOCON_OFF);
if (ourchip->bitmap_gpio_int & BIT(offset))
con |= 0xf << con_4bit_shift(offset);
else
con &= ~(0xf << con_4bit_shift(offset));
- __raw_writel(con, base + GPIOCON_OFF);
+ writel_relaxed(con, base + GPIOCON_OFF);
pr_debug("%s: %p: CON now %08lx\n", __func__, base, con);
@@ -570,20 +570,20 @@
unsigned long con;
unsigned long dat;
- con = __raw_readl(base + GPIOCON_OFF);
+ con = readl_relaxed(base + GPIOCON_OFF);
con &= ~(0xf << con_4bit_shift(offset));
con |= 0x1 << con_4bit_shift(offset);
- dat = __raw_readl(base + GPIODAT_OFF);
+ dat = readl_relaxed(base + GPIODAT_OFF);
if (value)
dat |= 1 << offset;
else
dat &= ~(1 << offset);
- __raw_writel(dat, base + GPIODAT_OFF);
- __raw_writel(con, base + GPIOCON_OFF);
- __raw_writel(dat, base + GPIODAT_OFF);
+ writel_relaxed(dat, base + GPIODAT_OFF);
+ writel_relaxed(con, base + GPIOCON_OFF);
+ writel_relaxed(dat, base + GPIODAT_OFF);
pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
@@ -625,9 +625,9 @@
else
regcon -= 4;
- con = __raw_readl(regcon);
+ con = readl_relaxed(regcon);
con &= ~(0xf << con_4bit_shift(offset));
- __raw_writel(con, regcon);
+ writel_relaxed(con, regcon);
pr_debug("%s: %p: CON %08lx\n", __func__, base, con);
@@ -649,20 +649,20 @@
else
regcon -= 4;
- con = __raw_readl(regcon);
+ con = readl_relaxed(regcon);
con &= ~(0xf << con_4bit_shift(con_offset));
con |= 0x1 << con_4bit_shift(con_offset);
- dat = __raw_readl(base + GPIODAT_OFF);
+ dat = readl_relaxed(base + GPIODAT_OFF);
if (value)
dat |= 1 << offset;
else
dat &= ~(1 << offset);
- __raw_writel(dat, base + GPIODAT_OFF);
- __raw_writel(con, regcon);
- __raw_writel(dat, base + GPIODAT_OFF);
+ writel_relaxed(dat, base + GPIODAT_OFF);
+ writel_relaxed(con, regcon);
+ writel_relaxed(dat, base + GPIODAT_OFF);
pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
@@ -688,19 +688,19 @@
local_irq_save(flags);
- con = __raw_readl(base + 0x00);
- dat = __raw_readl(base + 0x04);
+ con = readl_relaxed(base + 0x00);
+ dat = readl_relaxed(base + 0x04);
dat &= ~(1 << offset);
if (value)
dat |= 1 << offset;
- __raw_writel(dat, base + 0x04);
+ writel_relaxed(dat, base + 0x04);
con &= ~(1 << offset);
- __raw_writel(con, base + 0x00);
- __raw_writel(dat, base + 0x04);
+ writel_relaxed(con, base + 0x00);
+ writel_relaxed(dat, base + 0x04);
local_irq_restore(flags);
return 0;
@@ -736,9 +736,9 @@
samsung_gpio_lock(ourchip, flags);
- con = __raw_readl(regcon);
+ con = readl_relaxed(regcon);
con &= ~(0xf << con_4bit_shift(offset));
- __raw_writel(con, regcon);
+ writel_relaxed(con, regcon);
samsung_gpio_unlock(ourchip, flags);
@@ -774,18 +774,18 @@
samsung_gpio_lock(ourchip, flags);
- con = __raw_readl(regcon);
+ con = readl_relaxed(regcon);
con &= ~(0xf << con_4bit_shift(con_offset));
con |= 0x1 << con_4bit_shift(con_offset);
- dat = __raw_readl(base + GPIODAT_OFF);
+ dat = readl_relaxed(base + GPIODAT_OFF);
if (value)
dat |= 1 << offset;
else
dat &= ~(1 << offset);
- __raw_writel(con, regcon);
- __raw_writel(dat, base + GPIODAT_OFF);
+ writel_relaxed(con, regcon);
+ writel_relaxed(dat, base + GPIODAT_OFF);
samsung_gpio_unlock(ourchip, flags);
@@ -802,11 +802,11 @@
samsung_gpio_lock(ourchip, flags);
- dat = __raw_readl(base + 0x04);
+ dat = readl_relaxed(base + 0x04);
dat &= ~(1 << offset);
if (value)
dat |= 1 << offset;
- __raw_writel(dat, base + 0x04);
+ writel_relaxed(dat, base + 0x04);
samsung_gpio_unlock(ourchip, flags);
}
@@ -816,7 +816,7 @@
struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
unsigned long val;
- val = __raw_readl(ourchip->base + 0x04);
+ val = readl_relaxed(ourchip->base + 0x04);
val >>= offset;
val &= 1;
@@ -2289,7 +2289,7 @@
shift = off * 2;
reg = chip->base + 0x0C;
- drvstr = __raw_readl(reg);
+ drvstr = readl_relaxed(reg);
drvstr = drvstr >> shift;
drvstr &= 0x3;
@@ -2312,11 +2312,11 @@
shift = off * 2;
reg = chip->base + 0x0C;
- tmp = __raw_readl(reg);
+ tmp = readl_relaxed(reg);
tmp &= ~(0x3 << shift);
tmp |= drvstr << shift;
- __raw_writel(tmp, reg);
+ writel_relaxed(tmp, reg);
return 0;
}
@@ -2330,10 +2330,10 @@
unsigned long misccr;
local_irq_save(flags);
- misccr = __raw_readl(S3C24XX_MISCCR);
+ misccr = readl_relaxed(S3C24XX_MISCCR);
misccr &= ~clear;
misccr ^= change;
- __raw_writel(misccr, S3C24XX_MISCCR);
+ writel_relaxed(misccr, S3C24XX_MISCCR);
local_irq_restore(flags);
return misccr;
diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c
index 40e6440..73fb699 100644
--- a/drivers/irqchip/exynos-combiner.c
+++ b/drivers/irqchip/exynos-combiner.c
@@ -50,14 +50,14 @@
{
u32 mask = 1 << (data->hwirq % 32);
- __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
+ writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
}
static void combiner_unmask_irq(struct irq_data *data)
{
u32 mask = 1 << (data->hwirq % 32);
- __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
+ writel_relaxed(mask, combiner_base(data) + COMBINER_ENABLE_SET);
}
static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
@@ -70,7 +70,7 @@
chained_irq_enter(chip, desc);
spin_lock(&irq_controller_lock);
- status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
+ status = readl_relaxed(chip_data->base + COMBINER_INT_STATUS);
spin_unlock(&irq_controller_lock);
status &= chip_data->irq_mask;
@@ -131,7 +131,7 @@
combiner_data->parent_irq = irq;
/* Disable all interrupts */
- __raw_writel(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
+ writel_relaxed(combiner_data->irq_mask, base + COMBINER_ENABLE_CLEAR);
}
static int combiner_irq_domain_xlate(struct irq_domain *d,
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index bc50912..42e1e2b 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -165,7 +165,7 @@
}
if (TMU_SUPPORTS(pdata, TRIM_RELOAD))
- __raw_writel(1, data->base + reg->triminfo_ctrl);
+ writel_relaxed(1, data->base + reg->triminfo_ctrl);
if (pdata->cal_mode == HW_MODE)
goto skip_calib_data;
diff --git a/drivers/tty/serial/samsung.h b/drivers/tty/serial/samsung.h
index 8827e54..ceb11f7 100644
--- a/drivers/tty/serial/samsung.h
+++ b/drivers/tty/serial/samsung.h
@@ -72,10 +72,10 @@
((unsigned long *)(unsigned long)((port)->membase + (reg)))
#define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
-#define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
+#define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
#define wr_regb(port, reg, val) __raw_writeb(val, portaddr(port, reg))
-#define wr_regl(port, reg, val) __raw_writel(val, portaddr(port, reg))
+#define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
#if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
defined(CONFIG_DEBUG_LL) && \
