| /* |
| * SAMSUNG EXYNOS5420 SoC device tree source |
| * |
| * Copyright (c) 2013 Samsung Electronics Co., Ltd. |
| * http://www.samsung.com |
| * |
| * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file. |
| * EXYNOS5420 based board files can include this file and provide |
| * values for board specfic bindings. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| */ |
| |
| #include "exynos5.dtsi" |
| #include "exynos5420-pinctrl.dtsi" |
| |
| #include <dt-bindings/clk/exynos-audss-clk.h> |
| |
| / { |
| compatible = "samsung,exynos5420"; |
| |
| aliases { |
| pinctrl0 = &pinctrl_0; |
| pinctrl1 = &pinctrl_1; |
| pinctrl2 = &pinctrl_2; |
| pinctrl3 = &pinctrl_3; |
| pinctrl4 = &pinctrl_4; |
| i2c0 = &i2c_0; |
| i2c1 = &i2c_1; |
| i2c2 = &i2c_2; |
| i2c3 = &i2c_3; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a15"; |
| reg = <0x0>; |
| clock-frequency = <1800000000>; |
| }; |
| |
| cpu1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a15"; |
| reg = <0x1>; |
| clock-frequency = <1800000000>; |
| }; |
| |
| cpu2: cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a15"; |
| reg = <0x2>; |
| clock-frequency = <1800000000>; |
| }; |
| |
| cpu3: cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a15"; |
| reg = <0x3>; |
| clock-frequency = <1800000000>; |
| }; |
| }; |
| |
| clock: clock-controller@10010000 { |
| compatible = "samsung,exynos5420-clock"; |
| reg = <0x10010000 0x30000>; |
| #clock-cells = <1>; |
| }; |
| |
| clock_audss: audss-clock-controller@3810000 { |
| compatible = "samsung,exynos5420-audss-clock"; |
| reg = <0x03810000 0x0C>; |
| #clock-cells = <1>; |
| clocks = <&clock 148>; |
| clock-names = "sclk_audio"; |
| }; |
| |
| codec@11000000 { |
| compatible = "samsung,mfc-v7"; |
| reg = <0x11000000 0x10000>; |
| interrupts = <0 96 0>; |
| clocks = <&clock 401>; |
| clock-names = "mfc"; |
| }; |
| |
| mct@101C0000 { |
| compatible = "samsung,exynos4210-mct"; |
| reg = <0x101C0000 0x800>; |
| interrupt-controller; |
| #interrups-cells = <1>; |
| interrupt-parent = <&mct_map>; |
| interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>; |
| clocks = <&clock 1>, <&clock 315>; |
| clock-names = "fin_pll", "mct"; |
| |
| mct_map: mct-map { |
| #interrupt-cells = <1>; |
| #address-cells = <0>; |
| #size-cells = <0>; |
| interrupt-map = <0 &combiner 23 3>, |
| <1 &combiner 23 4>, |
| <2 &combiner 25 2>, |
| <3 &combiner 25 3>, |
| <4 &gic 0 120 0>, |
| <5 &gic 0 121 0>, |
| <6 &gic 0 122 0>, |
| <7 &gic 0 123 0>; |
| }; |
| }; |
| |
| gsc_pd: power-domain@10044000 { |
| compatible = "samsung,exynos4210-pd"; |
| reg = <0x10044000 0x20>; |
| }; |
| |
| isp_pd: power-domain@10044020 { |
| compatible = "samsung,exynos4210-pd"; |
| reg = <0x10044020 0x20>; |
| }; |
| |
| mfc_pd: power-domain@10044060 { |
| compatible = "samsung,exynos4210-pd"; |
| reg = <0x10044060 0x20>; |
| }; |
| |
| disp_pd: power-domain@100440C0 { |
| compatible = "samsung,exynos4210-pd"; |
| reg = <0x100440C0 0x20>; |
| }; |
| |
| mau_pd: power-domain@100440E0 { |
| compatible = "samsung,exynos4210-pd"; |
| reg = <0x100440E0 0x20>; |
| }; |
| |
| g2d_pd: power-domain@10044100 { |
| compatible = "samsung,exynos4210-pd"; |
| reg = <0x10044100 0x20>; |
| }; |
| |
| msc_pd: power-domain@10044120 { |
| compatible = "samsung,exynos4210-pd"; |
| reg = <0x10044120 0x20>; |
| }; |
| |
| pinctrl_0: pinctrl@13400000 { |
| compatible = "samsung,exynos5420-pinctrl"; |
| reg = <0x13400000 0x1000>; |
| interrupts = <0 45 0>; |
| |
| wakeup-interrupt-controller { |
| compatible = "samsung,exynos4210-wakeup-eint"; |
| interrupt-parent = <&gic>; |
| interrupts = <0 32 0>; |
| }; |
| }; |
| |
| pinctrl_1: pinctrl@13410000 { |
| compatible = "samsung,exynos5420-pinctrl"; |
| reg = <0x13410000 0x1000>; |
| interrupts = <0 78 0>; |
| }; |
| |
| pinctrl_2: pinctrl@14000000 { |
| compatible = "samsung,exynos5420-pinctrl"; |
| reg = <0x14000000 0x1000>; |
| interrupts = <0 46 0>; |
| }; |
| |
| pinctrl_3: pinctrl@14010000 { |
| compatible = "samsung,exynos5420-pinctrl"; |
| reg = <0x14010000 0x1000>; |
| interrupts = <0 50 0>; |
| }; |
| |
| pinctrl_4: pinctrl@03860000 { |
| compatible = "samsung,exynos5420-pinctrl"; |
| reg = <0x03860000 0x1000>; |
| interrupts = <0 47 0>; |
| }; |
| |
| rtc@101E0000 { |
| clocks = <&clock 317>; |
| clock-names = "rtc"; |
| status = "okay"; |
| }; |
| |
| serial@12C00000 { |
| clocks = <&clock 257>, <&clock 128>; |
| clock-names = "uart", "clk_uart_baud0"; |
| }; |
| |
| serial@12C10000 { |
| clocks = <&clock 258>, <&clock 129>; |
| clock-names = "uart", "clk_uart_baud0"; |
| }; |
| |
| serial@12C20000 { |
| clocks = <&clock 259>, <&clock 130>; |
| clock-names = "uart", "clk_uart_baud0"; |
| }; |
| |
| serial@12C30000 { |
| clocks = <&clock 260>, <&clock 131>; |
| clock-names = "uart", "clk_uart_baud0"; |
| }; |
| |
| dp_phy: video-phy@10040728 { |
| compatible = "samsung,exynos5250-dp-video-phy"; |
| reg = <0x10040728 4>; |
| #phy-cells = <0>; |
| }; |
| |
| dp-controller@145B0000 { |
| clocks = <&clock 412>; |
| clock-names = "dp"; |
| phys = <&dp_phy>; |
| phy-names = "dp"; |
| }; |
| |
| fimd@14400000 { |
| samsung,power-domain = <&disp_pd>; |
| clocks = <&clock 147>, <&clock 421>; |
| clock-names = "sclk_fimd", "fimd"; |
| }; |
| |
| adc: adc@12D10000 { |
| compatible = "samsung,exynos-adc-v2"; |
| reg = <0x12D10000 0x100>, <0x10040720 0x4>; |
| interrupts = <0 106 0>; |
| clocks = <&clock 270>; |
| clock-names = "adc"; |
| #io-channel-cells = <1>; |
| io-channel-ranges; |
| status = "disabled"; |
| }; |
| |
| i2c_0: i2c@12C60000 { |
| compatible = "samsung,s3c2440-i2c"; |
| reg = <0x12C60000 0x100>; |
| interrupts = <0 56 0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&clock 261>; |
| clock-names = "i2c"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c0_bus>; |
| status = "disabled"; |
| }; |
| |
| i2c_1: i2c@12C70000 { |
| compatible = "samsung,s3c2440-i2c"; |
| reg = <0x12C70000 0x100>; |
| interrupts = <0 57 0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&clock 262>; |
| clock-names = "i2c"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c1_bus>; |
| status = "disabled"; |
| }; |
| |
| i2c_2: i2c@12C80000 { |
| compatible = "samsung,s3c2440-i2c"; |
| reg = <0x12C80000 0x100>; |
| interrupts = <0 58 0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&clock 263>; |
| clock-names = "i2c"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c2_bus>; |
| status = "disabled"; |
| }; |
| |
| i2c_3: i2c@12C90000 { |
| compatible = "samsung,s3c2440-i2c"; |
| reg = <0x12C90000 0x100>; |
| interrupts = <0 59 0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&clock 264>; |
| clock-names = "i2c"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c3_bus>; |
| status = "disabled"; |
| }; |
| |
| hdmi@14530000 { |
| compatible = "samsung,exynos4212-hdmi"; |
| reg = <0x14530000 0x70000>; |
| interrupts = <0 95 0>; |
| clocks = <&clock 413>, <&clock 143>, <&clock 768>, |
| <&clock 158>, <&clock 640>; |
| clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", |
| "sclk_hdmiphy", "mout_hdmi"; |
| status = "disabled"; |
| }; |
| |
| mixer@14450000 { |
| compatible = "samsung,exynos5420-mixer"; |
| reg = <0x14450000 0x10000>; |
| interrupts = <0 94 0>; |
| clocks = <&clock 431>, <&clock 143>; |
| clock-names = "mixer", "sclk_hdmi"; |
| }; |
| }; |
