dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 1 | /* |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 2 | * Copyright (C) NEC Electronics Corporation 2004-2006 |
| 3 | * |
| 4 | * This file is based on the arch/mips/ddb5xxx/ddb5477/irq.c |
| 5 | * |
| 6 | * Copyright 2001 MontaVista Software Inc. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | */ |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 22 | #include <linux/init.h> |
| 23 | #include <linux/interrupt.h> |
| 24 | #include <linux/irq.h> |
| 25 | #include <linux/types.h> |
| 26 | #include <linux/ptrace.h> |
| 27 | #include <linux/delay.h> |
| 28 | |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 29 | #include <asm/irq_cpu.h> |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 30 | #include <asm/mipsregs.h> |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 31 | #include <asm/addrspace.h> |
| 32 | #include <asm/bootinfo.h> |
| 33 | |
Shinya Kuribayashi | d91f2cb | 2008-10-24 01:30:20 +0900 | [diff] [blame] | 34 | #include <asm/emma/emma2rh.h> |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 35 | |
Thomas Gleixner | 90a568f | 2011-03-23 21:08:51 +0000 | [diff] [blame] | 36 | static void emma2rh_irq_enable(struct irq_data *d) |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 37 | { |
Thomas Gleixner | 90a568f | 2011-03-23 21:08:51 +0000 | [diff] [blame] | 38 | unsigned int irq = d->irq - EMMA2RH_IRQ_BASE; |
| 39 | u32 reg_value, reg_bitmask, reg_index; |
Shinya Kuribayashi | 49618d6 | 2008-10-24 01:35:59 +0900 | [diff] [blame] | 40 | |
| 41 | reg_index = EMMA2RH_BHIF_INT_EN_0 + |
| 42 | (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32); |
| 43 | reg_value = emma2rh_in32(reg_index); |
| 44 | reg_bitmask = 0x1 << (irq % 32); |
| 45 | emma2rh_out32(reg_index, reg_value | reg_bitmask); |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 46 | } |
| 47 | |
Thomas Gleixner | 90a568f | 2011-03-23 21:08:51 +0000 | [diff] [blame] | 48 | static void emma2rh_irq_disable(struct irq_data *d) |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 49 | { |
Thomas Gleixner | 90a568f | 2011-03-23 21:08:51 +0000 | [diff] [blame] | 50 | unsigned int irq = d->irq - EMMA2RH_IRQ_BASE; |
| 51 | u32 reg_value, reg_bitmask, reg_index; |
Shinya Kuribayashi | 49618d6 | 2008-10-24 01:35:59 +0900 | [diff] [blame] | 52 | |
| 53 | reg_index = EMMA2RH_BHIF_INT_EN_0 + |
| 54 | (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0) * (irq / 32); |
| 55 | reg_value = emma2rh_in32(reg_index); |
| 56 | reg_bitmask = 0x1 << (irq % 32); |
| 57 | emma2rh_out32(reg_index, reg_value & ~reg_bitmask); |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 58 | } |
| 59 | |
| 60 | struct irq_chip emma2rh_irq_controller = { |
| 61 | .name = "emma2rh_irq", |
Thomas Gleixner | 90a568f | 2011-03-23 21:08:51 +0000 | [diff] [blame] | 62 | .irq_mask = emma2rh_irq_disable, |
| 63 | .irq_unmask = emma2rh_irq_enable, |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 64 | }; |
| 65 | |
| 66 | void emma2rh_irq_init(void) |
| 67 | { |
| 68 | u32 i; |
| 69 | |
| 70 | for (i = 0; i < NUM_EMMA2RH_IRQ; i++) |
Thomas Gleixner | e4ec798 | 2011-03-27 15:19:28 +0200 | [diff] [blame] | 71 | irq_set_chip_and_handler_name(EMMA2RH_IRQ_BASE + i, |
Shinya Kuribayashi | ae3c1d3 | 2009-03-21 22:08:12 +0900 | [diff] [blame] | 72 | &emma2rh_irq_controller, |
| 73 | handle_level_irq, "level"); |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 74 | } |
| 75 | |
Thomas Gleixner | 90a568f | 2011-03-23 21:08:51 +0000 | [diff] [blame] | 76 | static void emma2rh_sw_irq_enable(struct irq_data *d) |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 77 | { |
Thomas Gleixner | 90a568f | 2011-03-23 21:08:51 +0000 | [diff] [blame] | 78 | unsigned int irq = d->irq - EMMA2RH_SW_IRQ_BASE; |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 79 | u32 reg; |
| 80 | |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 81 | reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); |
| 82 | reg |= 1 << irq; |
| 83 | emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg); |
| 84 | } |
| 85 | |
Thomas Gleixner | 90a568f | 2011-03-23 21:08:51 +0000 | [diff] [blame] | 86 | static void emma2rh_sw_irq_disable(struct irq_data *d) |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 87 | { |
Thomas Gleixner | 90a568f | 2011-03-23 21:08:51 +0000 | [diff] [blame] | 88 | unsigned int irq = d->irq - EMMA2RH_SW_IRQ_BASE; |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 89 | u32 reg; |
| 90 | |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 91 | reg = emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); |
| 92 | reg &= ~(1 << irq); |
| 93 | emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, reg); |
| 94 | } |
| 95 | |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 96 | struct irq_chip emma2rh_sw_irq_controller = { |
| 97 | .name = "emma2rh_sw_irq", |
Thomas Gleixner | 90a568f | 2011-03-23 21:08:51 +0000 | [diff] [blame] | 98 | .irq_mask = emma2rh_sw_irq_disable, |
| 99 | .irq_unmask = emma2rh_sw_irq_enable, |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 100 | }; |
| 101 | |
| 102 | void emma2rh_sw_irq_init(void) |
| 103 | { |
| 104 | u32 i; |
| 105 | |
| 106 | for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++) |
Thomas Gleixner | e4ec798 | 2011-03-27 15:19:28 +0200 | [diff] [blame] | 107 | irq_set_chip_and_handler_name(EMMA2RH_SW_IRQ_BASE + i, |
Shinya Kuribayashi | ae3c1d3 | 2009-03-21 22:08:12 +0900 | [diff] [blame] | 108 | &emma2rh_sw_irq_controller, |
| 109 | handle_level_irq, "level"); |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 110 | } |
| 111 | |
Thomas Gleixner | 90a568f | 2011-03-23 21:08:51 +0000 | [diff] [blame] | 112 | static void emma2rh_gpio_irq_enable(struct irq_data *d) |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 113 | { |
Thomas Gleixner | 90a568f | 2011-03-23 21:08:51 +0000 | [diff] [blame] | 114 | unsigned int irq = d->irq - EMMA2RH_GPIO_IRQ_BASE; |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 115 | u32 reg; |
| 116 | |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 117 | reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); |
| 118 | reg |= 1 << irq; |
| 119 | emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); |
| 120 | } |
| 121 | |
Thomas Gleixner | 90a568f | 2011-03-23 21:08:51 +0000 | [diff] [blame] | 122 | static void emma2rh_gpio_irq_disable(struct irq_data *d) |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 123 | { |
Thomas Gleixner | 90a568f | 2011-03-23 21:08:51 +0000 | [diff] [blame] | 124 | unsigned int irq = d->irq - EMMA2RH_GPIO_IRQ_BASE; |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 125 | u32 reg; |
| 126 | |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 127 | reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); |
| 128 | reg &= ~(1 << irq); |
| 129 | emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); |
| 130 | } |
| 131 | |
Thomas Gleixner | 90a568f | 2011-03-23 21:08:51 +0000 | [diff] [blame] | 132 | static void emma2rh_gpio_irq_ack(struct irq_data *d) |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 133 | { |
Thomas Gleixner | 90a568f | 2011-03-23 21:08:51 +0000 | [diff] [blame] | 134 | unsigned int irq = d->irq - EMMA2RH_GPIO_IRQ_BASE; |
| 135 | |
Shinya Kuribayashi | 8da55bb | 2009-03-21 22:06:14 +0900 | [diff] [blame] | 136 | emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq)); |
| 137 | } |
| 138 | |
Thomas Gleixner | 90a568f | 2011-03-23 21:08:51 +0000 | [diff] [blame] | 139 | static void emma2rh_gpio_irq_mask_ack(struct irq_data *d) |
Shinya Kuribayashi | 8da55bb | 2009-03-21 22:06:14 +0900 | [diff] [blame] | 140 | { |
Thomas Gleixner | 90a568f | 2011-03-23 21:08:51 +0000 | [diff] [blame] | 141 | unsigned int irq = d->irq - EMMA2RH_GPIO_IRQ_BASE; |
Shinya Kuribayashi | 49618d6 | 2008-10-24 01:35:59 +0900 | [diff] [blame] | 142 | u32 reg; |
| 143 | |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 144 | emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq)); |
Shinya Kuribayashi | 49618d6 | 2008-10-24 01:35:59 +0900 | [diff] [blame] | 145 | |
| 146 | reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); |
| 147 | reg &= ~(1 << irq); |
| 148 | emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 149 | } |
| 150 | |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 151 | struct irq_chip emma2rh_gpio_irq_controller = { |
| 152 | .name = "emma2rh_gpio_irq", |
Thomas Gleixner | 90a568f | 2011-03-23 21:08:51 +0000 | [diff] [blame] | 153 | .irq_ack = emma2rh_gpio_irq_ack, |
| 154 | .irq_mask = emma2rh_gpio_irq_disable, |
| 155 | .irq_mask_ack = emma2rh_gpio_irq_mask_ack, |
| 156 | .irq_unmask = emma2rh_gpio_irq_enable, |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 157 | }; |
| 158 | |
| 159 | void emma2rh_gpio_irq_init(void) |
| 160 | { |
| 161 | u32 i; |
| 162 | |
| 163 | for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++) |
Thomas Gleixner | e4ec798 | 2011-03-27 15:19:28 +0200 | [diff] [blame] | 164 | irq_set_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i, |
Shinya Kuribayashi | 8da55bb | 2009-03-21 22:06:14 +0900 | [diff] [blame] | 165 | &emma2rh_gpio_irq_controller, |
| 166 | handle_edge_irq, "edge"); |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 167 | } |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 168 | |
| 169 | static struct irqaction irq_cascade = { |
| 170 | .handler = no_action, |
Wu Zhangjin | 5a4a4ad | 2011-07-23 12:41:24 +0000 | [diff] [blame] | 171 | .flags = IRQF_NO_THREAD, |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 172 | .name = "cascade", |
| 173 | .dev_id = NULL, |
| 174 | .next = NULL, |
| 175 | }; |
| 176 | |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 177 | /* |
| 178 | * the first level int-handler will jump here if it is a emma2rh irq |
| 179 | */ |
| 180 | void emma2rh_irq_dispatch(void) |
| 181 | { |
| 182 | u32 intStatus; |
| 183 | u32 bitmask; |
| 184 | u32 i; |
| 185 | |
| 186 | intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_0) & |
| 187 | emma2rh_in32(EMMA2RH_BHIF_INT_EN_0); |
| 188 | |
| 189 | #ifdef EMMA2RH_SW_CASCADE |
Shinya Kuribayashi | fb2826b | 2009-03-21 22:04:21 +0900 | [diff] [blame] | 190 | if (intStatus & (1UL << EMMA2RH_SW_CASCADE)) { |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 191 | u32 swIntStatus; |
| 192 | swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT) |
| 193 | & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); |
| 194 | for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) { |
| 195 | if (swIntStatus & bitmask) { |
| 196 | do_IRQ(EMMA2RH_SW_IRQ_BASE + i); |
| 197 | return; |
| 198 | } |
| 199 | } |
| 200 | } |
Shinya Kuribayashi | fb2826b | 2009-03-21 22:04:21 +0900 | [diff] [blame] | 201 | /* Skip S/W interrupt */ |
| 202 | intStatus &= ~(1UL << EMMA2RH_SW_CASCADE); |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 203 | #endif |
| 204 | |
| 205 | for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) { |
| 206 | if (intStatus & bitmask) { |
| 207 | do_IRQ(EMMA2RH_IRQ_BASE + i); |
| 208 | return; |
| 209 | } |
| 210 | } |
| 211 | |
| 212 | intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_1) & |
| 213 | emma2rh_in32(EMMA2RH_BHIF_INT_EN_1); |
| 214 | |
| 215 | #ifdef EMMA2RH_GPIO_CASCADE |
Shinya Kuribayashi | fb2826b | 2009-03-21 22:04:21 +0900 | [diff] [blame] | 216 | if (intStatus & (1UL << (EMMA2RH_GPIO_CASCADE % 32))) { |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 217 | u32 gpioIntStatus; |
| 218 | gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST) |
| 219 | & emma2rh_in32(EMMA2RH_GPIO_INT_MASK); |
| 220 | for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) { |
| 221 | if (gpioIntStatus & bitmask) { |
| 222 | do_IRQ(EMMA2RH_GPIO_IRQ_BASE + i); |
| 223 | return; |
| 224 | } |
| 225 | } |
| 226 | } |
Shinya Kuribayashi | fb2826b | 2009-03-21 22:04:21 +0900 | [diff] [blame] | 227 | /* Skip GPIO interrupt */ |
| 228 | intStatus &= ~(1UL << (EMMA2RH_GPIO_CASCADE % 32)); |
Shinya Kuribayashi | 9ae9fd7 | 2008-10-24 01:32:40 +0900 | [diff] [blame] | 229 | #endif |
| 230 | |
| 231 | for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) { |
| 232 | if (intStatus & bitmask) { |
| 233 | do_IRQ(EMMA2RH_IRQ_BASE + i); |
| 234 | return; |
| 235 | } |
| 236 | } |
| 237 | |
| 238 | intStatus = emma2rh_in32(EMMA2RH_BHIF_INT_ST_2) & |
| 239 | emma2rh_in32(EMMA2RH_BHIF_INT_EN_2); |
| 240 | |
| 241 | for (i = 64, bitmask = 1; i < 96; i++, bitmask <<= 1) { |
| 242 | if (intStatus & bitmask) { |
| 243 | do_IRQ(EMMA2RH_IRQ_BASE + i); |
| 244 | return; |
| 245 | } |
| 246 | } |
| 247 | } |
| 248 | |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 249 | void __init arch_init_irq(void) |
| 250 | { |
| 251 | u32 reg; |
| 252 | |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 253 | /* by default, interrupts are disabled. */ |
| 254 | emma2rh_out32(EMMA2RH_BHIF_INT_EN_0, 0); |
| 255 | emma2rh_out32(EMMA2RH_BHIF_INT_EN_1, 0); |
| 256 | emma2rh_out32(EMMA2RH_BHIF_INT_EN_2, 0); |
| 257 | emma2rh_out32(EMMA2RH_BHIF_INT1_EN_0, 0); |
| 258 | emma2rh_out32(EMMA2RH_BHIF_INT1_EN_1, 0); |
| 259 | emma2rh_out32(EMMA2RH_BHIF_INT1_EN_2, 0); |
| 260 | emma2rh_out32(EMMA2RH_BHIF_SW_INT_EN, 0); |
| 261 | |
| 262 | clear_c0_status(0xff00); |
| 263 | set_c0_status(0x0400); |
| 264 | |
| 265 | #define GPIO_PCI (0xf<<15) |
| 266 | /* setup GPIO interrupt for PCI interface */ |
| 267 | /* direction input */ |
| 268 | reg = emma2rh_in32(EMMA2RH_GPIO_DIR); |
| 269 | emma2rh_out32(EMMA2RH_GPIO_DIR, reg & ~GPIO_PCI); |
| 270 | /* disable interrupt */ |
| 271 | reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); |
| 272 | emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg & ~GPIO_PCI); |
| 273 | /* level triggerd */ |
| 274 | reg = emma2rh_in32(EMMA2RH_GPIO_INT_MODE); |
| 275 | emma2rh_out32(EMMA2RH_GPIO_INT_MODE, reg | GPIO_PCI); |
| 276 | reg = emma2rh_in32(EMMA2RH_GPIO_INT_CND_A); |
| 277 | emma2rh_out32(EMMA2RH_GPIO_INT_CND_A, reg & (~GPIO_PCI)); |
| 278 | /* interrupt clear */ |
| 279 | emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~GPIO_PCI); |
| 280 | |
| 281 | /* init all controllers */ |
Shinya Kuribayashi | 9b6c04b | 2008-10-24 01:31:16 +0900 | [diff] [blame] | 282 | emma2rh_irq_init(); |
Shinya Kuribayashi | 68ed1ca | 2008-10-24 01:31:43 +0900 | [diff] [blame] | 283 | emma2rh_sw_irq_init(); |
Shinya Kuribayashi | fcb3cfe | 2008-10-24 01:32:11 +0900 | [diff] [blame] | 284 | emma2rh_gpio_irq_init(); |
Atsushi Nemoto | 97dcb82 | 2007-01-08 02:14:29 +0900 | [diff] [blame] | 285 | mips_cpu_irq_init(); |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 286 | |
| 287 | /* setup cascade interrupts */ |
| 288 | setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_SW_CASCADE, &irq_cascade); |
| 289 | setup_irq(EMMA2RH_IRQ_BASE + EMMA2RH_GPIO_CASCADE, &irq_cascade); |
Shinya Kuribayashi | 9e6f396 | 2010-06-17 20:36:13 +0900 | [diff] [blame] | 290 | setup_irq(MIPS_CPU_IRQ_BASE + 2, &irq_cascade); |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 291 | } |
| 292 | |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 293 | asmlinkage void plat_irq_dispatch(void) |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 294 | { |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 295 | unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 296 | |
| 297 | if (pending & STATUSF_IP7) |
Shinya Kuribayashi | eebacda | 2010-06-17 20:35:58 +0900 | [diff] [blame] | 298 | do_IRQ(MIPS_CPU_IRQ_BASE + 7); |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 299 | else if (pending & STATUSF_IP2) |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 300 | emma2rh_irq_dispatch(); |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 301 | else if (pending & STATUSF_IP1) |
Shinya Kuribayashi | eebacda | 2010-06-17 20:35:58 +0900 | [diff] [blame] | 302 | do_IRQ(MIPS_CPU_IRQ_BASE + 1); |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 303 | else if (pending & STATUSF_IP0) |
Shinya Kuribayashi | eebacda | 2010-06-17 20:35:58 +0900 | [diff] [blame] | 304 | do_IRQ(MIPS_CPU_IRQ_BASE + 0); |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 305 | else |
Ralf Baechle | 937a801 | 2006-10-07 19:44:33 +0100 | [diff] [blame] | 306 | spurious_interrupt(); |
dmitry pervushin | 355c471 | 2006-05-21 14:53:06 +0400 | [diff] [blame] | 307 | } |