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gem5
/
arm
/
linux-arm64-legacy
/
0aacceacf35451ffb771ec825555e98c5dce8b01
/
.
/
include
/
asm-m32r
/
cache.h
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#ifndef
_ASM_M32R_CACHE_H
#define
_ASM_M32R_CACHE_H
/* $Id$ */
/* L1 cache line size */
#define
L1_CACHE_SHIFT
4
#define
L1_CACHE_BYTES
(
1
<<
L1_CACHE_SHIFT
)
#define
L1_CACHE_SHIFT_MAX
4
#endif
/* _ASM_M32R_CACHE_H */