| /******************************************************************************* |
| * |
| * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver |
| * Copyright(c) 2013 - 2014 Intel Corporation. |
| * |
| * This program is free software; you can redistribute it and/or modify it |
| * under the terms and conditions of the GNU General Public License, |
| * version 2, as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope it will be useful, but WITHOUT |
| * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| * more details. |
| * |
| * You should have received a copy of the GNU General Public License along |
| * with this program. If not, see <http://www.gnu.org/licenses/>. |
| * |
| * The full GNU General Public License is included in this distribution in |
| * the file called "COPYING". |
| * |
| * Contact Information: |
| * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| * |
| ******************************************************************************/ |
| |
| #ifndef _I40E_REGISTER_H_ |
| #define _I40E_REGISTER_H_ |
| |
| #define I40E_GL_GP_FUSE(_i) (0x0009400C + ((_i) * 4)) /* _i=0...28 */ |
| #define I40E_GL_GP_FUSE_MAX_INDEX 28 |
| #define I40E_GL_GP_FUSE_GL_GP_FUSE_SHIFT 0 |
| #define I40E_GL_GP_FUSE_GL_GP_FUSE_MASK (0xFFFFFFFF << I40E_GL_GP_FUSE_GL_GP_FUSE_SHIFT) |
| #define I40E_GLPCI_PM_MUX_NPQ 0x0009C4F4 |
| #define I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT 0 |
| #define I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_MASK (0x7 << I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT) |
| #define I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_SHIFT 16 |
| #define I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_MASK (0x1F << I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_SHIFT) |
| #define I40E_GLPCI_PM_MUX_PFB 0x0009C4F0 |
| #define I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_SHIFT 0 |
| #define I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_MASK (0x1F << I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_SHIFT) |
| #define I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT 16 |
| #define I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_MASK (0x7 << I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT) |
| #define I40E_GLPCI_PQ_MAX_USED_SPC 0x0009C4EC |
| #define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_SHIFT 0 |
| #define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_MASK (0xFF << I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_SHIFT) |
| #define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_SHIFT 8 |
| #define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_MASK (0xFF << I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_SHIFT) |
| #define I40E_GLPCI_SPARE_BITS_0 0x0009C4F8 |
| #define I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT 0 |
| #define I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_MASK (0xFFFFFFFF << I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT) |
| #define I40E_GLPCI_SPARE_BITS_1 0x0009C4FC |
| #define I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_SHIFT 0 |
| #define I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_MASK (0xFFFFFFFF << I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_SHIFT) |
| #define I40E_PFPCI_PF_FLUSH_DONE 0x0009C800 |
| #define I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_SHIFT 0 |
| #define I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_MASK (0x1 << I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_SHIFT) |
| #define I40E_PFPCI_VF_FLUSH_DONE 0x0009C600 |
| #define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT 0 |
| #define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_MASK (0x1 << I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT) |
| #define I40E_PFPCI_VF_FLUSH_DONE1(_VF) (0x0009C600 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_PFPCI_VF_FLUSH_DONE1_MAX_INDEX 127 |
| #define I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_SHIFT 0 |
| #define I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_MASK (0x1 << I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_SHIFT) |
| #define I40E_PFPCI_VM_FLUSH_DONE 0x0009C880 |
| #define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT 0 |
| #define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_MASK (0x1 << I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT) |
| |
| #define I40E_PF_ARQBAH 0x00080180 |
| #define I40E_PF_ARQBAH_ARQBAH_SHIFT 0 |
| #define I40E_PF_ARQBAH_ARQBAH_MASK (0xFFFFFFFF << I40E_PF_ARQBAH_ARQBAH_SHIFT) |
| #define I40E_PF_ARQBAL 0x00080080 |
| #define I40E_PF_ARQBAL_ARQBAL_SHIFT 0 |
| #define I40E_PF_ARQBAL_ARQBAL_MASK (0xFFFFFFFF << I40E_PF_ARQBAL_ARQBAL_SHIFT) |
| #define I40E_PF_ARQH 0x00080380 |
| #define I40E_PF_ARQH_ARQH_SHIFT 0 |
| #define I40E_PF_ARQH_ARQH_MASK (0x3FF << I40E_PF_ARQH_ARQH_SHIFT) |
| #define I40E_PF_ARQLEN 0x00080280 |
| #define I40E_PF_ARQLEN_ARQLEN_SHIFT 0 |
| #define I40E_PF_ARQLEN_ARQLEN_MASK (0x3FF << I40E_PF_ARQLEN_ARQLEN_SHIFT) |
| #define I40E_PF_ARQLEN_ARQVFE_SHIFT 28 |
| #define I40E_PF_ARQLEN_ARQVFE_MASK (0x1 << I40E_PF_ARQLEN_ARQVFE_SHIFT) |
| #define I40E_PF_ARQLEN_ARQOVFL_SHIFT 29 |
| #define I40E_PF_ARQLEN_ARQOVFL_MASK (0x1 << I40E_PF_ARQLEN_ARQOVFL_SHIFT) |
| #define I40E_PF_ARQLEN_ARQCRIT_SHIFT 30 |
| #define I40E_PF_ARQLEN_ARQCRIT_MASK (0x1 << I40E_PF_ARQLEN_ARQCRIT_SHIFT) |
| #define I40E_PF_ARQLEN_ARQENABLE_SHIFT 31 |
| #define I40E_PF_ARQLEN_ARQENABLE_MASK (0x1 << I40E_PF_ARQLEN_ARQENABLE_SHIFT) |
| #define I40E_PF_ARQT 0x00080480 |
| #define I40E_PF_ARQT_ARQT_SHIFT 0 |
| #define I40E_PF_ARQT_ARQT_MASK (0x3FF << I40E_PF_ARQT_ARQT_SHIFT) |
| #define I40E_PF_ATQBAH 0x00080100 |
| #define I40E_PF_ATQBAH_ATQBAH_SHIFT 0 |
| #define I40E_PF_ATQBAH_ATQBAH_MASK (0xFFFFFFFF << I40E_PF_ATQBAH_ATQBAH_SHIFT) |
| #define I40E_PF_ATQBAL 0x00080000 |
| #define I40E_PF_ATQBAL_ATQBAL_SHIFT 0 |
| #define I40E_PF_ATQBAL_ATQBAL_MASK (0xFFFFFFFF << I40E_PF_ATQBAL_ATQBAL_SHIFT) |
| #define I40E_PF_ATQH 0x00080300 |
| #define I40E_PF_ATQH_ATQH_SHIFT 0 |
| #define I40E_PF_ATQH_ATQH_MASK (0x3FF << I40E_PF_ATQH_ATQH_SHIFT) |
| #define I40E_PF_ATQLEN 0x00080200 |
| #define I40E_PF_ATQLEN_ATQLEN_SHIFT 0 |
| #define I40E_PF_ATQLEN_ATQLEN_MASK (0x3FF << I40E_PF_ATQLEN_ATQLEN_SHIFT) |
| #define I40E_PF_ATQLEN_ATQVFE_SHIFT 28 |
| #define I40E_PF_ATQLEN_ATQVFE_MASK (0x1 << I40E_PF_ATQLEN_ATQVFE_SHIFT) |
| #define I40E_PF_ATQLEN_ATQOVFL_SHIFT 29 |
| #define I40E_PF_ATQLEN_ATQOVFL_MASK (0x1 << I40E_PF_ATQLEN_ATQOVFL_SHIFT) |
| #define I40E_PF_ATQLEN_ATQCRIT_SHIFT 30 |
| #define I40E_PF_ATQLEN_ATQCRIT_MASK (0x1 << I40E_PF_ATQLEN_ATQCRIT_SHIFT) |
| #define I40E_PF_ATQLEN_ATQENABLE_SHIFT 31 |
| #define I40E_PF_ATQLEN_ATQENABLE_MASK (0x1 << I40E_PF_ATQLEN_ATQENABLE_SHIFT) |
| #define I40E_PF_ATQT 0x00080400 |
| #define I40E_PF_ATQT_ATQT_SHIFT 0 |
| #define I40E_PF_ATQT_ATQT_MASK (0x3FF << I40E_PF_ATQT_ATQT_SHIFT) |
| #define I40E_VF_ARQBAH(_VF) (0x00081400 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VF_ARQBAH_MAX_INDEX 127 |
| #define I40E_VF_ARQBAH_ARQBAH_SHIFT 0 |
| #define I40E_VF_ARQBAH_ARQBAH_MASK (0xFFFFFFFF << I40E_VF_ARQBAH_ARQBAH_SHIFT) |
| #define I40E_VF_ARQBAL(_VF) (0x00080C00 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VF_ARQBAL_MAX_INDEX 127 |
| #define I40E_VF_ARQBAL_ARQBAL_SHIFT 0 |
| #define I40E_VF_ARQBAL_ARQBAL_MASK (0xFFFFFFFF << I40E_VF_ARQBAL_ARQBAL_SHIFT) |
| #define I40E_VF_ARQH(_VF) (0x00082400 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VF_ARQH_MAX_INDEX 127 |
| #define I40E_VF_ARQH_ARQH_SHIFT 0 |
| #define I40E_VF_ARQH_ARQH_MASK (0x3FF << I40E_VF_ARQH_ARQH_SHIFT) |
| #define I40E_VF_ARQLEN(_VF) (0x00081C00 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VF_ARQLEN_MAX_INDEX 127 |
| #define I40E_VF_ARQLEN_ARQLEN_SHIFT 0 |
| #define I40E_VF_ARQLEN_ARQLEN_MASK (0x3FF << I40E_VF_ARQLEN_ARQLEN_SHIFT) |
| #define I40E_VF_ARQLEN_ARQVFE_SHIFT 28 |
| #define I40E_VF_ARQLEN_ARQVFE_MASK (0x1 << I40E_VF_ARQLEN_ARQVFE_SHIFT) |
| #define I40E_VF_ARQLEN_ARQOVFL_SHIFT 29 |
| #define I40E_VF_ARQLEN_ARQOVFL_MASK (0x1 << I40E_VF_ARQLEN_ARQOVFL_SHIFT) |
| #define I40E_VF_ARQLEN_ARQCRIT_SHIFT 30 |
| #define I40E_VF_ARQLEN_ARQCRIT_MASK (0x1 << I40E_VF_ARQLEN_ARQCRIT_SHIFT) |
| #define I40E_VF_ARQLEN_ARQENABLE_SHIFT 31 |
| #define I40E_VF_ARQLEN_ARQENABLE_MASK (0x1 << I40E_VF_ARQLEN_ARQENABLE_SHIFT) |
| #define I40E_VF_ARQT(_VF) (0x00082C00 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VF_ARQT_MAX_INDEX 127 |
| #define I40E_VF_ARQT_ARQT_SHIFT 0 |
| #define I40E_VF_ARQT_ARQT_MASK (0x3FF << I40E_VF_ARQT_ARQT_SHIFT) |
| #define I40E_VF_ATQBAH(_VF) (0x00081000 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VF_ATQBAH_MAX_INDEX 127 |
| #define I40E_VF_ATQBAH_ATQBAH_SHIFT 0 |
| #define I40E_VF_ATQBAH_ATQBAH_MASK (0xFFFFFFFF << I40E_VF_ATQBAH_ATQBAH_SHIFT) |
| #define I40E_VF_ATQBAL(_VF) (0x00080800 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VF_ATQBAL_MAX_INDEX 127 |
| #define I40E_VF_ATQBAL_ATQBAL_SHIFT 0 |
| #define I40E_VF_ATQBAL_ATQBAL_MASK (0xFFFFFFFF << I40E_VF_ATQBAL_ATQBAL_SHIFT) |
| #define I40E_VF_ATQH(_VF) (0x00082000 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VF_ATQH_MAX_INDEX 127 |
| #define I40E_VF_ATQH_ATQH_SHIFT 0 |
| #define I40E_VF_ATQH_ATQH_MASK (0x3FF << I40E_VF_ATQH_ATQH_SHIFT) |
| #define I40E_VF_ATQLEN(_VF) (0x00081800 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VF_ATQLEN_MAX_INDEX 127 |
| #define I40E_VF_ATQLEN_ATQLEN_SHIFT 0 |
| #define I40E_VF_ATQLEN_ATQLEN_MASK (0x3FF << I40E_VF_ATQLEN_ATQLEN_SHIFT) |
| #define I40E_VF_ATQLEN_ATQVFE_SHIFT 28 |
| #define I40E_VF_ATQLEN_ATQVFE_MASK (0x1 << I40E_VF_ATQLEN_ATQVFE_SHIFT) |
| #define I40E_VF_ATQLEN_ATQOVFL_SHIFT 29 |
| #define I40E_VF_ATQLEN_ATQOVFL_MASK (0x1 << I40E_VF_ATQLEN_ATQOVFL_SHIFT) |
| #define I40E_VF_ATQLEN_ATQCRIT_SHIFT 30 |
| #define I40E_VF_ATQLEN_ATQCRIT_MASK (0x1 << I40E_VF_ATQLEN_ATQCRIT_SHIFT) |
| #define I40E_VF_ATQLEN_ATQENABLE_SHIFT 31 |
| #define I40E_VF_ATQLEN_ATQENABLE_MASK (0x1 << I40E_VF_ATQLEN_ATQENABLE_SHIFT) |
| #define I40E_VF_ATQT(_VF) (0x00082800 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VF_ATQT_MAX_INDEX 127 |
| #define I40E_VF_ATQT_ATQT_SHIFT 0 |
| #define I40E_VF_ATQT_ATQT_MASK (0x3FF << I40E_VF_ATQT_ATQT_SHIFT) |
| #define I40E_PRT_L2TAGSEN 0x001C0B20 |
| #define I40E_PRT_L2TAGSEN_ENABLE_SHIFT 0 |
| #define I40E_PRT_L2TAGSEN_ENABLE_MASK (0xFF << I40E_PRT_L2TAGSEN_ENABLE_SHIFT) |
| #define I40E_PFCM_LAN_ERRDATA 0x0010C080 |
| #define I40E_PFCM_LAN_ERRDATA_ERROR_CODE_SHIFT 0 |
| #define I40E_PFCM_LAN_ERRDATA_ERROR_CODE_MASK (0xF << I40E_PFCM_LAN_ERRDATA_ERROR_CODE_SHIFT) |
| #define I40E_PFCM_LAN_ERRDATA_Q_TYPE_SHIFT 4 |
| #define I40E_PFCM_LAN_ERRDATA_Q_TYPE_MASK (0x7 << I40E_PFCM_LAN_ERRDATA_Q_TYPE_SHIFT) |
| #define I40E_PFCM_LAN_ERRDATA_Q_NUM_SHIFT 8 |
| #define I40E_PFCM_LAN_ERRDATA_Q_NUM_MASK (0xFFF << I40E_PFCM_LAN_ERRDATA_Q_NUM_SHIFT) |
| #define I40E_PFCM_LAN_ERRINFO 0x0010C000 |
| #define I40E_PFCM_LAN_ERRINFO_ERROR_VALID_SHIFT 0 |
| #define I40E_PFCM_LAN_ERRINFO_ERROR_VALID_MASK (0x1 << I40E_PFCM_LAN_ERRINFO_ERROR_VALID_SHIFT) |
| #define I40E_PFCM_LAN_ERRINFO_ERROR_INST_SHIFT 4 |
| #define I40E_PFCM_LAN_ERRINFO_ERROR_INST_MASK (0x7 << I40E_PFCM_LAN_ERRINFO_ERROR_INST_SHIFT) |
| #define I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_SHIFT 8 |
| #define I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_MASK (0xFF << I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_SHIFT) |
| #define I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_SHIFT 16 |
| #define I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_MASK (0xFF << I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_SHIFT) |
| #define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT 24 |
| #define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_MASK (0xFF << I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT) |
| #define I40E_PFCM_LANCTXCTL(_pf) (0x0010C300 + ((_pf) * 4))/* _pf=0..15 */ |
| #define I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT 0 |
| #define I40E_PFCM_LANCTXCTL_QUEUE_NUM_MASK (0xFFF << I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT) |
| #define I40E_PFCM_LANCTXCTL_SUB_LINE_SHIFT 12 |
| #define I40E_PFCM_LANCTXCTL_SUB_LINE_MASK (0x7 << I40E_PFCM_LANCTXCTL_SUB_LINE_SHIFT) |
| #define I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT 15 |
| #define I40E_PFCM_LANCTXCTL_QUEUE_TYPE_MASK (0x3 << I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT) |
| #define I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT 17 |
| #define I40E_PFCM_LANCTXCTL_OP_CODE_MASK (0x3 << I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT) |
| #define I40E_PFCM_LANCTXDATA(_i, _pf) (0x0010C100 + ((_i) * 4) + ((_pf) * 16))/* _i=0...3 _pf=0..15 */ |
| #define I40E_PFCM_LANCTXDATA_MAX_INDEX 3 |
| #define I40E_PFCM_LANCTXDATA_DATA_SHIFT 0 |
| #define I40E_PFCM_LANCTXDATA_DATA_MASK (0xFFFFFFFF << I40E_PFCM_LANCTXDATA_DATA_SHIFT) |
| #define I40E_PFCM_LANCTXSTAT(_pf) (0x0010C380 + ((_pf) * 4))/* _pf=0..15 */ |
| #define I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT 0 |
| #define I40E_PFCM_LANCTXSTAT_CTX_DONE_MASK (0x1 << I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT) |
| #define I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT 1 |
| #define I40E_PFCM_LANCTXSTAT_CTX_MISS_MASK (0x1 << I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT) |
| #define I40E_PFCM_PE_ERRDATA 0x00138D00 |
| #define I40E_PFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0 |
| #define I40E_PFCM_PE_ERRDATA_ERROR_CODE_MASK (0xF << I40E_PFCM_PE_ERRDATA_ERROR_CODE_SHIFT) |
| #define I40E_PFCM_PE_ERRDATA_Q_TYPE_SHIFT 4 |
| #define I40E_PFCM_PE_ERRDATA_Q_TYPE_MASK (0x7 << I40E_PFCM_PE_ERRDATA_Q_TYPE_SHIFT) |
| #define I40E_PFCM_PE_ERRDATA_Q_NUM_SHIFT 8 |
| #define I40E_PFCM_PE_ERRDATA_Q_NUM_MASK (0x3FFFF << I40E_PFCM_PE_ERRDATA_Q_NUM_SHIFT) |
| #define I40E_PFCM_PE_ERRINFO 0x00138C80 |
| #define I40E_PFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0 |
| #define I40E_PFCM_PE_ERRINFO_ERROR_VALID_MASK (0x1 << I40E_PFCM_PE_ERRINFO_ERROR_VALID_SHIFT) |
| #define I40E_PFCM_PE_ERRINFO_ERROR_INST_SHIFT 4 |
| #define I40E_PFCM_PE_ERRINFO_ERROR_INST_MASK (0x7 << I40E_PFCM_PE_ERRINFO_ERROR_INST_SHIFT) |
| #define I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8 |
| #define I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK (0xFF << I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT) |
| #define I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16 |
| #define I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK (0xFF << I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT) |
| #define I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24 |
| #define I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK (0xFF << I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT) |
| #define I40E_VFCM_PE_ERRDATA1(_VF) (0x00138800 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VFCM_PE_ERRDATA1_MAX_INDEX 127 |
| #define I40E_VFCM_PE_ERRDATA1_ERROR_CODE_SHIFT 0 |
| #define I40E_VFCM_PE_ERRDATA1_ERROR_CODE_MASK (0xF << I40E_VFCM_PE_ERRDATA1_ERROR_CODE_SHIFT) |
| #define I40E_VFCM_PE_ERRDATA1_Q_TYPE_SHIFT 4 |
| #define I40E_VFCM_PE_ERRDATA1_Q_TYPE_MASK (0x7 << I40E_VFCM_PE_ERRDATA1_Q_TYPE_SHIFT) |
| #define I40E_VFCM_PE_ERRDATA1_Q_NUM_SHIFT 8 |
| #define I40E_VFCM_PE_ERRDATA1_Q_NUM_MASK (0x3FFFF << I40E_VFCM_PE_ERRDATA1_Q_NUM_SHIFT) |
| #define I40E_VFCM_PE_ERRINFO1(_VF) (0x00138400 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VFCM_PE_ERRINFO1_MAX_INDEX 127 |
| #define I40E_VFCM_PE_ERRINFO1_ERROR_VALID_SHIFT 0 |
| #define I40E_VFCM_PE_ERRINFO1_ERROR_VALID_MASK (0x1 << I40E_VFCM_PE_ERRINFO1_ERROR_VALID_SHIFT) |
| #define I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT 4 |
| #define I40E_VFCM_PE_ERRINFO1_ERROR_INST_MASK (0x7 << I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT) |
| #define I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT 8 |
| #define I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_MASK (0xFF << I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT) |
| #define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT 16 |
| #define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_MASK (0xFF << I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT) |
| #define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT 24 |
| #define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_MASK (0xFF << I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT) |
| #define I40E_GLDCB_GENC 0x00083044 |
| #define I40E_GLDCB_GENC_PCIRTT_SHIFT 0 |
| #define I40E_GLDCB_GENC_PCIRTT_MASK (0xFFFF << I40E_GLDCB_GENC_PCIRTT_SHIFT) |
| #define I40E_GLDCB_RUPTI 0x00122618 |
| #define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT 0 |
| #define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_MASK (0xFFFFFFFF << I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT) |
| #define I40E_PRTDCB_FCCFG 0x001E4640 |
| #define I40E_PRTDCB_FCCFG_TFCE_SHIFT 3 |
| #define I40E_PRTDCB_FCCFG_TFCE_MASK (0x3 << I40E_PRTDCB_FCCFG_TFCE_SHIFT) |
| #define I40E_PRTDCB_FCRTV 0x001E4600 |
| #define I40E_PRTDCB_FCRTV_FC_REFRESH_TH_SHIFT 0 |
| #define I40E_PRTDCB_FCRTV_FC_REFRESH_TH_MASK (0xFFFF << I40E_PRTDCB_FCRTV_FC_REFRESH_TH_SHIFT) |
| #define I40E_PRTDCB_FCTTVN(_i) (0x001E4580 + ((_i) * 32)) /* _i=0...3 */ |
| #define I40E_PRTDCB_FCTTVN_MAX_INDEX 3 |
| #define I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT 0 |
| #define I40E_PRTDCB_FCTTVN_TTV_2N_MASK (0xFFFF << I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT) |
| #define I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT 16 |
| #define I40E_PRTDCB_FCTTVN_TTV_2N_P1_MASK (0xFFFF << I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT) |
| #define I40E_PRTDCB_GENC 0x00083000 |
| #define I40E_PRTDCB_GENC_RESERVED_1_SHIFT 0 |
| #define I40E_PRTDCB_GENC_RESERVED_1_MASK (0x3 << I40E_PRTDCB_GENC_RESERVED_1_SHIFT) |
| #define I40E_PRTDCB_GENC_NUMTC_SHIFT 2 |
| #define I40E_PRTDCB_GENC_NUMTC_MASK (0xF << I40E_PRTDCB_GENC_NUMTC_SHIFT) |
| #define I40E_PRTDCB_GENC_FCOEUP_SHIFT 6 |
| #define I40E_PRTDCB_GENC_FCOEUP_MASK (0x7 << I40E_PRTDCB_GENC_FCOEUP_SHIFT) |
| #define I40E_PRTDCB_GENC_FCOEUP_VALID_SHIFT 9 |
| #define I40E_PRTDCB_GENC_FCOEUP_VALID_MASK (0x1 << I40E_PRTDCB_GENC_FCOEUP_VALID_SHIFT) |
| #define I40E_PRTDCB_GENC_PFCLDA_SHIFT 16 |
| #define I40E_PRTDCB_GENC_PFCLDA_MASK (0xFFFF << I40E_PRTDCB_GENC_PFCLDA_SHIFT) |
| #define I40E_PRTDCB_GENS 0x00083020 |
| #define I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT 0 |
| #define I40E_PRTDCB_GENS_DCBX_STATUS_MASK (0x7 << I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT) |
| #define I40E_PRTDCB_MFLCN 0x001E2400 |
| #define I40E_PRTDCB_MFLCN_PMCF_SHIFT 0 |
| #define I40E_PRTDCB_MFLCN_PMCF_MASK (0x1 << I40E_PRTDCB_MFLCN_PMCF_SHIFT) |
| #define I40E_PRTDCB_MFLCN_DPF_SHIFT 1 |
| #define I40E_PRTDCB_MFLCN_DPF_MASK (0x1 << I40E_PRTDCB_MFLCN_DPF_SHIFT) |
| #define I40E_PRTDCB_MFLCN_RPFCM_SHIFT 2 |
| #define I40E_PRTDCB_MFLCN_RPFCM_MASK (0x1 << I40E_PRTDCB_MFLCN_RPFCM_SHIFT) |
| #define I40E_PRTDCB_MFLCN_RFCE_SHIFT 3 |
| #define I40E_PRTDCB_MFLCN_RFCE_MASK (0x1 << I40E_PRTDCB_MFLCN_RFCE_SHIFT) |
| #define I40E_PRTDCB_MFLCN_RPFCE_SHIFT 4 |
| #define I40E_PRTDCB_MFLCN_RPFCE_MASK (0xFF << I40E_PRTDCB_MFLCN_RPFCE_SHIFT) |
| #define I40E_PRTDCB_RETSC 0x001223E0 |
| #define I40E_PRTDCB_RETSC_ETS_MODE_SHIFT 0 |
| #define I40E_PRTDCB_RETSC_ETS_MODE_MASK (0x1 << I40E_PRTDCB_RETSC_ETS_MODE_SHIFT) |
| #define I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT 1 |
| #define I40E_PRTDCB_RETSC_NON_ETS_MODE_MASK (0x1 << I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT) |
| #define I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT 2 |
| #define I40E_PRTDCB_RETSC_ETS_MAX_EXP_MASK (0xF << I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT) |
| #define I40E_PRTDCB_RETSC_LLTC_SHIFT 8 |
| #define I40E_PRTDCB_RETSC_LLTC_MASK (0xFF << I40E_PRTDCB_RETSC_LLTC_SHIFT) |
| #define I40E_PRTDCB_RETSTCC(_i) (0x00122180 + ((_i) * 32)) /* _i=0...7 */ |
| #define I40E_PRTDCB_RETSTCC_MAX_INDEX 7 |
| #define I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT 0 |
| #define I40E_PRTDCB_RETSTCC_BWSHARE_MASK (0x7F << I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) |
| #define I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT 30 |
| #define I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK (0x1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) |
| #define I40E_PRTDCB_RETSTCC_ETSTC_SHIFT 31 |
| #define I40E_PRTDCB_RETSTCC_ETSTC_MASK (0x1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) |
| #define I40E_PRTDCB_RPPMC 0x001223A0 |
| #define I40E_PRTDCB_RPPMC_LANRPPM_SHIFT 0 |
| #define I40E_PRTDCB_RPPMC_LANRPPM_MASK (0xFF << I40E_PRTDCB_RPPMC_LANRPPM_SHIFT) |
| #define I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT 8 |
| #define I40E_PRTDCB_RPPMC_RDMARPPM_MASK (0xFF << I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT) |
| #define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT 16 |
| #define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK (0xFF << I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT) |
| #define I40E_PRTDCB_RUP 0x001C0B00 |
| #define I40E_PRTDCB_RUP_NOVLANUP_SHIFT 0 |
| #define I40E_PRTDCB_RUP_NOVLANUP_MASK (0x7 << I40E_PRTDCB_RUP_NOVLANUP_SHIFT) |
| #define I40E_PRTDCB_RUP2TC 0x001C09A0 |
| #define I40E_PRTDCB_RUP2TC_UP0TC_SHIFT 0 |
| #define I40E_PRTDCB_RUP2TC_UP0TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP0TC_SHIFT) |
| #define I40E_PRTDCB_RUP2TC_UP1TC_SHIFT 3 |
| #define I40E_PRTDCB_RUP2TC_UP1TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP1TC_SHIFT) |
| #define I40E_PRTDCB_RUP2TC_UP2TC_SHIFT 6 |
| #define I40E_PRTDCB_RUP2TC_UP2TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP2TC_SHIFT) |
| #define I40E_PRTDCB_RUP2TC_UP3TC_SHIFT 9 |
| #define I40E_PRTDCB_RUP2TC_UP3TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP3TC_SHIFT) |
| #define I40E_PRTDCB_RUP2TC_UP4TC_SHIFT 12 |
| #define I40E_PRTDCB_RUP2TC_UP4TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP4TC_SHIFT) |
| #define I40E_PRTDCB_RUP2TC_UP5TC_SHIFT 15 |
| #define I40E_PRTDCB_RUP2TC_UP5TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP5TC_SHIFT) |
| #define I40E_PRTDCB_RUP2TC_UP6TC_SHIFT 18 |
| #define I40E_PRTDCB_RUP2TC_UP6TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP6TC_SHIFT) |
| #define I40E_PRTDCB_RUP2TC_UP7TC_SHIFT 21 |
| #define I40E_PRTDCB_RUP2TC_UP7TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP7TC_SHIFT) |
| #define I40E_PRTDCB_TC2PFC 0x001C0980 |
| #define I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT 0 |
| #define I40E_PRTDCB_TC2PFC_TC2PFC_MASK (0xFF << I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT) |
| #define I40E_PRTDCB_TCPMC 0x000A21A0 |
| #define I40E_PRTDCB_TCPMC_CPM_SHIFT 0 |
| #define I40E_PRTDCB_TCPMC_CPM_MASK (0x1FFF << I40E_PRTDCB_TCPMC_CPM_SHIFT) |
| #define I40E_PRTDCB_TCPMC_LLTC_SHIFT 13 |
| #define I40E_PRTDCB_TCPMC_LLTC_MASK (0xFF << I40E_PRTDCB_TCPMC_LLTC_SHIFT) |
| #define I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT 30 |
| #define I40E_PRTDCB_TCPMC_TCPM_MODE_MASK (0x1 << I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT) |
| #define I40E_PRTDCB_TCWSTC(_i) (0x000A2040 + ((_i) * 32)) /* _i=0...7 */ |
| #define I40E_PRTDCB_TCWSTC_MAX_INDEX 7 |
| #define I40E_PRTDCB_TCWSTC_MSTC_SHIFT 0 |
| #define I40E_PRTDCB_TCWSTC_MSTC_MASK (0xFFFFF << I40E_PRTDCB_TCWSTC_MSTC_SHIFT) |
| #define I40E_PRTDCB_TDPMC 0x000A0180 |
| #define I40E_PRTDCB_TDPMC_DPM_SHIFT 0 |
| #define I40E_PRTDCB_TDPMC_DPM_MASK (0xFF << I40E_PRTDCB_TDPMC_DPM_SHIFT) |
| #define I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT 30 |
| #define I40E_PRTDCB_TDPMC_TCPM_MODE_MASK (0x1 << I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT) |
| #define I40E_PRTDCB_TDPUC 0x00044100 |
| #define I40E_PRTDCB_TDPUC_MAX_TXFRAME_SHIFT 0 |
| #define I40E_PRTDCB_TDPUC_MAX_TXFRAME_MASK (0xFFFF << I40E_PRTDCB_TDPUC_MAX_TXFRAME_SHIFT) |
| #define I40E_PRTDCB_TETSC_TCB 0x000AE060 |
| #define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT 0 |
| #define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_MASK (0x1 << I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT) |
| #define I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT 8 |
| #define I40E_PRTDCB_TETSC_TCB_LLTC_MASK (0xFF << I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT) |
| #define I40E_PRTDCB_TETSC_TPB 0x00098060 |
| #define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT 0 |
| #define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_MASK (0x1 << I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT) |
| #define I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT 8 |
| #define I40E_PRTDCB_TETSC_TPB_LLTC_MASK (0xFF << I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT) |
| #define I40E_PRTDCB_TFCS 0x001E4560 |
| #define I40E_PRTDCB_TFCS_TXOFF_SHIFT 0 |
| #define I40E_PRTDCB_TFCS_TXOFF_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF_SHIFT) |
| #define I40E_PRTDCB_TFCS_TXOFF0_SHIFT 8 |
| #define I40E_PRTDCB_TFCS_TXOFF0_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF0_SHIFT) |
| #define I40E_PRTDCB_TFCS_TXOFF1_SHIFT 9 |
| #define I40E_PRTDCB_TFCS_TXOFF1_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF1_SHIFT) |
| #define I40E_PRTDCB_TFCS_TXOFF2_SHIFT 10 |
| #define I40E_PRTDCB_TFCS_TXOFF2_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF2_SHIFT) |
| #define I40E_PRTDCB_TFCS_TXOFF3_SHIFT 11 |
| #define I40E_PRTDCB_TFCS_TXOFF3_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF3_SHIFT) |
| #define I40E_PRTDCB_TFCS_TXOFF4_SHIFT 12 |
| #define I40E_PRTDCB_TFCS_TXOFF4_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF4_SHIFT) |
| #define I40E_PRTDCB_TFCS_TXOFF5_SHIFT 13 |
| #define I40E_PRTDCB_TFCS_TXOFF5_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF5_SHIFT) |
| #define I40E_PRTDCB_TFCS_TXOFF6_SHIFT 14 |
| #define I40E_PRTDCB_TFCS_TXOFF6_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF6_SHIFT) |
| #define I40E_PRTDCB_TFCS_TXOFF7_SHIFT 15 |
| #define I40E_PRTDCB_TFCS_TXOFF7_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF7_SHIFT) |
| #define I40E_PRTDCB_TFWSTC(_i) (0x000A0040 + ((_i) * 32)) /* _i=0...7 */ |
| #define I40E_PRTDCB_TFWSTC_MAX_INDEX 7 |
| #define I40E_PRTDCB_TFWSTC_MSTC_SHIFT 0 |
| #define I40E_PRTDCB_TFWSTC_MSTC_MASK (0xFFFFF << I40E_PRTDCB_TFWSTC_MSTC_SHIFT) |
| #define I40E_PRTDCB_TPFCTS(_i) (0x001E4660 + ((_i) * 32)) /* _i=0...7 */ |
| #define I40E_PRTDCB_TPFCTS_MAX_INDEX 7 |
| #define I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT 0 |
| #define I40E_PRTDCB_TPFCTS_PFCTIMER_MASK (0x3FFF << I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT) |
| #define I40E_GLFCOE_RCTL 0x00269B94 |
| #define I40E_GLFCOE_RCTL_FCOEVER_SHIFT 0 |
| #define I40E_GLFCOE_RCTL_FCOEVER_MASK (0xF << I40E_GLFCOE_RCTL_FCOEVER_SHIFT) |
| #define I40E_GLFCOE_RCTL_SAVBAD_SHIFT 4 |
| #define I40E_GLFCOE_RCTL_SAVBAD_MASK (0x1 << I40E_GLFCOE_RCTL_SAVBAD_SHIFT) |
| #define I40E_GLFCOE_RCTL_ICRC_SHIFT 5 |
| #define I40E_GLFCOE_RCTL_ICRC_MASK (0x1 << I40E_GLFCOE_RCTL_ICRC_SHIFT) |
| #define I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT 16 |
| #define I40E_GLFCOE_RCTL_MAX_SIZE_MASK (0x3FFF << I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT) |
| #define I40E_GL_FWSTS 0x00083048 |
| #define I40E_GL_FWSTS_FWS0B_SHIFT 0 |
| #define I40E_GL_FWSTS_FWS0B_MASK (0xFF << I40E_GL_FWSTS_FWS0B_SHIFT) |
| #define I40E_GL_FWSTS_FWRI_SHIFT 9 |
| #define I40E_GL_FWSTS_FWRI_MASK (0x1 << I40E_GL_FWSTS_FWRI_SHIFT) |
| #define I40E_GL_FWSTS_FWS1B_SHIFT 16 |
| #define I40E_GL_FWSTS_FWS1B_MASK (0xFF << I40E_GL_FWSTS_FWS1B_SHIFT) |
| #define I40E_GLGEN_CLKSTAT 0x000B8184 |
| #define I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT 0 |
| #define I40E_GLGEN_CLKSTAT_CLKMODE_MASK (0x1 << I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT) |
| #define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT 4 |
| #define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_MASK (0x3 << I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT) |
| #define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT 8 |
| #define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_MASK (0x7 << I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT) |
| #define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT 12 |
| #define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_MASK (0x7 << I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT) |
| #define I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_SHIFT 16 |
| #define I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_MASK (0x7 << I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_SHIFT) |
| #define I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_SHIFT 20 |
| #define I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_MASK (0x7 << I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_SHIFT) |
| #define I40E_GLGEN_GPIO_CTL(_i) (0x00088100 + ((_i) * 4)) /* _i=0...29 */ |
| #define I40E_GLGEN_GPIO_CTL_MAX_INDEX 29 |
| #define I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT 0 |
| #define I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK (0x3 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT) |
| #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT 3 |
| #define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK (0x1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT) |
| #define I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT 4 |
| #define I40E_GLGEN_GPIO_CTL_PIN_DIR_MASK (0x1 << I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT) |
| #define I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT 5 |
| #define I40E_GLGEN_GPIO_CTL_TRI_CTL_MASK (0x1 << I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT) |
| #define I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT 6 |
| #define I40E_GLGEN_GPIO_CTL_OUT_CTL_MASK (0x1 << I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT) |
| #define I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT 7 |
| #define I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK (0x7 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) |
| #define I40E_GLGEN_GPIO_CTL_LED_INVRT_SHIFT 10 |
| #define I40E_GLGEN_GPIO_CTL_LED_INVRT_MASK (0x1 << I40E_GLGEN_GPIO_CTL_LED_INVRT_SHIFT) |
| #define I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT 11 |
| #define I40E_GLGEN_GPIO_CTL_LED_BLINK_MASK (0x1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT) |
| #define I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT 12 |
| #define I40E_GLGEN_GPIO_CTL_LED_MODE_MASK (0xF << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) |
| #define I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT 17 |
| #define I40E_GLGEN_GPIO_CTL_INT_MODE_MASK (0x3 << I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT) |
| #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT 19 |
| #define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_MASK (0x1 << I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT) |
| #define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT 20 |
| #define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_MASK (0x3F << I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT) |
| #define I40E_GLGEN_GPIO_SET 0x00088184 |
| #define I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT 0 |
| #define I40E_GLGEN_GPIO_SET_GPIO_INDX_MASK (0x1F << I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT) |
| #define I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT 5 |
| #define I40E_GLGEN_GPIO_SET_SDP_DATA_MASK (0x1 << I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT) |
| #define I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT 6 |
| #define I40E_GLGEN_GPIO_SET_DRIVE_SDP_MASK (0x1 << I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT) |
| #define I40E_GLGEN_GPIO_STAT 0x0008817C |
| #define I40E_GLGEN_GPIO_STAT_GPIO_VALUE_SHIFT 0 |
| #define I40E_GLGEN_GPIO_STAT_GPIO_VALUE_MASK (0x3FFFFFFF << I40E_GLGEN_GPIO_STAT_GPIO_VALUE_SHIFT) |
| #define I40E_GLGEN_GPIO_TRANSIT 0x00088180 |
| #define I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_SHIFT 0 |
| #define I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_MASK (0x3FFFFFFF << I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_SHIFT) |
| #define I40E_GLGEN_I2CCMD(_i) (0x000881E0 + ((_i) * 4)) /* _i=0...3 */ |
| #define I40E_GLGEN_I2CCMD_MAX_INDEX 3 |
| #define I40E_GLGEN_I2CCMD_DATA_SHIFT 0 |
| #define I40E_GLGEN_I2CCMD_DATA_MASK (0xFFFF << I40E_GLGEN_I2CCMD_DATA_SHIFT) |
| #define I40E_GLGEN_I2CCMD_REGADD_SHIFT 16 |
| #define I40E_GLGEN_I2CCMD_REGADD_MASK (0xFF << I40E_GLGEN_I2CCMD_REGADD_SHIFT) |
| #define I40E_GLGEN_I2CCMD_PHYADD_SHIFT 24 |
| #define I40E_GLGEN_I2CCMD_PHYADD_MASK (0x7 << I40E_GLGEN_I2CCMD_PHYADD_SHIFT) |
| #define I40E_GLGEN_I2CCMD_OP_SHIFT 27 |
| #define I40E_GLGEN_I2CCMD_OP_MASK (0x1 << I40E_GLGEN_I2CCMD_OP_SHIFT) |
| #define I40E_GLGEN_I2CCMD_RESET_SHIFT 28 |
| #define I40E_GLGEN_I2CCMD_RESET_MASK (0x1 << I40E_GLGEN_I2CCMD_RESET_SHIFT) |
| #define I40E_GLGEN_I2CCMD_R_SHIFT 29 |
| #define I40E_GLGEN_I2CCMD_R_MASK (0x1 << I40E_GLGEN_I2CCMD_R_SHIFT) |
| #define I40E_GLGEN_I2CCMD_E_SHIFT 31 |
| #define I40E_GLGEN_I2CCMD_E_MASK (0x1 << I40E_GLGEN_I2CCMD_E_SHIFT) |
| #define I40E_GLGEN_I2CPARAMS(_i) (0x000881AC + ((_i) * 4)) /* _i=0...3 */ |
| #define I40E_GLGEN_I2CPARAMS_MAX_INDEX 3 |
| #define I40E_GLGEN_I2CPARAMS_WRITE_TIME_SHIFT 0 |
| #define I40E_GLGEN_I2CPARAMS_WRITE_TIME_MASK (0x1F << I40E_GLGEN_I2CPARAMS_WRITE_TIME_SHIFT) |
| #define I40E_GLGEN_I2CPARAMS_READ_TIME_SHIFT 5 |
| #define I40E_GLGEN_I2CPARAMS_READ_TIME_MASK (0x7 << I40E_GLGEN_I2CPARAMS_READ_TIME_SHIFT) |
| #define I40E_GLGEN_I2CPARAMS_I2CBB_EN_SHIFT 8 |
| #define I40E_GLGEN_I2CPARAMS_I2CBB_EN_MASK (0x1 << I40E_GLGEN_I2CPARAMS_I2CBB_EN_SHIFT) |
| #define I40E_GLGEN_I2CPARAMS_CLK_SHIFT 9 |
| #define I40E_GLGEN_I2CPARAMS_CLK_MASK (0x1 << I40E_GLGEN_I2CPARAMS_CLK_SHIFT) |
| #define I40E_GLGEN_I2CPARAMS_DATA_OUT_SHIFT 10 |
| #define I40E_GLGEN_I2CPARAMS_DATA_OUT_MASK (0x1 << I40E_GLGEN_I2CPARAMS_DATA_OUT_SHIFT) |
| #define I40E_GLGEN_I2CPARAMS_DATA_OE_N_SHIFT 11 |
| #define I40E_GLGEN_I2CPARAMS_DATA_OE_N_MASK (0x1 << I40E_GLGEN_I2CPARAMS_DATA_OE_N_SHIFT) |
| #define I40E_GLGEN_I2CPARAMS_DATA_IN_SHIFT 12 |
| #define I40E_GLGEN_I2CPARAMS_DATA_IN_MASK (0x1 << I40E_GLGEN_I2CPARAMS_DATA_IN_SHIFT) |
| #define I40E_GLGEN_I2CPARAMS_CLK_OE_N_SHIFT 13 |
| #define I40E_GLGEN_I2CPARAMS_CLK_OE_N_MASK (0x1 << I40E_GLGEN_I2CPARAMS_CLK_OE_N_SHIFT) |
| #define I40E_GLGEN_I2CPARAMS_CLK_IN_SHIFT 14 |
| #define I40E_GLGEN_I2CPARAMS_CLK_IN_MASK (0x1 << I40E_GLGEN_I2CPARAMS_CLK_IN_SHIFT) |
| #define I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_SHIFT 15 |
| #define I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_MASK (0x1 << I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_SHIFT) |
| #define I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_SHIFT 31 |
| #define I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_MASK (0x1 << I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_SHIFT) |
| #define I40E_GLGEN_LED_CTL 0x00088178 |
| #define I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT 0 |
| #define I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_MASK (0x1 << I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT) |
| #define I40E_GLGEN_MDIO_CTRL(_i) (0x000881D0 + ((_i) * 4)) /* _i=0...3 */ |
| #define I40E_GLGEN_MDIO_CTRL_MAX_INDEX 3 |
| #define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT 0 |
| #define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_MASK (0x1FFFF << I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT) |
| #define I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT 17 |
| #define I40E_GLGEN_MDIO_CTRL_CONTMDC_MASK (0x1 << I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT) |
| #define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT 18 |
| #define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_MASK (0x3FFF << I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT) |
| #define I40E_GLGEN_MDIO_I2C_SEL(_i) (0x000881C0 + ((_i) * 4)) /* _i=0...3 */ |
| #define I40E_GLGEN_MDIO_I2C_SEL_MAX_INDEX 3 |
| #define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT 0 |
| #define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_MASK (0x1 << I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT) |
| #define I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT 1 |
| #define I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_MASK (0xF << I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT) |
| #define I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT 5 |
| #define I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_MASK (0x1F << I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT) |
| #define I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_SHIFT 10 |
| #define I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_MASK (0x1F << I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_SHIFT) |
| #define I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_SHIFT 15 |
| #define I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_MASK (0x1F << I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_SHIFT) |
| #define I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_SHIFT 20 |
| #define I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_MASK (0x1F << I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_SHIFT) |
| #define I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_SHIFT 25 |
| #define I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_MASK (0xF << I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_SHIFT) |
| #define I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_SHIFT 31 |
| #define I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_MASK (0x1 << I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_SHIFT) |
| #define I40E_GLGEN_MSCA(_i) (0x0008818C + ((_i) * 4)) /* _i=0...3 */ |
| #define I40E_GLGEN_MSCA_MAX_INDEX 3 |
| #define I40E_GLGEN_MSCA_MDIADD_SHIFT 0 |
| #define I40E_GLGEN_MSCA_MDIADD_MASK (0xFFFF << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
| #define I40E_GLGEN_MSCA_DEVADD_SHIFT 16 |
| #define I40E_GLGEN_MSCA_DEVADD_MASK (0x1F << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
| #define I40E_GLGEN_MSCA_PHYADD_SHIFT 21 |
| #define I40E_GLGEN_MSCA_PHYADD_MASK (0x1F << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
| #define I40E_GLGEN_MSCA_OPCODE_SHIFT 26 |
| #define I40E_GLGEN_MSCA_OPCODE_MASK (0x3 << I40E_GLGEN_MSCA_OPCODE_SHIFT) |
| #define I40E_GLGEN_MSCA_STCODE_SHIFT 28 |
| #define I40E_GLGEN_MSCA_STCODE_MASK (0x3 << I40E_GLGEN_MSCA_STCODE_SHIFT) |
| #define I40E_GLGEN_MSCA_MDICMD_SHIFT 30 |
| #define I40E_GLGEN_MSCA_MDICMD_MASK (0x1 << I40E_GLGEN_MSCA_MDICMD_SHIFT) |
| #define I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT 31 |
| #define I40E_GLGEN_MSCA_MDIINPROGEN_MASK (0x1 << I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT) |
| #define I40E_GLGEN_MSRWD(_i) (0x0008819C + ((_i) * 4)) /* _i=0...3 */ |
| #define I40E_GLGEN_MSRWD_MAX_INDEX 3 |
| #define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0 |
| #define I40E_GLGEN_MSRWD_MDIWRDATA_MASK (0xFFFF << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT) |
| #define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16 |
| #define I40E_GLGEN_MSRWD_MDIRDDATA_MASK (0xFFFF << I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT) |
| #define I40E_GLGEN_PCIFCNCNT 0x001C0AB4 |
| #define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0 |
| #define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK (0x1F << I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT) |
| #define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT 16 |
| #define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_MASK (0xFF << I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT) |
| #define I40E_GLGEN_PE_ENA 0x000B81A0 |
| #define I40E_GLGEN_PE_ENA_PE_ENA_SHIFT 0 |
| #define I40E_GLGEN_PE_ENA_PE_ENA_MASK (0x1 << I40E_GLGEN_PE_ENA_PE_ENA_SHIFT) |
| #define I40E_GLGEN_PE_ENA_PE_CLK_SRC_SEL_SHIFT 1 |
| #define I40E_GLGEN_PE_ENA_PE_CLK_SRC_SEL_MASK (0x3 << I40E_GLGEN_PE_ENA_PE_CLK_SRC_SEL_SHIFT) |
| #define I40E_GLGEN_RSTAT 0x000B8188 |
| #define I40E_GLGEN_RSTAT_DEVSTATE_SHIFT 0 |
| #define I40E_GLGEN_RSTAT_DEVSTATE_MASK (0x3 << I40E_GLGEN_RSTAT_DEVSTATE_SHIFT) |
| #define I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT 2 |
| #define I40E_GLGEN_RSTAT_RESET_TYPE_MASK (0x3 << I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT) |
| #define I40E_GLGEN_RSTAT_CORERCNT_SHIFT 4 |
| #define I40E_GLGEN_RSTAT_CORERCNT_MASK (0x3 << I40E_GLGEN_RSTAT_CORERCNT_SHIFT) |
| #define I40E_GLGEN_RSTAT_GLOBRCNT_SHIFT 6 |
| #define I40E_GLGEN_RSTAT_GLOBRCNT_MASK (0x3 << I40E_GLGEN_RSTAT_GLOBRCNT_SHIFT) |
| #define I40E_GLGEN_RSTAT_EMPRCNT_SHIFT 8 |
| #define I40E_GLGEN_RSTAT_EMPRCNT_MASK (0x3 << I40E_GLGEN_RSTAT_EMPRCNT_SHIFT) |
| #define I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT 10 |
| #define I40E_GLGEN_RSTAT_TIME_TO_RST_MASK (0x3F << I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT) |
| #define I40E_GLGEN_RSTCTL 0x000B8180 |
| #define I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT 0 |
| #define I40E_GLGEN_RSTCTL_GRSTDEL_MASK (0x3F << I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT) |
| #define I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT 8 |
| #define I40E_GLGEN_RSTCTL_ECC_RST_ENA_MASK (0x1 << I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT) |
| #define I40E_GLGEN_RSTENA_EMP 0x000B818C |
| #define I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_SHIFT 0 |
| #define I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK (0x1 << I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_SHIFT) |
| #define I40E_GLGEN_RTRIG 0x000B8190 |
| #define I40E_GLGEN_RTRIG_CORER_SHIFT 0 |
| #define I40E_GLGEN_RTRIG_CORER_MASK (0x1 << I40E_GLGEN_RTRIG_CORER_SHIFT) |
| #define I40E_GLGEN_RTRIG_GLOBR_SHIFT 1 |
| #define I40E_GLGEN_RTRIG_GLOBR_MASK (0x1 << I40E_GLGEN_RTRIG_GLOBR_SHIFT) |
| #define I40E_GLGEN_RTRIG_EMPFWR_SHIFT 2 |
| #define I40E_GLGEN_RTRIG_EMPFWR_MASK (0x1 << I40E_GLGEN_RTRIG_EMPFWR_SHIFT) |
| #define I40E_GLGEN_STAT 0x000B612C |
| #define I40E_GLGEN_STAT_HWRSVD0_SHIFT 0 |
| #define I40E_GLGEN_STAT_HWRSVD0_MASK (0x3 << I40E_GLGEN_STAT_HWRSVD0_SHIFT) |
| #define I40E_GLGEN_STAT_DCBEN_SHIFT 2 |
| #define I40E_GLGEN_STAT_DCBEN_MASK (0x1 << I40E_GLGEN_STAT_DCBEN_SHIFT) |
| #define I40E_GLGEN_STAT_VTEN_SHIFT 3 |
| #define I40E_GLGEN_STAT_VTEN_MASK (0x1 << I40E_GLGEN_STAT_VTEN_SHIFT) |
| #define I40E_GLGEN_STAT_FCOEN_SHIFT 4 |
| #define I40E_GLGEN_STAT_FCOEN_MASK (0x1 << I40E_GLGEN_STAT_FCOEN_SHIFT) |
| #define I40E_GLGEN_STAT_EVBEN_SHIFT 5 |
| #define I40E_GLGEN_STAT_EVBEN_MASK (0x1 << I40E_GLGEN_STAT_EVBEN_SHIFT) |
| #define I40E_GLGEN_STAT_HWRSVD1_SHIFT 6 |
| #define I40E_GLGEN_STAT_HWRSVD1_MASK (0x3 << I40E_GLGEN_STAT_HWRSVD1_SHIFT) |
| #define I40E_GLGEN_VFLRSTAT(_i) (0x00092600 + ((_i) * 4)) /* _i=0...3 */ |
| #define I40E_GLGEN_VFLRSTAT_MAX_INDEX 3 |
| #define I40E_GLGEN_VFLRSTAT_VFLRE_SHIFT 0 |
| #define I40E_GLGEN_VFLRSTAT_VFLRE_MASK (0xFFFFFFFF << I40E_GLGEN_VFLRSTAT_VFLRE_SHIFT) |
| #define I40E_GLVFGEN_TIMER 0x000881BC |
| #define I40E_GLVFGEN_TIMER_GTIME_SHIFT 0 |
| #define I40E_GLVFGEN_TIMER_GTIME_MASK (0xFFFFFFFF << I40E_GLVFGEN_TIMER_GTIME_SHIFT) |
| #define I40E_PFGEN_CTRL 0x00092400 |
| #define I40E_PFGEN_CTRL_PFSWR_SHIFT 0 |
| #define I40E_PFGEN_CTRL_PFSWR_MASK (0x1 << I40E_PFGEN_CTRL_PFSWR_SHIFT) |
| #define I40E_PFGEN_DRUN 0x00092500 |
| #define I40E_PFGEN_DRUN_DRVUNLD_SHIFT 0 |
| #define I40E_PFGEN_DRUN_DRVUNLD_MASK (0x1 << I40E_PFGEN_DRUN_DRVUNLD_SHIFT) |
| #define I40E_PFGEN_PORTNUM 0x001C0480 |
| #define I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT 0 |
| #define I40E_PFGEN_PORTNUM_PORT_NUM_MASK (0x3 << I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT) |
| #define I40E_PFGEN_STATE 0x00088000 |
| #define I40E_PFGEN_STATE_PFPEEN_SHIFT 0 |
| #define I40E_PFGEN_STATE_PFPEEN_MASK (0x1 << I40E_PFGEN_STATE_PFPEEN_SHIFT) |
| #define I40E_PFGEN_STATE_PFFCEN_SHIFT 1 |
| #define I40E_PFGEN_STATE_PFFCEN_MASK (0x1 << I40E_PFGEN_STATE_PFFCEN_SHIFT) |
| #define I40E_PFGEN_STATE_PFLINKEN_SHIFT 2 |
| #define I40E_PFGEN_STATE_PFLINKEN_MASK (0x1 << I40E_PFGEN_STATE_PFLINKEN_SHIFT) |
| #define I40E_PFGEN_STATE_PFSCEN_SHIFT 3 |
| #define I40E_PFGEN_STATE_PFSCEN_MASK (0x1 << I40E_PFGEN_STATE_PFSCEN_SHIFT) |
| #define I40E_PRTGEN_CNF 0x000B8120 |
| #define I40E_PRTGEN_CNF_PORT_DIS_SHIFT 0 |
| #define I40E_PRTGEN_CNF_PORT_DIS_MASK (0x1 << I40E_PRTGEN_CNF_PORT_DIS_SHIFT) |
| #define I40E_PRTGEN_CNF_ALLOW_PORT_DIS_SHIFT 1 |
| #define I40E_PRTGEN_CNF_ALLOW_PORT_DIS_MASK (0x1 << I40E_PRTGEN_CNF_ALLOW_PORT_DIS_SHIFT) |
| #define I40E_PRTGEN_CNF_EMP_PORT_DIS_SHIFT 2 |
| #define I40E_PRTGEN_CNF_EMP_PORT_DIS_MASK (0x1 << I40E_PRTGEN_CNF_EMP_PORT_DIS_SHIFT) |
| #define I40E_PRTGEN_CNF2 0x000B8160 |
| #define I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_SHIFT 0 |
| #define I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_MASK (0x1 << I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_SHIFT) |
| #define I40E_PRTGEN_STATUS 0x000B8100 |
| #define I40E_PRTGEN_STATUS_PORT_VALID_SHIFT 0 |
| #define I40E_PRTGEN_STATUS_PORT_VALID_MASK (0x1 << I40E_PRTGEN_STATUS_PORT_VALID_SHIFT) |
| #define I40E_PRTGEN_STATUS_PORT_ACTIVE_SHIFT 1 |
| #define I40E_PRTGEN_STATUS_PORT_ACTIVE_MASK (0x1 << I40E_PRTGEN_STATUS_PORT_ACTIVE_SHIFT) |
| #define I40E_VFGEN_RSTAT1(_VF) (0x00074400 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VFGEN_RSTAT1_MAX_INDEX 127 |
| #define I40E_VFGEN_RSTAT1_VFR_STATE_SHIFT 0 |
| #define I40E_VFGEN_RSTAT1_VFR_STATE_MASK (0x3 << I40E_VFGEN_RSTAT1_VFR_STATE_SHIFT) |
| #define I40E_VPGEN_VFRSTAT(_VF) (0x00091C00 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VPGEN_VFRSTAT_MAX_INDEX 127 |
| #define I40E_VPGEN_VFRSTAT_VFRD_SHIFT 0 |
| #define I40E_VPGEN_VFRSTAT_VFRD_MASK (0x1 << I40E_VPGEN_VFRSTAT_VFRD_SHIFT) |
| #define I40E_VPGEN_VFRTRIG(_VF) (0x00091800 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VPGEN_VFRTRIG_MAX_INDEX 127 |
| #define I40E_VPGEN_VFRTRIG_VFSWR_SHIFT 0 |
| #define I40E_VPGEN_VFRTRIG_VFSWR_MASK (0x1 << I40E_VPGEN_VFRTRIG_VFSWR_SHIFT) |
| #define I40E_VSIGEN_RSTAT(_VSI) (0x00090800 + ((_VSI) * 4)) /* _i=0...383 */ |
| #define I40E_VSIGEN_RSTAT_MAX_INDEX 383 |
| #define I40E_VSIGEN_RSTAT_VMRD_SHIFT 0 |
| #define I40E_VSIGEN_RSTAT_VMRD_MASK (0x1 << I40E_VSIGEN_RSTAT_VMRD_SHIFT) |
| #define I40E_VSIGEN_RTRIG(_VSI) (0x00090000 + ((_VSI) * 4)) /* _i=0...383 */ |
| #define I40E_VSIGEN_RTRIG_MAX_INDEX 383 |
| #define I40E_VSIGEN_RTRIG_VMSWR_SHIFT 0 |
| #define I40E_VSIGEN_RTRIG_VMSWR_MASK (0x1 << I40E_VSIGEN_RTRIG_VMSWR_SHIFT) |
| #define I40E_GLHMC_APBVTINUSEBASE(_i) (0x000C4a00 + ((_i) * 4)) |
| #define I40E_GLHMC_APBVTINUSEBASE_MAX_INDEX 15 |
| #define I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT 0 |
| #define I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_MASK (0xFFFFFF << I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT) |
| #define I40E_GLHMC_CEQPART(_i) (0x001312C0 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_CEQPART_MAX_INDEX 15 |
| #define I40E_GLHMC_CEQPART_PMCEQBASE_SHIFT 0 |
| #define I40E_GLHMC_CEQPART_PMCEQBASE_MASK (0xFF << I40E_GLHMC_CEQPART_PMCEQBASE_SHIFT) |
| #define I40E_GLHMC_CEQPART_PMCEQSIZE_SHIFT 16 |
| #define I40E_GLHMC_CEQPART_PMCEQSIZE_MASK (0x1FF << I40E_GLHMC_CEQPART_PMCEQSIZE_SHIFT) |
| #define I40E_GLHMC_DBCQPART(_i) (0x00131240 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_DBCQPART_MAX_INDEX 15 |
| #define I40E_GLHMC_DBCQPART_PMDBCQBASE_SHIFT 0 |
| #define I40E_GLHMC_DBCQPART_PMDBCQBASE_MASK (0x3FFF << I40E_GLHMC_DBCQPART_PMDBCQBASE_SHIFT) |
| #define I40E_GLHMC_DBCQPART_PMDBCQSIZE_SHIFT 16 |
| #define I40E_GLHMC_DBCQPART_PMDBCQSIZE_MASK (0x7FFF << I40E_GLHMC_DBCQPART_PMDBCQSIZE_SHIFT) |
| #define I40E_GLHMC_DBQPPART(_i) (0x00138D80 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_DBQPPART_MAX_INDEX 15 |
| #define I40E_GLHMC_DBQPPART_PMDBQPBASE_SHIFT 0 |
| #define I40E_GLHMC_DBQPPART_PMDBQPBASE_MASK (0x3FFF << I40E_GLHMC_DBQPPART_PMDBQPBASE_SHIFT) |
| #define I40E_GLHMC_DBQPPART_PMDBQPSIZE_SHIFT 16 |
| #define I40E_GLHMC_DBQPPART_PMDBQPSIZE_MASK (0x7FFF << I40E_GLHMC_DBQPPART_PMDBQPSIZE_SHIFT) |
| #define I40E_GLHMC_FCOEDDPBASE(_i) (0x000C6600 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_FCOEDDPBASE_MAX_INDEX 15 |
| #define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT 0 |
| #define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_MASK (0xFFFFFF << I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT) |
| #define I40E_GLHMC_FCOEDDPCNT(_i) (0x000C6700 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_FCOEDDPCNT_MAX_INDEX 15 |
| #define I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_SHIFT 0 |
| #define I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_MASK (0xFFFFF << I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_SHIFT) |
| #define I40E_GLHMC_FCOEDDPOBJSZ 0x000C2010 |
| #define I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_SHIFT 0 |
| #define I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_MASK (0xF << I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_SHIFT) |
| #define I40E_GLHMC_FCOEFBASE(_i) (0x000C6800 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_FCOEFBASE_MAX_INDEX 15 |
| #define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT 0 |
| #define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_MASK (0xFFFFFF << I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT) |
| #define I40E_GLHMC_FCOEFCNT(_i) (0x000C6900 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_FCOEFCNT_MAX_INDEX 15 |
| #define I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_SHIFT 0 |
| #define I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_MASK (0x7FFFFF << I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_SHIFT) |
| #define I40E_GLHMC_FCOEFMAX 0x000C20D0 |
| #define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT 0 |
| #define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK (0xFFFF << I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT) |
| #define I40E_GLHMC_FCOEFOBJSZ 0x000C2018 |
| #define I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_SHIFT 0 |
| #define I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_MASK (0xF << I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_SHIFT) |
| #define I40E_GLHMC_FCOEMAX 0x000C2014 |
| #define I40E_GLHMC_FCOEMAX_PMFCOEMAX_SHIFT 0 |
| #define I40E_GLHMC_FCOEMAX_PMFCOEMAX_MASK (0x1FFF << I40E_GLHMC_FCOEMAX_PMFCOEMAX_SHIFT) |
| #define I40E_GLHMC_FSIAVBASE(_i) (0x000C5600 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_FSIAVBASE_MAX_INDEX 15 |
| #define I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_SHIFT 0 |
| #define I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_MASK (0xFFFFFF << I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_SHIFT) |
| #define I40E_GLHMC_FSIAVCNT(_i) (0x000C5700 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_FSIAVCNT_MAX_INDEX 15 |
| #define I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_SHIFT 0 |
| #define I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_MASK (0x1FFFFFFF << I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_SHIFT) |
| #define I40E_GLHMC_FSIAVCNT_RSVD_SHIFT 29 |
| #define I40E_GLHMC_FSIAVCNT_RSVD_MASK (0x7 << I40E_GLHMC_FSIAVCNT_RSVD_SHIFT) |
| #define I40E_GLHMC_FSIAVMAX 0x000C2068 |
| #define I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_SHIFT 0 |
| #define I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_MASK (0x1FFFF << I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_SHIFT) |
| #define I40E_GLHMC_FSIAVOBJSZ 0x000C2064 |
| #define I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_SHIFT 0 |
| #define I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_MASK (0xF << I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_SHIFT) |
| #define I40E_GLHMC_FSIMCBASE(_i) (0x000C6000 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_FSIMCBASE_MAX_INDEX 15 |
| #define I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_SHIFT 0 |
| #define I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_MASK (0xFFFFFF << I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_SHIFT) |
| #define I40E_GLHMC_FSIMCCNT(_i) (0x000C6100 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_FSIMCCNT_MAX_INDEX 15 |
| #define I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_SHIFT 0 |
| #define I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_MASK (0x1FFFFFFF << I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_SHIFT) |
| #define I40E_GLHMC_FSIMCMAX 0x000C2060 |
| #define I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_SHIFT 0 |
| #define I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_MASK (0x3FFF << I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_SHIFT) |
| #define I40E_GLHMC_FSIMCOBJSZ 0x000C205c |
| #define I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_SHIFT 0 |
| #define I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_MASK (0xF << I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_SHIFT) |
| #define I40E_GLHMC_LANQMAX 0x000C2008 |
| #define I40E_GLHMC_LANQMAX_PMLANQMAX_SHIFT 0 |
| #define I40E_GLHMC_LANQMAX_PMLANQMAX_MASK (0x7FF << I40E_GLHMC_LANQMAX_PMLANQMAX_SHIFT) |
| #define I40E_GLHMC_LANRXBASE(_i) (0x000C6400 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_LANRXBASE_MAX_INDEX 15 |
| #define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT 0 |
| #define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_MASK (0xFFFFFF << I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT) |
| #define I40E_GLHMC_LANRXCNT(_i) (0x000C6500 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_LANRXCNT_MAX_INDEX 15 |
| #define I40E_GLHMC_LANRXCNT_FPMLANRXCNT_SHIFT 0 |
| #define I40E_GLHMC_LANRXCNT_FPMLANRXCNT_MASK (0x7FF << I40E_GLHMC_LANRXCNT_FPMLANRXCNT_SHIFT) |
| #define I40E_GLHMC_LANRXOBJSZ 0x000C200c |
| #define I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_SHIFT 0 |
| #define I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_MASK (0xF << I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_SHIFT) |
| #define I40E_GLHMC_LANTXBASE(_i) (0x000C6200 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_LANTXBASE_MAX_INDEX 15 |
| #define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT 0 |
| #define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_MASK (0xFFFFFF << I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT) |
| #define I40E_GLHMC_LANTXBASE_RSVD_SHIFT 24 |
| #define I40E_GLHMC_LANTXBASE_RSVD_MASK (0xFF << I40E_GLHMC_LANTXBASE_RSVD_SHIFT) |
| #define I40E_GLHMC_LANTXCNT(_i) (0x000C6300 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_LANTXCNT_MAX_INDEX 15 |
| #define I40E_GLHMC_LANTXCNT_FPMLANTXCNT_SHIFT 0 |
| #define I40E_GLHMC_LANTXCNT_FPMLANTXCNT_MASK (0x7FF << I40E_GLHMC_LANTXCNT_FPMLANTXCNT_SHIFT) |
| #define I40E_GLHMC_LANTXOBJSZ 0x000C2004 |
| #define I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_SHIFT 0 |
| #define I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_MASK (0xF << I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_SHIFT) |
| #define I40E_GLHMC_PEARPBASE(_i) (0x000C4800 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_PEARPBASE_MAX_INDEX 15 |
| #define I40E_GLHMC_PEARPBASE_FPMPEARPBASE_SHIFT 0 |
| #define I40E_GLHMC_PEARPBASE_FPMPEARPBASE_MASK (0xFFFFFF << I40E_GLHMC_PEARPBASE_FPMPEARPBASE_SHIFT) |
| #define I40E_GLHMC_PEARPCNT(_i) (0x000C4900 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_PEARPCNT_MAX_INDEX 15 |
| #define I40E_GLHMC_PEARPCNT_FPMPEARPCNT_SHIFT 0 |
| #define I40E_GLHMC_PEARPCNT_FPMPEARPCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEARPCNT_FPMPEARPCNT_SHIFT) |
| #define I40E_GLHMC_PEARPMAX 0x000C2038 |
| #define I40E_GLHMC_PEARPMAX_PMPEARPMAX_SHIFT 0 |
| #define I40E_GLHMC_PEARPMAX_PMPEARPMAX_MASK (0x1FFFF << I40E_GLHMC_PEARPMAX_PMPEARPMAX_SHIFT) |
| #define I40E_GLHMC_PEARPOBJSZ 0x000C2034 |
| #define I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_SHIFT 0 |
| #define I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_MASK (0x7 << I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_SHIFT) |
| #define I40E_GLHMC_PECQBASE(_i) (0x000C4200 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_PECQBASE_MAX_INDEX 15 |
| #define I40E_GLHMC_PECQBASE_FPMPECQBASE_SHIFT 0 |
| #define I40E_GLHMC_PECQBASE_FPMPECQBASE_MASK (0xFFFFFF << I40E_GLHMC_PECQBASE_FPMPECQBASE_SHIFT) |
| #define I40E_GLHMC_PECQCNT(_i) (0x000C4300 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_PECQCNT_MAX_INDEX 15 |
| #define I40E_GLHMC_PECQCNT_FPMPECQCNT_SHIFT 0 |
| #define I40E_GLHMC_PECQCNT_FPMPECQCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PECQCNT_FPMPECQCNT_SHIFT) |
| #define I40E_GLHMC_PECQOBJSZ 0x000C2020 |
| #define I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_SHIFT 0 |
| #define I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_MASK (0xF << I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_SHIFT) |
| #define I40E_GLHMC_PEHTCNT(_i) (0x000C4700 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_PEHTCNT_MAX_INDEX 15 |
| #define I40E_GLHMC_PEHTCNT_FPMPEHTCNT_SHIFT 0 |
| #define I40E_GLHMC_PEHTCNT_FPMPEHTCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEHTCNT_FPMPEHTCNT_SHIFT) |
| #define I40E_GLHMC_PEHTEBASE(_i) (0x000C4600 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_PEHTEBASE_MAX_INDEX 15 |
| #define I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_SHIFT 0 |
| #define I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_MASK (0xFFFFFF << I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_SHIFT) |
| #define I40E_GLHMC_PEHTEOBJSZ 0x000C202c |
| #define I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_SHIFT 0 |
| #define I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_MASK (0xF << I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_SHIFT) |
| #define I40E_GLHMC_PEHTMAX 0x000C2030 |
| #define I40E_GLHMC_PEHTMAX_PMPEHTMAX_SHIFT 0 |
| #define I40E_GLHMC_PEHTMAX_PMPEHTMAX_MASK (0x1FFFFF << I40E_GLHMC_PEHTMAX_PMPEHTMAX_SHIFT) |
| #define I40E_GLHMC_PEMRBASE(_i) (0x000C4c00 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_PEMRBASE_MAX_INDEX 15 |
| #define I40E_GLHMC_PEMRBASE_FPMPEMRBASE_SHIFT 0 |
| #define I40E_GLHMC_PEMRBASE_FPMPEMRBASE_MASK (0xFFFFFF << I40E_GLHMC_PEMRBASE_FPMPEMRBASE_SHIFT) |
| #define I40E_GLHMC_PEMRCNT(_i) (0x000C4d00 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_PEMRCNT_MAX_INDEX 15 |
| #define I40E_GLHMC_PEMRCNT_FPMPEMRSZ_SHIFT 0 |
| #define I40E_GLHMC_PEMRCNT_FPMPEMRSZ_MASK (0x1FFFFFFF << I40E_GLHMC_PEMRCNT_FPMPEMRSZ_SHIFT) |
| #define I40E_GLHMC_PEMRMAX 0x000C2040 |
| #define I40E_GLHMC_PEMRMAX_PMPEMRMAX_SHIFT 0 |
| #define I40E_GLHMC_PEMRMAX_PMPEMRMAX_MASK (0x7FFFFF << I40E_GLHMC_PEMRMAX_PMPEMRMAX_SHIFT) |
| #define I40E_GLHMC_PEMROBJSZ 0x000C203c |
| #define I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_SHIFT 0 |
| #define I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_MASK (0xF << I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_SHIFT) |
| #define I40E_GLHMC_PEPBLBASE(_i) (0x000C5800 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_PEPBLBASE_MAX_INDEX 15 |
| #define I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_SHIFT 0 |
| #define I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_MASK (0xFFFFFF << I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_SHIFT) |
| #define I40E_GLHMC_PEPBLCNT(_i) (0x000C5900 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_PEPBLCNT_MAX_INDEX 15 |
| #define I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_SHIFT 0 |
| #define I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_SHIFT) |
| #define I40E_GLHMC_PEPBLMAX 0x000C206c |
| #define I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_SHIFT 0 |
| #define I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_MASK (0x1FFFFFFF << I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_SHIFT) |
| #define I40E_GLHMC_PEQ1BASE(_i) (0x000C5200 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_PEQ1BASE_MAX_INDEX 15 |
| #define I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_SHIFT 0 |
| #define I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_MASK (0xFFFFFF << I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_SHIFT) |
| #define I40E_GLHMC_PEQ1CNT(_i) (0x000C5300 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_PEQ1CNT_MAX_INDEX 15 |
| #define I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_SHIFT 0 |
| #define I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_SHIFT) |
| #define I40E_GLHMC_PEQ1FLBASE(_i) (0x000C5400 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_PEQ1FLBASE_MAX_INDEX 15 |
| #define I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_SHIFT 0 |
| #define I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_MASK (0xFFFFFF << I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_SHIFT) |
| #define I40E_GLHMC_PEQ1FLCNT(_i) (0x000C5500 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_PEQ1FLCNT_MAX_INDEX 15 |
| #define I40E_GLHMC_PEQ1FLCNT_FPMPEQ1FLCNT_SHIFT 0 |
| #define I40E_GLHMC_PEQ1FLCNT_FPMPEQ1FLCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEQ1FLCNT_FPMPEQ1FLCNT_SHIFT) |
| #define I40E_GLHMC_PEQ1FLMAX 0x000C2058 |
| #define I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_SHIFT 0 |
| #define I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_MASK (0x3FFFFFF << I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_SHIFT) |
| #define I40E_GLHMC_PEQ1MAX 0x000C2054 |
| #define I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_SHIFT 0 |
| #define I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_MASK (0x3FFFFFF << I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_SHIFT) |
| #define I40E_GLHMC_PEQ1OBJSZ 0x000C2050 |
| #define I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_SHIFT 0 |
| #define I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_MASK (0xF << I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_SHIFT) |
| #define I40E_GLHMC_PEQPBASE(_i) (0x000C4000 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_PEQPBASE_MAX_INDEX 15 |
| #define I40E_GLHMC_PEQPBASE_FPMPEQPBASE_SHIFT 0 |
| #define I40E_GLHMC_PEQPBASE_FPMPEQPBASE_MASK (0xFFFFFF << I40E_GLHMC_PEQPBASE_FPMPEQPBASE_SHIFT) |
| #define I40E_GLHMC_PEQPCNT(_i) (0x000C4100 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_PEQPCNT_MAX_INDEX 15 |
| #define I40E_GLHMC_PEQPCNT_FPMPEQPCNT_SHIFT 0 |
| #define I40E_GLHMC_PEQPCNT_FPMPEQPCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEQPCNT_FPMPEQPCNT_SHIFT) |
| #define I40E_GLHMC_PEQPOBJSZ 0x000C201c |
| #define I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_SHIFT 0 |
| #define I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_MASK (0xF << I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_SHIFT) |
| #define I40E_GLHMC_PESRQBASE(_i) (0x000C4400 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_PESRQBASE_MAX_INDEX 15 |
| #define I40E_GLHMC_PESRQBASE_FPMPESRQBASE_SHIFT 0 |
| #define I40E_GLHMC_PESRQBASE_FPMPESRQBASE_MASK (0xFFFFFF << I40E_GLHMC_PESRQBASE_FPMPESRQBASE_SHIFT) |
| #define I40E_GLHMC_PESRQCNT(_i) (0x000C4500 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_PESRQCNT_MAX_INDEX 15 |
| #define I40E_GLHMC_PESRQCNT_FPMPESRQCNT_SHIFT 0 |
| #define I40E_GLHMC_PESRQCNT_FPMPESRQCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PESRQCNT_FPMPESRQCNT_SHIFT) |
| #define I40E_GLHMC_PESRQMAX 0x000C2028 |
| #define I40E_GLHMC_PESRQMAX_PMPESRQMAX_SHIFT 0 |
| #define I40E_GLHMC_PESRQMAX_PMPESRQMAX_MASK (0xFFFF << I40E_GLHMC_PESRQMAX_PMPESRQMAX_SHIFT) |
| #define I40E_GLHMC_PESRQOBJSZ 0x000C2024 |
| #define I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_SHIFT 0 |
| #define I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_MASK (0xF << I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_SHIFT) |
| #define I40E_GLHMC_PESRQOBJSZ_RSVD_SHIFT 4 |
| #define I40E_GLHMC_PESRQOBJSZ_RSVD_MASK (0xFFFFFFF << I40E_GLHMC_PESRQOBJSZ_RSVD_SHIFT) |
| #define I40E_GLHMC_PETIMERBASE(_i) (0x000C5A00 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_PETIMERBASE_MAX_INDEX 15 |
| #define I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_SHIFT 0 |
| #define I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_MASK (0xFFFFFF << I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_SHIFT) |
| #define I40E_GLHMC_PETIMERCNT(_i) (0x000C5B00 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_PETIMERCNT_MAX_INDEX 15 |
| #define I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_SHIFT 0 |
| #define I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_SHIFT) |
| #define I40E_GLHMC_PETIMERMAX 0x000C2084 |
| #define I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_SHIFT 0 |
| #define I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_MASK (0x1FFFFFFF << I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_SHIFT) |
| #define I40E_GLHMC_PETIMEROBJSZ 0x000C2080 |
| #define I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_SHIFT 0 |
| #define I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_MASK (0xF << I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_SHIFT) |
| #define I40E_GLHMC_PEXFBASE(_i) (0x000C4e00 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_PEXFBASE_MAX_INDEX 15 |
| #define I40E_GLHMC_PEXFBASE_FPMPEXFBASE_SHIFT 0 |
| #define I40E_GLHMC_PEXFBASE_FPMPEXFBASE_MASK (0xFFFFFF << I40E_GLHMC_PEXFBASE_FPMPEXFBASE_SHIFT) |
| #define I40E_GLHMC_PEXFCNT(_i) (0x000C4f00 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_PEXFCNT_MAX_INDEX 15 |
| #define I40E_GLHMC_PEXFCNT_FPMPEXFCNT_SHIFT 0 |
| #define I40E_GLHMC_PEXFCNT_FPMPEXFCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEXFCNT_FPMPEXFCNT_SHIFT) |
| #define I40E_GLHMC_PEXFFLBASE(_i) (0x000C5000 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_PEXFFLBASE_MAX_INDEX 15 |
| #define I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_SHIFT 0 |
| #define I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_MASK (0xFFFFFF << I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_SHIFT) |
| #define I40E_GLHMC_PEXFFLCNT(_i) (0x000C5100 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_PEXFFLCNT_MAX_INDEX 15 |
| #define I40E_GLHMC_PEXFFLCNT_FPMPEXFFLCNT_SHIFT 0 |
| #define I40E_GLHMC_PEXFFLCNT_FPMPEXFFLCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEXFFLCNT_FPMPEXFFLCNT_SHIFT) |
| #define I40E_GLHMC_PEXFFLMAX 0x000C204c |
| #define I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_SHIFT 0 |
| #define I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_MASK (0x1FFFFFF << I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_SHIFT) |
| #define I40E_GLHMC_PEXFMAX 0x000C2048 |
| #define I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT 0 |
| #define I40E_GLHMC_PEXFMAX_PMPEXFMAX_MASK (0x3FFFFFF << I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT) |
| #define I40E_GLHMC_PEXFOBJSZ 0x000C2044 |
| #define I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_SHIFT 0 |
| #define I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_MASK (0xF << I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_SHIFT) |
| #define I40E_GLHMC_PEXFOBJSZ_RSVD_SHIFT 4 |
| #define I40E_GLHMC_PEXFOBJSZ_RSVD_MASK (0xFFFFFFF << I40E_GLHMC_PEXFOBJSZ_RSVD_SHIFT) |
| #define I40E_GLHMC_PFASSIGN(_i) (0x000C0c00 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_PFASSIGN_MAX_INDEX 15 |
| #define I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_SHIFT 0 |
| #define I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_MASK (0xF << I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_SHIFT) |
| #define I40E_GLHMC_SDPART(_i) (0x000C0800 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLHMC_SDPART_MAX_INDEX 15 |
| #define I40E_GLHMC_SDPART_PMSDBASE_SHIFT 0 |
| #define I40E_GLHMC_SDPART_PMSDBASE_MASK (0xFFF << I40E_GLHMC_SDPART_PMSDBASE_SHIFT) |
| #define I40E_GLHMC_SDPART_PMSDSIZE_SHIFT 16 |
| #define I40E_GLHMC_SDPART_PMSDSIZE_MASK (0x1FFF << I40E_GLHMC_SDPART_PMSDSIZE_SHIFT) |
| #define I40E_GLHMC_VFAPBVTINUSEBASE(_i) (0x000Cca00 + ((_i) * 4)) |
| #define I40E_GLHMC_VFAPBVTINUSEBASE_MAX_INDEX 31 |
| #define I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT 0 |
| #define I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_MASK (0xFFFFFF << I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT) |
| #define I40E_GLHMC_VFCEQPART(_i) (0x00132240 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFCEQPART_MAX_INDEX 31 |
| #define I40E_GLHMC_VFCEQPART_PMCEQBASE_SHIFT 0 |
| #define I40E_GLHMC_VFCEQPART_PMCEQBASE_MASK (0xFF << I40E_GLHMC_VFCEQPART_PMCEQBASE_SHIFT) |
| #define I40E_GLHMC_VFCEQPART_PMCEQSIZE_SHIFT 16 |
| #define I40E_GLHMC_VFCEQPART_PMCEQSIZE_MASK (0x1FF << I40E_GLHMC_VFCEQPART_PMCEQSIZE_SHIFT) |
| #define I40E_GLHMC_VFDBCQPART(_i) (0x00132140 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFDBCQPART_MAX_INDEX 31 |
| #define I40E_GLHMC_VFDBCQPART_PMDBCQBASE_SHIFT 0 |
| #define I40E_GLHMC_VFDBCQPART_PMDBCQBASE_MASK (0x3FFF << I40E_GLHMC_VFDBCQPART_PMDBCQBASE_SHIFT) |
| #define I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_SHIFT 16 |
| #define I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_MASK (0x7FFF << I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_SHIFT) |
| #define I40E_GLHMC_VFDBQPPART(_i) (0x00138E00 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFDBQPPART_MAX_INDEX 31 |
| #define I40E_GLHMC_VFDBQPPART_PMDBQPBASE_SHIFT 0 |
| #define I40E_GLHMC_VFDBQPPART_PMDBQPBASE_MASK (0x3FFF << I40E_GLHMC_VFDBQPPART_PMDBQPBASE_SHIFT) |
| #define I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_SHIFT 16 |
| #define I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_MASK (0x7FFF << I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_SHIFT) |
| #define I40E_GLHMC_VFFSIAVBASE(_i) (0x000Cd600 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFFSIAVBASE_MAX_INDEX 31 |
| #define I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_SHIFT 0 |
| #define I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_MASK (0xFFFFFF << I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_SHIFT) |
| #define I40E_GLHMC_VFFSIAVCNT(_i) (0x000Cd700 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFFSIAVCNT_MAX_INDEX 31 |
| #define I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_SHIFT 0 |
| #define I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_SHIFT) |
| #define I40E_GLHMC_VFFSIAVCNT_RSVD_SHIFT 29 |
| #define I40E_GLHMC_VFFSIAVCNT_RSVD_MASK (0x7 << I40E_GLHMC_VFFSIAVCNT_RSVD_SHIFT) |
| #define I40E_GLHMC_VFPDINV(_i) (0x000C8300 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFPDINV_MAX_INDEX 31 |
| #define I40E_GLHMC_VFPDINV_PMSDIDX_SHIFT 0 |
| #define I40E_GLHMC_VFPDINV_PMSDIDX_MASK (0xFFF << I40E_GLHMC_VFPDINV_PMSDIDX_SHIFT) |
| #define I40E_GLHMC_VFPDINV_PMPDIDX_SHIFT 16 |
| #define I40E_GLHMC_VFPDINV_PMPDIDX_MASK (0x1FF << I40E_GLHMC_VFPDINV_PMPDIDX_SHIFT) |
| #define I40E_GLHMC_VFPEARPBASE(_i) (0x000Cc800 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFPEARPBASE_MAX_INDEX 31 |
| #define I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_SHIFT 0 |
| #define I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_SHIFT) |
| #define I40E_GLHMC_VFPEARPCNT(_i) (0x000Cc900 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFPEARPCNT_MAX_INDEX 31 |
| #define I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_SHIFT 0 |
| #define I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_SHIFT) |
| #define I40E_GLHMC_VFPECQBASE(_i) (0x000Cc200 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFPECQBASE_MAX_INDEX 31 |
| #define I40E_GLHMC_VFPECQBASE_FPMPECQBASE_SHIFT 0 |
| #define I40E_GLHMC_VFPECQBASE_FPMPECQBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPECQBASE_FPMPECQBASE_SHIFT) |
| #define I40E_GLHMC_VFPECQCNT(_i) (0x000Cc300 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFPECQCNT_MAX_INDEX 31 |
| #define I40E_GLHMC_VFPECQCNT_FPMPECQCNT_SHIFT 0 |
| #define I40E_GLHMC_VFPECQCNT_FPMPECQCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPECQCNT_FPMPECQCNT_SHIFT) |
| #define I40E_GLHMC_VFPEHTCNT(_i) (0x000Cc700 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFPEHTCNT_MAX_INDEX 31 |
| #define I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_SHIFT 0 |
| #define I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_SHIFT) |
| #define I40E_GLHMC_VFPEHTEBASE(_i) (0x000Cc600 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFPEHTEBASE_MAX_INDEX 31 |
| #define I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_SHIFT 0 |
| #define I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_SHIFT) |
| #define I40E_GLHMC_VFPEMRBASE(_i) (0x000Ccc00 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFPEMRBASE_MAX_INDEX 31 |
| #define I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_SHIFT 0 |
| #define I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_SHIFT) |
| #define I40E_GLHMC_VFPEMRCNT(_i) (0x000Ccd00 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFPEMRCNT_MAX_INDEX 31 |
| #define I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_SHIFT 0 |
| #define I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_SHIFT) |
| #define I40E_GLHMC_VFPEPBLBASE(_i) (0x000Cd800 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFPEPBLBASE_MAX_INDEX 31 |
| #define I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_SHIFT 0 |
| #define I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_SHIFT) |
| #define I40E_GLHMC_VFPEPBLCNT(_i) (0x000Cd900 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFPEPBLCNT_MAX_INDEX 31 |
| #define I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_SHIFT 0 |
| #define I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_SHIFT) |
| #define I40E_GLHMC_VFPEQ1BASE(_i) (0x000Cd200 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFPEQ1BASE_MAX_INDEX 31 |
| #define I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_SHIFT 0 |
| #define I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_SHIFT) |
| #define I40E_GLHMC_VFPEQ1CNT(_i) (0x000Cd300 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFPEQ1CNT_MAX_INDEX 31 |
| #define I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_SHIFT 0 |
| #define I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_SHIFT) |
| #define I40E_GLHMC_VFPEQ1FLBASE(_i) (0x000Cd400 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFPEQ1FLBASE_MAX_INDEX 31 |
| #define I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_SHIFT 0 |
| #define I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_SHIFT) |
| #define I40E_GLHMC_VFPEQ1FLCNT(_i) (0x000Cd500 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFPEQ1FLCNT_MAX_INDEX 31 |
| #define I40E_GLHMC_VFPEQ1FLCNT_FPMPEQ1FLCNT_SHIFT 0 |
| #define I40E_GLHMC_VFPEQ1FLCNT_FPMPEQ1FLCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEQ1FLCNT_FPMPEQ1FLCNT_SHIFT) |
| #define I40E_GLHMC_VFPEQPBASE(_i) (0x000Cc000 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFPEQPBASE_MAX_INDEX 31 |
| #define I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_SHIFT 0 |
| #define I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_SHIFT) |
| #define I40E_GLHMC_VFPEQPCNT(_i) (0x000Cc100 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFPEQPCNT_MAX_INDEX 31 |
| #define I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_SHIFT 0 |
| #define I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_SHIFT) |
| #define I40E_GLHMC_VFPESRQBASE(_i) (0x000Cc400 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFPESRQBASE_MAX_INDEX 31 |
| #define I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_SHIFT 0 |
| #define I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_SHIFT) |
| #define I40E_GLHMC_VFPESRQCNT(_i) (0x000Cc500 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFPESRQCNT_MAX_INDEX 31 |
| #define I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_SHIFT 0 |
| #define I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_SHIFT) |
| #define I40E_GLHMC_VFPETIMERBASE(_i) (0x000CDA00 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFPETIMERBASE_MAX_INDEX 31 |
| #define I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_SHIFT 0 |
| #define I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_SHIFT) |
| #define I40E_GLHMC_VFPETIMERCNT(_i) (0x000CDB00 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFPETIMERCNT_MAX_INDEX 31 |
| #define I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_SHIFT 0 |
| #define I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_SHIFT) |
| #define I40E_GLHMC_VFPEXFBASE(_i) (0x000Cce00 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFPEXFBASE_MAX_INDEX 31 |
| #define I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_SHIFT 0 |
| #define I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_SHIFT) |
| #define I40E_GLHMC_VFPEXFCNT(_i) (0x000Ccf00 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFPEXFCNT_MAX_INDEX 31 |
| #define I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_SHIFT 0 |
| #define I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_SHIFT) |
| #define I40E_GLHMC_VFPEXFFLBASE(_i) (0x000Cd000 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFPEXFFLBASE_MAX_INDEX 31 |
| #define I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_SHIFT 0 |
| #define I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_SHIFT) |
| #define I40E_GLHMC_VFPEXFFLCNT(_i) (0x000Cd100 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFPEXFFLCNT_MAX_INDEX 31 |
| #define I40E_GLHMC_VFPEXFFLCNT_FPMPEXFFLCNT_SHIFT 0 |
| #define I40E_GLHMC_VFPEXFFLCNT_FPMPEXFFLCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEXFFLCNT_FPMPEXFFLCNT_SHIFT) |
| #define I40E_GLHMC_VFSDPART(_i) (0x000C8800 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLHMC_VFSDPART_MAX_INDEX 31 |
| #define I40E_GLHMC_VFSDPART_PMSDBASE_SHIFT 0 |
| #define I40E_GLHMC_VFSDPART_PMSDBASE_MASK (0xFFF << I40E_GLHMC_VFSDPART_PMSDBASE_SHIFT) |
| #define I40E_GLHMC_VFSDPART_PMSDSIZE_SHIFT 16 |
| #define I40E_GLHMC_VFSDPART_PMSDSIZE_MASK (0x1FFF << I40E_GLHMC_VFSDPART_PMSDSIZE_SHIFT) |
| #define I40E_PFHMC_ERRORDATA 0x000C0500 |
| #define I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_SHIFT 0 |
| #define I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_MASK (0x3FFFFFFF << I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_SHIFT) |
| #define I40E_PFHMC_ERRORINFO 0x000C0400 |
| #define I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT 0 |
| #define I40E_PFHMC_ERRORINFO_PMF_INDEX_MASK (0x1F << I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT) |
| #define I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT 7 |
| #define I40E_PFHMC_ERRORINFO_PMF_ISVF_MASK (0x1 << I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT) |
| #define I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_SHIFT 8 |
| #define I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_MASK (0xF << I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_SHIFT) |
| #define I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT 16 |
| #define I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_MASK (0x1F << I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT) |
| #define I40E_PFHMC_ERRORINFO_ERROR_DETECTED_SHIFT 31 |
| #define I40E_PFHMC_ERRORINFO_ERROR_DETECTED_MASK (0x1 << I40E_PFHMC_ERRORINFO_ERROR_DETECTED_SHIFT) |
| #define I40E_PFHMC_PDINV 0x000C0300 |
| #define I40E_PFHMC_PDINV_PMSDIDX_SHIFT 0 |
| #define I40E_PFHMC_PDINV_PMSDIDX_MASK (0xFFF << I40E_PFHMC_PDINV_PMSDIDX_SHIFT) |
| #define I40E_PFHMC_PDINV_PMPDIDX_SHIFT 16 |
| #define I40E_PFHMC_PDINV_PMPDIDX_MASK (0x1FF << I40E_PFHMC_PDINV_PMPDIDX_SHIFT) |
| #define I40E_PFHMC_SDCMD 0x000C0000 |
| #define I40E_PFHMC_SDCMD_PMSDIDX_SHIFT 0 |
| #define I40E_PFHMC_SDCMD_PMSDIDX_MASK (0xFFF << I40E_PFHMC_SDCMD_PMSDIDX_SHIFT) |
| #define I40E_PFHMC_SDCMD_PMSDWR_SHIFT 31 |
| #define I40E_PFHMC_SDCMD_PMSDWR_MASK (0x1 << I40E_PFHMC_SDCMD_PMSDWR_SHIFT) |
| #define I40E_PFHMC_SDDATAHIGH 0x000C0200 |
| #define I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_SHIFT 0 |
| #define I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_MASK (0xFFFFFFFF << I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_SHIFT) |
| #define I40E_PFHMC_SDDATALOW 0x000C0100 |
| #define I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT 0 |
| #define I40E_PFHMC_SDDATALOW_PMSDVALID_MASK (0x1 << I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT) |
| #define I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT 1 |
| #define I40E_PFHMC_SDDATALOW_PMSDTYPE_MASK (0x1 << I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT) |
| #define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT 2 |
| #define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_MASK (0x3FF << I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) |
| #define I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT 12 |
| #define I40E_PFHMC_SDDATALOW_PMSDDATALOW_MASK (0xFFFFF << I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT) |
| #define I40E_GL_UFUSE 0x00094008 |
| #define I40E_GL_UFUSE_FOUR_PORT_ENABLE_SHIFT 1 |
| #define I40E_GL_UFUSE_FOUR_PORT_ENABLE_MASK (0x1 << I40E_GL_UFUSE_FOUR_PORT_ENABLE_SHIFT) |
| #define I40E_GL_UFUSE_NIC_ID_SHIFT 2 |
| #define I40E_GL_UFUSE_NIC_ID_MASK (0x1 << I40E_GL_UFUSE_NIC_ID_SHIFT) |
| #define I40E_GL_UFUSE_ULT_LOCKOUT_SHIFT 10 |
| #define I40E_GL_UFUSE_ULT_LOCKOUT_MASK (0x1 << I40E_GL_UFUSE_ULT_LOCKOUT_SHIFT) |
| #define I40E_GL_UFUSE_CLS_LOCKOUT_SHIFT 11 |
| #define I40E_GL_UFUSE_CLS_LOCKOUT_MASK (0x1 << I40E_GL_UFUSE_CLS_LOCKOUT_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA 0x00088188 |
| #define I40E_EMPINT_GPIO_ENA_GPIO0_ENA_SHIFT 0 |
| #define I40E_EMPINT_GPIO_ENA_GPIO0_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO0_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO1_ENA_SHIFT 1 |
| #define I40E_EMPINT_GPIO_ENA_GPIO1_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO1_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO2_ENA_SHIFT 2 |
| #define I40E_EMPINT_GPIO_ENA_GPIO2_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO2_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO3_ENA_SHIFT 3 |
| #define I40E_EMPINT_GPIO_ENA_GPIO3_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO3_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO4_ENA_SHIFT 4 |
| #define I40E_EMPINT_GPIO_ENA_GPIO4_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO4_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO5_ENA_SHIFT 5 |
| #define I40E_EMPINT_GPIO_ENA_GPIO5_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO5_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO6_ENA_SHIFT 6 |
| #define I40E_EMPINT_GPIO_ENA_GPIO6_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO6_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO7_ENA_SHIFT 7 |
| #define I40E_EMPINT_GPIO_ENA_GPIO7_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO7_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO8_ENA_SHIFT 8 |
| #define I40E_EMPINT_GPIO_ENA_GPIO8_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO8_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO9_ENA_SHIFT 9 |
| #define I40E_EMPINT_GPIO_ENA_GPIO9_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO9_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO10_ENA_SHIFT 10 |
| #define I40E_EMPINT_GPIO_ENA_GPIO10_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO10_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO11_ENA_SHIFT 11 |
| #define I40E_EMPINT_GPIO_ENA_GPIO11_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO11_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO12_ENA_SHIFT 12 |
| #define I40E_EMPINT_GPIO_ENA_GPIO12_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO12_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO13_ENA_SHIFT 13 |
| #define I40E_EMPINT_GPIO_ENA_GPIO13_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO13_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO14_ENA_SHIFT 14 |
| #define I40E_EMPINT_GPIO_ENA_GPIO14_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO14_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO15_ENA_SHIFT 15 |
| #define I40E_EMPINT_GPIO_ENA_GPIO15_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO15_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO16_ENA_SHIFT 16 |
| #define I40E_EMPINT_GPIO_ENA_GPIO16_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO16_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO17_ENA_SHIFT 17 |
| #define I40E_EMPINT_GPIO_ENA_GPIO17_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO17_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO18_ENA_SHIFT 18 |
| #define I40E_EMPINT_GPIO_ENA_GPIO18_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO18_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO19_ENA_SHIFT 19 |
| #define I40E_EMPINT_GPIO_ENA_GPIO19_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO19_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO20_ENA_SHIFT 20 |
| #define I40E_EMPINT_GPIO_ENA_GPIO20_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO20_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO21_ENA_SHIFT 21 |
| #define I40E_EMPINT_GPIO_ENA_GPIO21_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO21_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO22_ENA_SHIFT 22 |
| #define I40E_EMPINT_GPIO_ENA_GPIO22_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO22_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO23_ENA_SHIFT 23 |
| #define I40E_EMPINT_GPIO_ENA_GPIO23_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO23_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO24_ENA_SHIFT 24 |
| #define I40E_EMPINT_GPIO_ENA_GPIO24_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO24_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO25_ENA_SHIFT 25 |
| #define I40E_EMPINT_GPIO_ENA_GPIO25_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO25_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO26_ENA_SHIFT 26 |
| #define I40E_EMPINT_GPIO_ENA_GPIO26_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO26_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO27_ENA_SHIFT 27 |
| #define I40E_EMPINT_GPIO_ENA_GPIO27_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO27_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO28_ENA_SHIFT 28 |
| #define I40E_EMPINT_GPIO_ENA_GPIO28_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO28_ENA_SHIFT) |
| #define I40E_EMPINT_GPIO_ENA_GPIO29_ENA_SHIFT 29 |
| #define I40E_EMPINT_GPIO_ENA_GPIO29_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO29_ENA_SHIFT) |
| #define I40E_PFGEN_PORTMDIO_NUM 0x0003F100 |
| #define I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_SHIFT 0 |
| #define I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_MASK (0x3 << I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_SHIFT) |
| #define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT 4 |
| #define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK (0x1 << I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT) |
| #define I40E_PFINT_AEQCTL 0x00038700 |
| #define I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT 0 |
| #define I40E_PFINT_AEQCTL_MSIX_INDX_MASK (0xFF << I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT) |
| #define I40E_PFINT_AEQCTL_ITR_INDX_SHIFT 11 |
| #define I40E_PFINT_AEQCTL_ITR_INDX_MASK (0x3 << I40E_PFINT_AEQCTL_ITR_INDX_SHIFT) |
| #define I40E_PFINT_AEQCTL_MSIX0_INDX_SHIFT 13 |
| #define I40E_PFINT_AEQCTL_MSIX0_INDX_MASK (0x7 << I40E_PFINT_AEQCTL_MSIX0_INDX_SHIFT) |
| #define I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT 30 |
| #define I40E_PFINT_AEQCTL_CAUSE_ENA_MASK (0x1 << I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT) |
| #define I40E_PFINT_AEQCTL_INTEVENT_SHIFT 31 |
| #define I40E_PFINT_AEQCTL_INTEVENT_MASK (0x1 << I40E_PFINT_AEQCTL_INTEVENT_SHIFT) |
| #define I40E_PFINT_CEQCTL(_INTPF) (0x00036800 + ((_INTPF) * 4)) /* _i=0...511 */ |
| #define I40E_PFINT_CEQCTL_MAX_INDEX 511 |
| #define I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT 0 |
| #define I40E_PFINT_CEQCTL_MSIX_INDX_MASK (0xFF << I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT) |
| #define I40E_PFINT_CEQCTL_ITR_INDX_SHIFT 11 |
| #define I40E_PFINT_CEQCTL_ITR_INDX_MASK (0x3 << I40E_PFINT_CEQCTL_ITR_INDX_SHIFT) |
| #define I40E_PFINT_CEQCTL_MSIX0_INDX_SHIFT 13 |
| #define I40E_PFINT_CEQCTL_MSIX0_INDX_MASK (0x7 << I40E_PFINT_CEQCTL_MSIX0_INDX_SHIFT) |
| #define I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT 16 |
| #define I40E_PFINT_CEQCTL_NEXTQ_INDX_MASK (0x7FF << I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT) |
| #define I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT 27 |
| #define I40E_PFINT_CEQCTL_NEXTQ_TYPE_MASK (0x3 << I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT) |
| #define I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT 30 |
| #define I40E_PFINT_CEQCTL_CAUSE_ENA_MASK (0x1 << I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT) |
| #define I40E_PFINT_CEQCTL_INTEVENT_SHIFT 31 |
| #define I40E_PFINT_CEQCTL_INTEVENT_MASK (0x1 << I40E_PFINT_CEQCTL_INTEVENT_SHIFT) |
| #define I40E_PFINT_DYN_CTL0 0x00038480 |
| #define I40E_PFINT_DYN_CTL0_INTENA_SHIFT 0 |
| #define I40E_PFINT_DYN_CTL0_INTENA_MASK (0x1 << I40E_PFINT_DYN_CTL0_INTENA_SHIFT) |
| #define I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT 1 |
| #define I40E_PFINT_DYN_CTL0_CLEARPBA_MASK (0x1 << I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT) |
| #define I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT 2 |
| #define I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK (0x1 << I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT) |
| #define I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT 3 |
| #define I40E_PFINT_DYN_CTL0_ITR_INDX_MASK (0x3 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
| #define I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT 5 |
| #define I40E_PFINT_DYN_CTL0_INTERVAL_MASK (0xFFF << I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT) |
| #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT 24 |
| #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK (0x1 << I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT) |
| #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT 25 |
| #define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK (0x3 << I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT) |
| #define I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT 31 |
| #define I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK (0x1 << I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT) |
| #define I40E_PFINT_DYN_CTLN(_INTPF) (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */ |
| #define I40E_PFINT_DYN_CTLN_MAX_INDEX 511 |
| #define I40E_PFINT_DYN_CTLN_INTENA_SHIFT 0 |
| #define I40E_PFINT_DYN_CTLN_INTENA_MASK (0x1 << I40E_PFINT_DYN_CTLN_INTENA_SHIFT) |
| #define I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT 1 |
| #define I40E_PFINT_DYN_CTLN_CLEARPBA_MASK (0x1 << I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT) |
| #define I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT 2 |
| #define I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK (0x1 << I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT) |
| #define I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT 3 |
| #define I40E_PFINT_DYN_CTLN_ITR_INDX_MASK (0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
| #define I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT 5 |
| #define I40E_PFINT_DYN_CTLN_INTERVAL_MASK (0xFFF << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT) |
| #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT 24 |
| #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK (0x1 << I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT) |
| #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT 25 |
| #define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK (0x3 << I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT) |
| #define I40E_PFINT_DYN_CTLN_INTENA_MSK_SHIFT 31 |
| #define I40E_PFINT_DYN_CTLN_INTENA_MSK_MASK (0x1 << I40E_PFINT_DYN_CTLN_INTENA_MSK_SHIFT) |
| #define I40E_PFINT_GPIO_ENA 0x00088080 |
| #define I40E_PFINT_GPIO_ENA_GPIO0_ENA_SHIFT 0 |
| #define I40E_PFINT_GPIO_ENA_GPIO0_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO0_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO1_ENA_SHIFT 1 |
| #define I40E_PFINT_GPIO_ENA_GPIO1_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO1_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO2_ENA_SHIFT 2 |
| #define I40E_PFINT_GPIO_ENA_GPIO2_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO2_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO3_ENA_SHIFT 3 |
| #define I40E_PFINT_GPIO_ENA_GPIO3_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO3_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO4_ENA_SHIFT 4 |
| #define I40E_PFINT_GPIO_ENA_GPIO4_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO4_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO5_ENA_SHIFT 5 |
| #define I40E_PFINT_GPIO_ENA_GPIO5_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO5_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO6_ENA_SHIFT 6 |
| #define I40E_PFINT_GPIO_ENA_GPIO6_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO6_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO7_ENA_SHIFT 7 |
| #define I40E_PFINT_GPIO_ENA_GPIO7_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO7_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO8_ENA_SHIFT 8 |
| #define I40E_PFINT_GPIO_ENA_GPIO8_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO8_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO9_ENA_SHIFT 9 |
| #define I40E_PFINT_GPIO_ENA_GPIO9_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO9_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO10_ENA_SHIFT 10 |
| #define I40E_PFINT_GPIO_ENA_GPIO10_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO10_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO11_ENA_SHIFT 11 |
| #define I40E_PFINT_GPIO_ENA_GPIO11_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO11_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO12_ENA_SHIFT 12 |
| #define I40E_PFINT_GPIO_ENA_GPIO12_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO12_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO13_ENA_SHIFT 13 |
| #define I40E_PFINT_GPIO_ENA_GPIO13_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO13_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO14_ENA_SHIFT 14 |
| #define I40E_PFINT_GPIO_ENA_GPIO14_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO14_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO15_ENA_SHIFT 15 |
| #define I40E_PFINT_GPIO_ENA_GPIO15_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO15_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO16_ENA_SHIFT 16 |
| #define I40E_PFINT_GPIO_ENA_GPIO16_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO16_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO17_ENA_SHIFT 17 |
| #define I40E_PFINT_GPIO_ENA_GPIO17_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO17_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO18_ENA_SHIFT 18 |
| #define I40E_PFINT_GPIO_ENA_GPIO18_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO18_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO19_ENA_SHIFT 19 |
| #define I40E_PFINT_GPIO_ENA_GPIO19_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO19_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO20_ENA_SHIFT 20 |
| #define I40E_PFINT_GPIO_ENA_GPIO20_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO20_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO21_ENA_SHIFT 21 |
| #define I40E_PFINT_GPIO_ENA_GPIO21_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO21_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO22_ENA_SHIFT 22 |
| #define I40E_PFINT_GPIO_ENA_GPIO22_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO22_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO23_ENA_SHIFT 23 |
| #define I40E_PFINT_GPIO_ENA_GPIO23_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO23_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO24_ENA_SHIFT 24 |
| #define I40E_PFINT_GPIO_ENA_GPIO24_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO24_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO25_ENA_SHIFT 25 |
| #define I40E_PFINT_GPIO_ENA_GPIO25_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO25_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO26_ENA_SHIFT 26 |
| #define I40E_PFINT_GPIO_ENA_GPIO26_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO26_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO27_ENA_SHIFT 27 |
| #define I40E_PFINT_GPIO_ENA_GPIO27_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO27_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO28_ENA_SHIFT 28 |
| #define I40E_PFINT_GPIO_ENA_GPIO28_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO28_ENA_SHIFT) |
| #define I40E_PFINT_GPIO_ENA_GPIO29_ENA_SHIFT 29 |
| #define I40E_PFINT_GPIO_ENA_GPIO29_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO29_ENA_SHIFT) |
| #define I40E_PFINT_ICR0 0x00038780 |
| #define I40E_PFINT_ICR0_INTEVENT_SHIFT 0 |
| #define I40E_PFINT_ICR0_INTEVENT_MASK (0x1 << I40E_PFINT_ICR0_INTEVENT_SHIFT) |
| #define I40E_PFINT_ICR0_QUEUE_0_SHIFT 1 |
| #define I40E_PFINT_ICR0_QUEUE_0_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_0_SHIFT) |
| #define I40E_PFINT_ICR0_QUEUE_1_SHIFT 2 |
| #define I40E_PFINT_ICR0_QUEUE_1_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_1_SHIFT) |
| #define I40E_PFINT_ICR0_QUEUE_2_SHIFT 3 |
| #define I40E_PFINT_ICR0_QUEUE_2_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_2_SHIFT) |
| #define I40E_PFINT_ICR0_QUEUE_3_SHIFT 4 |
| #define I40E_PFINT_ICR0_QUEUE_3_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_3_SHIFT) |
| #define I40E_PFINT_ICR0_QUEUE_4_SHIFT 5 |
| #define I40E_PFINT_ICR0_QUEUE_4_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_4_SHIFT) |
| #define I40E_PFINT_ICR0_QUEUE_5_SHIFT 6 |
| #define I40E_PFINT_ICR0_QUEUE_5_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_5_SHIFT) |
| #define I40E_PFINT_ICR0_QUEUE_6_SHIFT 7 |
| #define I40E_PFINT_ICR0_QUEUE_6_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_6_SHIFT) |
| #define I40E_PFINT_ICR0_QUEUE_7_SHIFT 8 |
| #define I40E_PFINT_ICR0_QUEUE_7_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_7_SHIFT) |
| #define I40E_PFINT_ICR0_ECC_ERR_SHIFT 16 |
| #define I40E_PFINT_ICR0_ECC_ERR_MASK (0x1 << I40E_PFINT_ICR0_ECC_ERR_SHIFT) |
| #define I40E_PFINT_ICR0_MAL_DETECT_SHIFT 19 |
| #define I40E_PFINT_ICR0_MAL_DETECT_MASK (0x1 << I40E_PFINT_ICR0_MAL_DETECT_SHIFT) |
| #define I40E_PFINT_ICR0_GRST_SHIFT 20 |
| #define I40E_PFINT_ICR0_GRST_MASK (0x1 << I40E_PFINT_ICR0_GRST_SHIFT) |
| #define I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT 21 |
| #define I40E_PFINT_ICR0_PCI_EXCEPTION_MASK (0x1 << I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT) |
| #define I40E_PFINT_ICR0_GPIO_SHIFT 22 |
| #define I40E_PFINT_ICR0_GPIO_MASK (0x1 << I40E_PFINT_ICR0_GPIO_SHIFT) |
| #define I40E_PFINT_ICR0_TIMESYNC_SHIFT 23 |
| #define I40E_PFINT_ICR0_TIMESYNC_MASK (0x1 << I40E_PFINT_ICR0_TIMESYNC_SHIFT) |
| #define I40E_PFINT_ICR0_LINK_STAT_CHANGE_SHIFT 25 |
| #define I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK (0x1 << I40E_PFINT_ICR0_LINK_STAT_CHANGE_SHIFT) |
| #define I40E_PFINT_ICR0_HMC_ERR_SHIFT 26 |
| #define I40E_PFINT_ICR0_HMC_ERR_MASK (0x1 << I40E_PFINT_ICR0_HMC_ERR_SHIFT) |
| #define I40E_PFINT_ICR0_PE_CRITERR_SHIFT 28 |
| #define I40E_PFINT_ICR0_PE_CRITERR_MASK (0x1 << I40E_PFINT_ICR0_PE_CRITERR_SHIFT) |
| #define I40E_PFINT_ICR0_VFLR_SHIFT 29 |
| #define I40E_PFINT_ICR0_VFLR_MASK (0x1 << I40E_PFINT_ICR0_VFLR_SHIFT) |
| #define I40E_PFINT_ICR0_ADMINQ_SHIFT 30 |
| #define I40E_PFINT_ICR0_ADMINQ_MASK (0x1 << I40E_PFINT_ICR0_ADMINQ_SHIFT) |
| #define I40E_PFINT_ICR0_SWINT_SHIFT 31 |
| #define I40E_PFINT_ICR0_SWINT_MASK (0x1 << I40E_PFINT_ICR0_SWINT_SHIFT) |
| #define I40E_PFINT_ICR0_ENA 0x00038800 |
| #define I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT 16 |
| #define I40E_PFINT_ICR0_ENA_ECC_ERR_MASK (0x1 << I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT) |
| #define I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT 19 |
| #define I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK (0x1 << I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT) |
| #define I40E_PFINT_ICR0_ENA_GRST_SHIFT 20 |
| #define I40E_PFINT_ICR0_ENA_GRST_MASK (0x1 << I40E_PFINT_ICR0_ENA_GRST_SHIFT) |
| #define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT 21 |
| #define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK (0x1 << I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT) |
| #define I40E_PFINT_ICR0_ENA_GPIO_SHIFT 22 |
| #define I40E_PFINT_ICR0_ENA_GPIO_MASK (0x1 << I40E_PFINT_ICR0_ENA_GPIO_SHIFT) |
| #define I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT 23 |
| #define I40E_PFINT_ICR0_ENA_TIMESYNC_MASK (0x1 << I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT) |
| #define I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT 25 |
| #define I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK (0x1 << I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT) |
| #define I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT 26 |
| #define I40E_PFINT_ICR0_ENA_HMC_ERR_MASK (0x1 << I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT) |
| #define I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT 28 |
| #define I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK (0x1 << I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT) |
| #define I40E_PFINT_ICR0_ENA_VFLR_SHIFT 29 |
| #define I40E_PFINT_ICR0_ENA_VFLR_MASK (0x1 << I40E_PFINT_ICR0_ENA_VFLR_SHIFT) |
| #define I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT 30 |
| #define I40E_PFINT_ICR0_ENA_ADMINQ_MASK (0x1 << I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT) |
| #define I40E_PFINT_ICR0_ENA_RSVD_SHIFT 31 |
| #define I40E_PFINT_ICR0_ENA_RSVD_MASK (0x1 << I40E_PFINT_ICR0_ENA_RSVD_SHIFT) |
| #define I40E_PFINT_ITR0(_i) (0x00038000 + ((_i) * 128)) /* _i=0...2 */ |
| #define I40E_PFINT_ITR0_MAX_INDEX 2 |
| #define I40E_PFINT_ITR0_INTERVAL_SHIFT 0 |
| #define I40E_PFINT_ITR0_INTERVAL_MASK (0xFFF << I40E_PFINT_ITR0_INTERVAL_SHIFT) |
| #define I40E_PFINT_ITRN(_i, _INTPF) (0x00030000 + ((_i) * 2048 + (_INTPF) * 4)) |
| #define I40E_PFINT_ITRN_MAX_INDEX 2 |
| #define I40E_PFINT_ITRN_INTERVAL_SHIFT 0 |
| #define I40E_PFINT_ITRN_INTERVAL_MASK (0xFFF << I40E_PFINT_ITRN_INTERVAL_SHIFT) |
| #define I40E_PFINT_LNKLST0 0x00038500 |
| #define I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT 0 |
| #define I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK (0x7FF << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
| #define I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT 11 |
| #define I40E_PFINT_LNKLST0_FIRSTQ_TYPE_MASK (0x3 << I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT) |
| #define I40E_PFINT_LNKLSTN(_INTPF) (0x00035000 + ((_INTPF) * 4)) /* _i=0...511 */ |
| #define I40E_PFINT_LNKLSTN_MAX_INDEX 511 |
| #define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0 |
| #define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK (0x7FF << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
| #define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11 |
| #define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_MASK (0x3 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT) |
| #define I40E_PFINT_RATE0 0x00038580 |
| #define I40E_PFINT_RATE0_INTERVAL_SHIFT 0 |
| #define I40E_PFINT_RATE0_INTERVAL_MASK (0x3F << I40E_PFINT_RATE0_INTERVAL_SHIFT) |
| #define I40E_PFINT_RATE0_INTRL_ENA_SHIFT 6 |
| #define I40E_PFINT_RATE0_INTRL_ENA_MASK (0x1 << I40E_PFINT_RATE0_INTRL_ENA_SHIFT) |
| #define I40E_PFINT_RATEN(_INTPF) (0x00035800 + ((_INTPF) * 4)) /* _i=0...511 */ |
| #define I40E_PFINT_RATEN_MAX_INDEX 511 |
| #define I40E_PFINT_RATEN_INTERVAL_SHIFT 0 |
| #define I40E_PFINT_RATEN_INTERVAL_MASK (0x3F << I40E_PFINT_RATEN_INTERVAL_SHIFT) |
| #define I40E_PFINT_RATEN_INTRL_ENA_SHIFT 6 |
| #define I40E_PFINT_RATEN_INTRL_ENA_MASK (0x1 << I40E_PFINT_RATEN_INTRL_ENA_SHIFT) |
| #define I40E_PFINT_STAT_CTL0 0x00038400 |
| #define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2 |
| #define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK (0x3 << I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT) |
| #define I40E_QINT_RQCTL(_Q) (0x0003A000 + ((_Q) * 4)) /* _i=0...1535 */ |
| #define I40E_QINT_RQCTL_MAX_INDEX 1535 |
| #define I40E_QINT_RQCTL_MSIX_INDX_SHIFT 0 |
| #define I40E_QINT_RQCTL_MSIX_INDX_MASK (0xFF << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
| #define I40E_QINT_RQCTL_ITR_INDX_SHIFT 11 |
| #define I40E_QINT_RQCTL_ITR_INDX_MASK (0x3 << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
| #define I40E_QINT_RQCTL_MSIX0_INDX_SHIFT 13 |
| #define I40E_QINT_RQCTL_MSIX0_INDX_MASK (0x7 << I40E_QINT_RQCTL_MSIX0_INDX_SHIFT) |
| #define I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT 16 |
| #define I40E_QINT_RQCTL_NEXTQ_INDX_MASK (0x7FF << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
| #define I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT 27 |
| #define I40E_QINT_RQCTL_NEXTQ_TYPE_MASK (0x3 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
| #define I40E_QINT_RQCTL_CAUSE_ENA_SHIFT 30 |
| #define I40E_QINT_RQCTL_CAUSE_ENA_MASK (0x1 << I40E_QINT_RQCTL_CAUSE_ENA_SHIFT) |
| #define I40E_QINT_RQCTL_INTEVENT_SHIFT 31 |
| #define I40E_QINT_RQCTL_INTEVENT_MASK (0x1 << I40E_QINT_RQCTL_INTEVENT_SHIFT) |
| #define I40E_QINT_TQCTL(_Q) (0x0003C000 + ((_Q) * 4)) /* _i=0...1535 */ |
| #define I40E_QINT_TQCTL_MAX_INDEX 1535 |
| #define I40E_QINT_TQCTL_MSIX_INDX_SHIFT 0 |
| #define I40E_QINT_TQCTL_MSIX_INDX_MASK (0xFF << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
| #define I40E_QINT_TQCTL_ITR_INDX_SHIFT 11 |
| #define I40E_QINT_TQCTL_ITR_INDX_MASK (0x3 << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
| #define I40E_QINT_TQCTL_MSIX0_INDX_SHIFT 13 |
| #define I40E_QINT_TQCTL_MSIX0_INDX_MASK (0x7 << I40E_QINT_TQCTL_MSIX0_INDX_SHIFT) |
| #define I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT 16 |
| #define I40E_QINT_TQCTL_NEXTQ_INDX_MASK (0x7FF << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) |
| #define I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT 27 |
| #define I40E_QINT_TQCTL_NEXTQ_TYPE_MASK (0x3 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT) |
| #define I40E_QINT_TQCTL_CAUSE_ENA_SHIFT 30 |
| #define I40E_QINT_TQCTL_CAUSE_ENA_MASK (0x1 << I40E_QINT_TQCTL_CAUSE_ENA_SHIFT) |
| #define I40E_QINT_TQCTL_INTEVENT_SHIFT 31 |
| #define I40E_QINT_TQCTL_INTEVENT_MASK (0x1 << I40E_QINT_TQCTL_INTEVENT_SHIFT) |
| #define I40E_VFINT_DYN_CTL0(_VF) (0x0002A400 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VFINT_DYN_CTL0_MAX_INDEX 127 |
| #define I40E_VFINT_DYN_CTL0_INTENA_SHIFT 0 |
| #define I40E_VFINT_DYN_CTL0_INTENA_MASK (0x1 << I40E_VFINT_DYN_CTL0_INTENA_SHIFT) |
| #define I40E_VFINT_DYN_CTL0_CLEARPBA_SHIFT 1 |
| #define I40E_VFINT_DYN_CTL0_CLEARPBA_MASK (0x1 << I40E_VFINT_DYN_CTL0_CLEARPBA_SHIFT) |
| #define I40E_VFINT_DYN_CTL0_SWINT_TRIG_SHIFT 2 |
| #define I40E_VFINT_DYN_CTL0_SWINT_TRIG_MASK (0x1 << I40E_VFINT_DYN_CTL0_SWINT_TRIG_SHIFT) |
| #define I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT 3 |
| #define I40E_VFINT_DYN_CTL0_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
| #define I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT 5 |
| #define I40E_VFINT_DYN_CTL0_INTERVAL_MASK (0xFFF << I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT) |
| #define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT 24 |
| #define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK (0x1 << I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT) |
| #define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_SHIFT 25 |
| #define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTL0_SW_ITR_INDX_SHIFT) |
| #define I40E_VFINT_DYN_CTL0_INTENA_MSK_SHIFT 31 |
| #define I40E_VFINT_DYN_CTL0_INTENA_MSK_MASK (0x1 << I40E_VFINT_DYN_CTL0_INTENA_MSK_SHIFT) |
| #define I40E_VFINT_DYN_CTLN(_INTVF) (0x00024800 + ((_INTVF) * 4)) /* _i=0...511 */ |
| #define I40E_VFINT_DYN_CTLN_MAX_INDEX 511 |
| #define I40E_VFINT_DYN_CTLN_INTENA_SHIFT 0 |
| #define I40E_VFINT_DYN_CTLN_INTENA_MASK (0x1 << I40E_VFINT_DYN_CTLN_INTENA_SHIFT) |
| #define I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT 1 |
| #define I40E_VFINT_DYN_CTLN_CLEARPBA_MASK (0x1 << I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT) |
| #define I40E_VFINT_DYN_CTLN_SWINT_TRIG_SHIFT 2 |
| #define I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK (0x1 << I40E_VFINT_DYN_CTLN_SWINT_TRIG_SHIFT) |
| #define I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT 3 |
| #define I40E_VFINT_DYN_CTLN_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT) |
| #define I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT 5 |
| #define I40E_VFINT_DYN_CTLN_INTERVAL_MASK (0xFFF << I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT) |
| #define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT 24 |
| #define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK (0x1 << I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT) |
| #define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_SHIFT 25 |
| #define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTLN_SW_ITR_INDX_SHIFT) |
| #define I40E_VFINT_DYN_CTLN_INTENA_MSK_SHIFT 31 |
| #define I40E_VFINT_DYN_CTLN_INTENA_MSK_MASK (0x1 << I40E_VFINT_DYN_CTLN_INTENA_MSK_SHIFT) |
| #define I40E_VFINT_ICR0(_VF) (0x0002BC00 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VFINT_ICR0_MAX_INDEX 127 |
| #define I40E_VFINT_ICR0_INTEVENT_SHIFT 0 |
| #define I40E_VFINT_ICR0_INTEVENT_MASK (0x1 << I40E_VFINT_ICR0_INTEVENT_SHIFT) |
| #define I40E_VFINT_ICR0_QUEUE_0_SHIFT 1 |
| #define I40E_VFINT_ICR0_QUEUE_0_MASK (0x1 << I40E_VFINT_ICR0_QUEUE_0_SHIFT) |
| #define I40E_VFINT_ICR0_QUEUE_1_SHIFT 2 |
| #define I40E_VFINT_ICR0_QUEUE_1_MASK (0x1 << I40E_VFINT_ICR0_QUEUE_1_SHIFT) |
| #define I40E_VFINT_ICR0_QUEUE_2_SHIFT 3 |
| #define I40E_VFINT_ICR0_QUEUE_2_MASK (0x1 << I40E_VFINT_ICR0_QUEUE_2_SHIFT) |
| #define I40E_VFINT_ICR0_QUEUE_3_SHIFT 4 |
| #define I40E_VFINT_ICR0_QUEUE_3_MASK (0x1 << I40E_VFINT_ICR0_QUEUE_3_SHIFT) |
| #define I40E_VFINT_ICR0_LINK_STAT_CHANGE_SHIFT 25 |
| #define I40E_VFINT_ICR0_LINK_STAT_CHANGE_MASK (0x1 << I40E_VFINT_ICR0_LINK_STAT_CHANGE_SHIFT) |
| #define I40E_VFINT_ICR0_ADMINQ_SHIFT 30 |
| #define I40E_VFINT_ICR0_ADMINQ_MASK (0x1 << I40E_VFINT_ICR0_ADMINQ_SHIFT) |
| #define I40E_VFINT_ICR0_SWINT_SHIFT 31 |
| #define I40E_VFINT_ICR0_SWINT_MASK (0x1 << I40E_VFINT_ICR0_SWINT_SHIFT) |
| #define I40E_VFINT_ICR0_ENA(_VF) (0x0002C000 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VFINT_ICR0_ENA_MAX_INDEX 127 |
| #define I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT 25 |
| #define I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK (0x1 << I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT) |
| #define I40E_VFINT_ICR0_ENA_ADMINQ_SHIFT 30 |
| #define I40E_VFINT_ICR0_ENA_ADMINQ_MASK (0x1 << I40E_VFINT_ICR0_ENA_ADMINQ_SHIFT) |
| #define I40E_VFINT_ICR0_ENA_RSVD_SHIFT 31 |
| #define I40E_VFINT_ICR0_ENA_RSVD_MASK (0x1 << I40E_VFINT_ICR0_ENA_RSVD_SHIFT) |
| #define I40E_VFINT_ITR0(_i, _VF) (0x00028000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...2, _VF=0...127 */ |
| #define I40E_VFINT_ITR0_MAX_INDEX 2 |
| #define I40E_VFINT_ITR0_INTERVAL_SHIFT 0 |
| #define I40E_VFINT_ITR0_INTERVAL_MASK (0xFFF << I40E_VFINT_ITR0_INTERVAL_SHIFT) |
| #define I40E_VFINT_ITRN(_i, _INTVF) (0x00020000 + ((_i) * 2048 + (_INTVF) * 4)) |
| #define I40E_VFINT_ITRN_MAX_INDEX 2 |
| #define I40E_VFINT_ITRN_INTERVAL_SHIFT 0 |
| #define I40E_VFINT_ITRN_INTERVAL_MASK (0xFFF << I40E_VFINT_ITRN_INTERVAL_SHIFT) |
| #define I40E_VFINT_STAT_CTL0(_VF) (0x0002A000 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VFINT_STAT_CTL0_MAX_INDEX 127 |
| #define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2 |
| #define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_MASK (0x3 << I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT) |
| #define I40E_VPINT_AEQCTL(_VF) (0x0002B800 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VPINT_AEQCTL_MAX_INDEX 127 |
| #define I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT 0 |
| #define I40E_VPINT_AEQCTL_MSIX_INDX_MASK (0xFF << I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT) |
| #define I40E_VPINT_AEQCTL_ITR_INDX_SHIFT 11 |
| #define I40E_VPINT_AEQCTL_ITR_INDX_MASK (0x3 << I40E_VPINT_AEQCTL_ITR_INDX_SHIFT) |
| #define I40E_VPINT_AEQCTL_MSIX0_INDX_SHIFT 13 |
| #define I40E_VPINT_AEQCTL_MSIX0_INDX_MASK (0x7 << I40E_VPINT_AEQCTL_MSIX0_INDX_SHIFT) |
| #define I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT 30 |
| #define I40E_VPINT_AEQCTL_CAUSE_ENA_MASK (0x1 << I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT) |
| #define I40E_VPINT_AEQCTL_INTEVENT_SHIFT 31 |
| #define I40E_VPINT_AEQCTL_INTEVENT_MASK (0x1 << I40E_VPINT_AEQCTL_INTEVENT_SHIFT) |
| #define I40E_VPINT_CEQCTL(_INTVF) (0x00026800 + ((_INTVF) * 4)) /* _i=0...511 */ |
| #define I40E_VPINT_CEQCTL_MAX_INDEX 511 |
| #define I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT 0 |
| #define I40E_VPINT_CEQCTL_MSIX_INDX_MASK (0xFF << I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT) |
| #define I40E_VPINT_CEQCTL_ITR_INDX_SHIFT 11 |
| #define I40E_VPINT_CEQCTL_ITR_INDX_MASK (0x3 << I40E_VPINT_CEQCTL_ITR_INDX_SHIFT) |
| #define I40E_VPINT_CEQCTL_MSIX0_INDX_SHIFT 13 |
| #define I40E_VPINT_CEQCTL_MSIX0_INDX_MASK (0x7 << I40E_VPINT_CEQCTL_MSIX0_INDX_SHIFT) |
| #define I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT 16 |
| #define I40E_VPINT_CEQCTL_NEXTQ_INDX_MASK (0x7FF << I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT) |
| #define I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT 27 |
| #define I40E_VPINT_CEQCTL_NEXTQ_TYPE_MASK (0x3 << I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT) |
| #define I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT 30 |
| #define I40E_VPINT_CEQCTL_CAUSE_ENA_MASK (0x1 << I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT) |
| #define I40E_VPINT_CEQCTL_INTEVENT_SHIFT 31 |
| #define I40E_VPINT_CEQCTL_INTEVENT_MASK (0x1 << I40E_VPINT_CEQCTL_INTEVENT_SHIFT) |
| #define I40E_VPINT_LNKLST0(_VF) (0x0002A800 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VPINT_LNKLST0_MAX_INDEX 127 |
| #define I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT 0 |
| #define I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK (0x7FF << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
| #define I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT 11 |
| #define I40E_VPINT_LNKLST0_FIRSTQ_TYPE_MASK (0x3 << I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT) |
| #define I40E_VPINT_LNKLSTN(_INTVF) (0x00025000 + ((_INTVF) * 4)) /* _i=0...511 */ |
| #define I40E_VPINT_LNKLSTN_MAX_INDEX 511 |
| #define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0 |
| #define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK (0x7FF << I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
| #define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11 |
| #define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK (0x3 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT) |
| #define I40E_VPINT_RATE0(_VF) (0x0002AC00 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VPINT_RATE0_MAX_INDEX 127 |
| #define I40E_VPINT_RATE0_INTERVAL_SHIFT 0 |
| #define I40E_VPINT_RATE0_INTERVAL_MASK (0x3F << I40E_VPINT_RATE0_INTERVAL_SHIFT) |
| #define I40E_VPINT_RATE0_INTRL_ENA_SHIFT 6 |
| #define I40E_VPINT_RATE0_INTRL_ENA_MASK (0x1 << I40E_VPINT_RATE0_INTRL_ENA_SHIFT) |
| #define I40E_VPINT_RATEN(_INTVF) (0x00025800 + ((_INTVF) * 4)) /* _i=0...511 */ |
| #define I40E_VPINT_RATEN_MAX_INDEX 511 |
| #define I40E_VPINT_RATEN_INTERVAL_SHIFT 0 |
| #define I40E_VPINT_RATEN_INTERVAL_MASK (0x3F << I40E_VPINT_RATEN_INTERVAL_SHIFT) |
| #define I40E_VPINT_RATEN_INTRL_ENA_SHIFT 6 |
| #define I40E_VPINT_RATEN_INTRL_ENA_MASK (0x1 << I40E_VPINT_RATEN_INTRL_ENA_SHIFT) |
| #define I40E_GL_RDPU_CNTRL 0x00051060 |
| #define I40E_GL_RDPU_CNTRL_RX_PAD_EN_SHIFT 0 |
| #define I40E_GL_RDPU_CNTRL_RX_PAD_EN_MASK (0x1 << I40E_GL_RDPU_CNTRL_RX_PAD_EN_SHIFT) |
| #define I40E_GL_RDPU_CNTRL_ECO_SHIFT 1 |
| #define I40E_GL_RDPU_CNTRL_ECO_MASK (0x7FFFFFFF << I40E_GL_RDPU_CNTRL_ECO_SHIFT) |
| #define I40E_GLLAN_RCTL_0 0x0012A500 |
| #define I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT 0 |
| #define I40E_GLLAN_RCTL_0_PXE_MODE_MASK (0x1 << I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT) |
| #define I40E_GLLAN_TSOMSK_F 0x000442D8 |
| #define I40E_GLLAN_TSOMSK_F_TCPMSKF_SHIFT 0 |
| #define I40E_GLLAN_TSOMSK_F_TCPMSKF_MASK (0xFFF << I40E_GLLAN_TSOMSK_F_TCPMSKF_SHIFT) |
| #define I40E_GLLAN_TSOMSK_L 0x000442E0 |
| #define I40E_GLLAN_TSOMSK_L_TCPMSKL_SHIFT 0 |
| #define I40E_GLLAN_TSOMSK_L_TCPMSKL_MASK (0xFFF << I40E_GLLAN_TSOMSK_L_TCPMSKL_SHIFT) |
| #define I40E_GLLAN_TSOMSK_M 0x000442DC |
| #define I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT 0 |
| #define I40E_GLLAN_TSOMSK_M_TCPMSKM_MASK (0xFFF << I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT) |
| #define I40E_GLLAN_TXPRE_QDIS(_i) (0x000E6500 + ((_i) * 4)) /* i=0..11 */ |
| #define I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT 0 |
| #define I40E_GLLAN_TXPRE_QDIS_QINDX_MASK (0x7FF << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT) |
| #define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT 30 |
| #define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK (0x1 << I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT) |
| #define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT 31 |
| #define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK (0x1 << I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT) |
| |
| #define I40E_PFLAN_QALLOC 0x001C0400 |
| #define I40E_PFLAN_QALLOC_FIRSTQ_SHIFT 0 |
| #define I40E_PFLAN_QALLOC_FIRSTQ_MASK (0x7FF << I40E_PFLAN_QALLOC_FIRSTQ_SHIFT) |
| #define I40E_PFLAN_QALLOC_LASTQ_SHIFT 16 |
| #define I40E_PFLAN_QALLOC_LASTQ_MASK (0x7FF << I40E_PFLAN_QALLOC_LASTQ_SHIFT) |
| #define I40E_PFLAN_QALLOC_VALID_SHIFT 31 |
| #define I40E_PFLAN_QALLOC_VALID_MASK (0x1 << I40E_PFLAN_QALLOC_VALID_SHIFT) |
| #define I40E_QRX_ENA(_Q) (0x00120000 + ((_Q) * 4)) /* _i=0...1535 */ |
| #define I40E_QRX_ENA_MAX_INDEX 1535 |
| #define I40E_QRX_ENA_QENA_REQ_SHIFT 0 |
| #define I40E_QRX_ENA_QENA_REQ_MASK (0x1 << I40E_QRX_ENA_QENA_REQ_SHIFT) |
| #define I40E_QRX_ENA_FAST_QDIS_SHIFT 1 |
| #define I40E_QRX_ENA_FAST_QDIS_MASK (0x1 << I40E_QRX_ENA_FAST_QDIS_SHIFT) |
| #define I40E_QRX_ENA_QENA_STAT_SHIFT 2 |
| #define I40E_QRX_ENA_QENA_STAT_MASK (0x1 << I40E_QRX_ENA_QENA_STAT_SHIFT) |
| #define I40E_QRX_TAIL(_Q) (0x00128000 + ((_Q) * 4)) /* _i=0...1535 */ |
| #define I40E_QRX_TAIL_MAX_INDEX 1535 |
| #define I40E_QRX_TAIL_TAIL_SHIFT 0 |
| #define I40E_QRX_TAIL_TAIL_MASK (0x1FFF << I40E_QRX_TAIL_TAIL_SHIFT) |
| #define I40E_QTX_CTL(_Q) (0x00104000 + ((_Q) * 4)) /* _i=0...1535 */ |
| #define I40E_QTX_CTL_MAX_INDEX 1535 |
| #define I40E_QTX_CTL_PFVF_Q_SHIFT 0 |
| #define I40E_QTX_CTL_PFVF_Q_MASK (0x3 << I40E_QTX_CTL_PFVF_Q_SHIFT) |
| #define I40E_QTX_CTL_PF_INDX_SHIFT 2 |
| #define I40E_QTX_CTL_PF_INDX_MASK (0xF << I40E_QTX_CTL_PF_INDX_SHIFT) |
| #define I40E_QTX_CTL_VFVM_INDX_SHIFT 7 |
| #define I40E_QTX_CTL_VFVM_INDX_MASK (0x1FF << I40E_QTX_CTL_VFVM_INDX_SHIFT) |
| #define I40E_QTX_ENA(_Q) (0x00100000 + ((_Q) * 4)) /* _i=0...1535 */ |
| #define I40E_QTX_ENA_MAX_INDEX 1535 |
| #define I40E_QTX_ENA_QENA_REQ_SHIFT 0 |
| #define I40E_QTX_ENA_QENA_REQ_MASK (0x1 << I40E_QTX_ENA_QENA_REQ_SHIFT) |
| #define I40E_QTX_ENA_FAST_QDIS_SHIFT 1 |
| #define I40E_QTX_ENA_FAST_QDIS_MASK (0x1 << I40E_QTX_ENA_FAST_QDIS_SHIFT) |
| #define I40E_QTX_ENA_QENA_STAT_SHIFT 2 |
| #define I40E_QTX_ENA_QENA_STAT_MASK (0x1 << I40E_QTX_ENA_QENA_STAT_SHIFT) |
| #define I40E_QTX_HEAD(_Q) (0x000E4000 + ((_Q) * 4)) /* _i=0...1535 */ |
| #define I40E_QTX_HEAD_MAX_INDEX 1535 |
| #define I40E_QTX_HEAD_HEAD_SHIFT 0 |
| #define I40E_QTX_HEAD_HEAD_MASK (0x1FFF << I40E_QTX_HEAD_HEAD_SHIFT) |
| #define I40E_QTX_HEAD_RS_PENDING_SHIFT 16 |
| #define I40E_QTX_HEAD_RS_PENDING_MASK (0x1 << I40E_QTX_HEAD_RS_PENDING_SHIFT) |
| #define I40E_QTX_TAIL(_Q) (0x00108000 + ((_Q) * 4)) /* _i=0...1535 */ |
| #define I40E_QTX_TAIL_MAX_INDEX 1535 |
| #define I40E_QTX_TAIL_TAIL_SHIFT 0 |
| #define I40E_QTX_TAIL_TAIL_MASK (0x1FFF << I40E_QTX_TAIL_TAIL_SHIFT) |
| #define I40E_VPLAN_MAPENA(_VF) (0x00074000 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VPLAN_MAPENA_MAX_INDEX 127 |
| #define I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT 0 |
| #define I40E_VPLAN_MAPENA_TXRX_ENA_MASK (0x1 << I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT) |
| #define I40E_VPLAN_QTABLE(_i, _VF) (0x00070000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ |
| #define I40E_VPLAN_QTABLE_MAX_INDEX 15 |
| #define I40E_VPLAN_QTABLE_QINDEX_SHIFT 0 |
| #define I40E_VPLAN_QTABLE_QINDEX_MASK (0x7FF << I40E_VPLAN_QTABLE_QINDEX_SHIFT) |
| #define I40E_VSILAN_QBASE(_VSI) (0x0020C800 + ((_VSI) * 4)) /* _i=0...383 */ |
| #define I40E_VSILAN_QBASE_MAX_INDEX 383 |
| #define I40E_VSILAN_QBASE_VSIBASE_SHIFT 0 |
| #define I40E_VSILAN_QBASE_VSIBASE_MASK (0x7FF << I40E_VSILAN_QBASE_VSIBASE_SHIFT) |
| #define I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT 11 |
| #define I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK (0x1 << I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT) |
| #define I40E_VSILAN_QTABLE(_i, _VSI) (0x00200000 + ((_i) * 2048 + (_VSI) * 4)) |
| #define I40E_VSILAN_QTABLE_MAX_INDEX 7 |
| #define I40E_VSILAN_QTABLE_QINDEX_0_SHIFT 0 |
| #define I40E_VSILAN_QTABLE_QINDEX_0_MASK (0x7FF << I40E_VSILAN_QTABLE_QINDEX_0_SHIFT) |
| #define I40E_VSILAN_QTABLE_QINDEX_1_SHIFT 16 |
| #define I40E_VSILAN_QTABLE_QINDEX_1_MASK (0x7FF << I40E_VSILAN_QTABLE_QINDEX_1_SHIFT) |
| #define I40E_PRTGL_SAH 0x001E2140 |
| #define I40E_PRTGL_SAH_FC_SAH_SHIFT 0 |
| #define I40E_PRTGL_SAH_FC_SAH_MASK (0xFFFF << I40E_PRTGL_SAH_FC_SAH_SHIFT) |
| #define I40E_PRTGL_SAH_MFS_SHIFT 16 |
| #define I40E_PRTGL_SAH_MFS_MASK (0xFFFF << I40E_PRTGL_SAH_MFS_SHIFT) |
| #define I40E_PRTGL_SAL 0x001E2120 |
| #define I40E_PRTGL_SAL_FC_SAL_SHIFT 0 |
| #define I40E_PRTGL_SAL_FC_SAL_MASK (0xFFFFFFFF << I40E_PRTGL_SAL_FC_SAL_SHIFT) |
| #define I40E_PRTMAC_HLCTLA 0x001E4760 |
| #define I40E_PRTMAC_HLCTLA_DROP_US_PKTS_SHIFT 0 |
| #define I40E_PRTMAC_HLCTLA_DROP_US_PKTS_MASK (0x1 << I40E_PRTMAC_HLCTLA_DROP_US_PKTS_SHIFT) |
| #define I40E_PRTMAC_HLCTLA_RX_FWRD_CTRL_SHIFT 1 |
| #define I40E_PRTMAC_HLCTLA_RX_FWRD_CTRL_MASK (0x1 << I40E_PRTMAC_HLCTLA_RX_FWRD_CTRL_SHIFT) |
| #define I40E_PRTMAC_HLCTLA_CHOP_OS_PKT_SHIFT 2 |
| #define I40E_PRTMAC_HLCTLA_CHOP_OS_PKT_MASK (0x1 << I40E_PRTMAC_HLCTLA_CHOP_OS_PKT_SHIFT) |
| #define I40E_PRTMAC_HLCTLA_TX_HYSTERESIS_SHIFT 4 |
| #define I40E_PRTMAC_HLCTLA_TX_HYSTERESIS_MASK (0x7 << I40E_PRTMAC_HLCTLA_TX_HYSTERESIS_SHIFT) |
| #define I40E_PRTMAC_HLCTLA_HYS_FLUSH_PKT_SHIFT 7 |
| #define I40E_PRTMAC_HLCTLA_HYS_FLUSH_PKT_MASK (0x1 << I40E_PRTMAC_HLCTLA_HYS_FLUSH_PKT_SHIFT) |
| #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GCP 0x001E3130 |
| #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GCP_HSEC_CTL_RX_CHECK_SA_GCP_SHIFT 0 |
| #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GCP_HSEC_CTL_RX_CHECK_SA_GCP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GCP_HSEC_CTL_RX_CHECK_SA_GCP_SHIFT) |
| #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GPP 0x001E3290 |
| #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GPP_HSEC_CTL_RX_CHECK_SA_GPP_SHIFT 0 |
| #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GPP_HSEC_CTL_RX_CHECK_SA_GPP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GPP_HSEC_CTL_RX_CHECK_SA_GPP_SHIFT) |
| #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_PPP 0x001E3310 |
| #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_PPP_HSEC_CTL_RX_CHECK_SA_PPP_SHIFT 0 |
| #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_PPP_HSEC_CTL_RX_CHECK_SA_PPP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_PPP_HSEC_CTL_RX_CHECK_SA_PPP_SHIFT) |
| #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GCP 0x001E3100 |
| #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GCP_HSEC_CTL_RX_CHECK_UCAST_GCP_SHIFT 0 |
| #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GCP_HSEC_CTL_RX_CHECK_UCAST_GCP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GCP_HSEC_CTL_RX_CHECK_UCAST_GCP_SHIFT) |
| #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GPP 0x001E3280 |
| #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GPP_HSEC_CTL_RX_CHECK_UCAST_GPP_SHIFT 0 |
| #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GPP_HSEC_CTL_RX_CHECK_UCAST_GPP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GPP_HSEC_CTL_RX_CHECK_UCAST_GPP_SHIFT) |
| #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_PPP 0x001E3300 |
| #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_PPP_HSEC_CTL_RX_CHECK_UCAST_PPP_SHIFT 0 |
| #define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_PPP_HSEC_CTL_RX_CHECK_UCAST_PPP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_PPP_HSEC_CTL_RX_CHECK_UCAST_PPP_SHIFT) |
| #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP 0x001E30E0 |
| #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_SHIFT 0 |
| #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_SHIFT) |
| #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP 0x001E3260 |
| #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_SHIFT 0 |
| #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_SHIFT) |
| #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP 0x001E32E0 |
| #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT 0 |
| #define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT) |
| #define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL 0x001E3360 |
| #define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_SHIFT 0 |
| #define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_SHIFT) |
| #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1 0x001E3110 |
| #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_SHIFT 0 |
| #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_MASK (0xFFFFFFFF << I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_SHIFT) |
| #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2 0x001E3120 |
| #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_SHIFT 0 |
| #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_MASK (0xFFFF << I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_SHIFT) |
| #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE 0x001E30C0 |
| #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT 0 |
| #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_MASK (0x1FF << I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT) |
| #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1 0x001E3140 |
| #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_SHIFT 0 |
| #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_MASK (0xFFFFFFFF << I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_SHIFT) |
| #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2 0x001E3150 |
| #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_SHIFT 0 |
| #define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_MASK (0xFFFF << I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_SHIFT) |
| #define I40E_PRTMAC_HSEC_CTL_TX_ENABLE 0x001E3000 |
| #define I40E_PRTMAC_HSEC_CTL_TX_ENABLE_HSEC_CTL_TX_ENABLE_SHIFT 0 |
| #define I40E_PRTMAC_HSEC_CTL_TX_ENABLE_HSEC_CTL_TX_ENABLE_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_TX_ENABLE_HSEC_CTL_TX_ENABLE_SHIFT) |
| #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE 0x001E30D0 |
| #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT 0 |
| #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_MASK (0x1FF << I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT) |
| #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i) (0x001E3370 + ((_i) * 16)) |
| #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 8 |
| #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_SHIFT 0 |
| #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_MASK (0xFFFF << I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_SHIFT) |
| #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3400 + ((_i) * 16)) |
| #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX 8 |
| #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT 0 |
| #define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MASK (0xFFFF << I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT) |
| #define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1 0x001E34B0 |
| #define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_SHIFT 0 |
| #define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_MASK (0xFFFFFFFF << I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_SHIFT) |
| #define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2 0x001E34C0 |
| #define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_SHIFT 0 |
| #define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_MASK (0xFFFF << I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_SHIFT) |
| #define I40E_PRTMAC_HSECTL1 0x001E3560 |
| #define I40E_PRTMAC_HSECTL1_DROP_US_PKTS_SHIFT 0 |
| #define I40E_PRTMAC_HSECTL1_DROP_US_PKTS_MASK (0x1 << I40E_PRTMAC_HSECTL1_DROP_US_PKTS_SHIFT) |
| #define I40E_PRTMAC_HSECTL1_PAD_US_PKT_SHIFT 3 |
| #define I40E_PRTMAC_HSECTL1_PAD_US_PKT_MASK (0x1 << I40E_PRTMAC_HSECTL1_PAD_US_PKT_SHIFT) |
| #define I40E_PRTMAC_HSECTL1_TX_HYSTERESIS_SHIFT 4 |
| #define I40E_PRTMAC_HSECTL1_TX_HYSTERESIS_MASK (0x7 << I40E_PRTMAC_HSECTL1_TX_HYSTERESIS_SHIFT) |
| #define I40E_PRTMAC_HSECTL1_HYS_FLUSH_PKT_SHIFT 7 |
| #define I40E_PRTMAC_HSECTL1_HYS_FLUSH_PKT_MASK (0x1 << I40E_PRTMAC_HSECTL1_HYS_FLUSH_PKT_SHIFT) |
| #define I40E_PRTMAC_HSECTL1_EN_SFD_CHECK_SHIFT 30 |
| #define I40E_PRTMAC_HSECTL1_EN_SFD_CHECK_MASK (0x1 << I40E_PRTMAC_HSECTL1_EN_SFD_CHECK_SHIFT) |
| #define I40E_PRTMAC_HSECTL1_EN_PREAMBLE_CHECK_SHIFT 31 |
| #define I40E_PRTMAC_HSECTL1_EN_PREAMBLE_CHECK_MASK (0x1 << I40E_PRTMAC_HSECTL1_EN_PREAMBLE_CHECK_SHIFT) |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_A 0x0008C480 |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_SHIFT 0 |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_SHIFT) |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_SHIFT 2 |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_SHIFT) |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_SHIFT 4 |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_SHIFT) |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_SHIFT 6 |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_SHIFT) |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_SHIFT 8 |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_SHIFT) |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_SHIFT 10 |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_SHIFT) |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_SHIFT 12 |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_SHIFT) |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_SHIFT 14 |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_SHIFT) |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_B 0x0008C484 |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_SHIFT 0 |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_SHIFT) |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_SHIFT 2 |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_SHIFT) |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_SHIFT 4 |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_SHIFT) |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_SHIFT 6 |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_SHIFT) |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_SHIFT 8 |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_SHIFT) |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_SHIFT 10 |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_SHIFT) |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_SHIFT 12 |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_SHIFT) |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT 14 |
| #define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT) |
| #define I40E_GL_MNG_FWSM 0x000B6134 |
| #define I40E_GL_MNG_FWSM_FW_MODES_SHIFT 1 |
| #define I40E_GL_MNG_FWSM_FW_MODES_MASK (0x7 << I40E_GL_MNG_FWSM_FW_MODES_SHIFT) |
| #define I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT 6 |
| #define I40E_GL_MNG_FWSM_EEP_RELOAD_IND_MASK (0x1 << I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT) |
| #define I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_SHIFT 11 |
| #define I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_MASK (0xF << I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_SHIFT) |
| #define I40E_GL_MNG_FWSM_FW_STATUS_VALID_SHIFT 15 |
| #define I40E_GL_MNG_FWSM_FW_STATUS_VALID_MASK (0x1 << I40E_GL_MNG_FWSM_FW_STATUS_VALID_SHIFT) |
| #define I40E_GL_MNG_FWSM_RESET_CNT_SHIFT 16 |
| #define I40E_GL_MNG_FWSM_RESET_CNT_MASK (0x7 << I40E_GL_MNG_FWSM_RESET_CNT_SHIFT) |
| #define I40E_GL_MNG_FWSM_EXT_ERR_IND_SHIFT 19 |
| #define I40E_GL_MNG_FWSM_EXT_ERR_IND_MASK (0x3F << I40E_GL_MNG_FWSM_EXT_ERR_IND_SHIFT) |
| #define I40E_GL_MNG_FWSM_RSVD_SHIFT 25 |
| #define I40E_GL_MNG_FWSM_RSVD_MASK (0x1 << I40E_GL_MNG_FWSM_RSVD_SHIFT) |
| #define I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_SHIFT 26 |
| #define I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_MASK (0x1 << I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_SHIFT) |
| #define I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_SHIFT 27 |
| #define I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_MASK (0x1 << I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_SHIFT) |
| #define I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_SHIFT 28 |
| #define I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_MASK (0x1 << I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_SHIFT) |
| #define I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_SHIFT 29 |
| #define I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_MASK (0x1 << I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_SHIFT) |
| #define I40E_GL_MNG_HWARB_CTRL 0x000B6130 |
| #define I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_SHIFT 0 |
| #define I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_MASK (0x1 << I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_SHIFT) |
| #define I40E_PRT_MNG_FTFT_DATA(_i) (0x000852A0 + ((_i) * 32)) /* _i=0...31 */ |
| #define I40E_PRT_MNG_FTFT_DATA_MAX_INDEX 31 |
| #define I40E_PRT_MNG_FTFT_DATA_DWORD_SHIFT 0 |
| #define I40E_PRT_MNG_FTFT_DATA_DWORD_MASK (0xFFFFFFFF << I40E_PRT_MNG_FTFT_DATA_DWORD_SHIFT) |
| #define I40E_PRT_MNG_FTFT_LENGTH 0x00085260 |
| #define I40E_PRT_MNG_FTFT_LENGTH_LENGTH_SHIFT 0 |
| #define I40E_PRT_MNG_FTFT_LENGTH_LENGTH_MASK (0xFF << I40E_PRT_MNG_FTFT_LENGTH_LENGTH_SHIFT) |
| #define I40E_PRT_MNG_FTFT_MASK(_i) (0x00085160 + ((_i) * 32)) /* _i=0...7 */ |
| #define I40E_PRT_MNG_FTFT_MASK_MAX_INDEX 7 |
| #define I40E_PRT_MNG_FTFT_MASK_MASK_SHIFT 0 |
| #define I40E_PRT_MNG_FTFT_MASK_MASK_MASK (0xFFFF << I40E_PRT_MNG_FTFT_MASK_MASK_SHIFT) |
| #define I40E_PRT_MNG_MANC 0x00256A20 |
| #define I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_SHIFT 0 |
| #define I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_MASK (0x1 << I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_SHIFT) |
| #define I40E_PRT_MNG_MANC_NCSI_DISCARD_SHIFT 1 |
| #define I40E_PRT_MNG_MANC_NCSI_DISCARD_MASK (0x1 << I40E_PRT_MNG_MANC_NCSI_DISCARD_SHIFT) |
| #define I40E_PRT_MNG_MANC_RCV_TCO_EN_SHIFT 17 |
| #define I40E_PRT_MNG_MANC_RCV_TCO_EN_MASK (0x1 << I40E_PRT_MNG_MANC_RCV_TCO_EN_SHIFT) |
| #define I40E_PRT_MNG_MANC_RCV_ALL_SHIFT 19 |
| #define I40E_PRT_MNG_MANC_RCV_ALL_MASK (0x1 << I40E_PRT_MNG_MANC_RCV_ALL_SHIFT) |
| #define I40E_PRT_MNG_MANC_FIXED_NET_TYPE_SHIFT 25 |
| #define I40E_PRT_MNG_MANC_FIXED_NET_TYPE_MASK (0x1 << I40E_PRT_MNG_MANC_FIXED_NET_TYPE_SHIFT) |
| #define I40E_PRT_MNG_MANC_NET_TYPE_SHIFT 26 |
| #define I40E_PRT_MNG_MANC_NET_TYPE_MASK (0x1 << I40E_PRT_MNG_MANC_NET_TYPE_SHIFT) |
| #define I40E_PRT_MNG_MANC_EN_BMC2OS_SHIFT 28 |
| #define I40E_PRT_MNG_MANC_EN_BMC2OS_MASK (0x1 << I40E_PRT_MNG_MANC_EN_BMC2OS_SHIFT) |
| #define I40E_PRT_MNG_MANC_EN_BMC2NET_SHIFT 29 |
| #define I40E_PRT_MNG_MANC_EN_BMC2NET_MASK (0x1 << I40E_PRT_MNG_MANC_EN_BMC2NET_SHIFT) |
| #define I40E_PRT_MNG_MAVTV(_i) (0x00255900 + ((_i) * 32)) /* _i=0...7 */ |
| #define I40E_PRT_MNG_MAVTV_MAX_INDEX 7 |
| #define I40E_PRT_MNG_MAVTV_VID_SHIFT 0 |
| #define I40E_PRT_MNG_MAVTV_VID_MASK (0xFFF << I40E_PRT_MNG_MAVTV_VID_SHIFT) |
| #define I40E_PRT_MNG_MDEF(_i) (0x00255D00 + ((_i) * 32)) |
| #define I40E_PRT_MNG_MDEF_MAX_INDEX 7 |
| #define I40E_PRT_MNG_MDEF_MAC_EXACT_AND_SHIFT 0 |
| #define I40E_PRT_MNG_MDEF_MAC_EXACT_AND_MASK (0xF << I40E_PRT_MNG_MDEF_MAC_EXACT_AND_SHIFT) |
| #define I40E_PRT_MNG_MDEF_BROADCAST_AND_SHIFT 4 |
| #define I40E_PRT_MNG_MDEF_BROADCAST_AND_MASK (0x1 << I40E_PRT_MNG_MDEF_BROADCAST_AND_SHIFT) |
| #define I40E_PRT_MNG_MDEF_VLAN_AND_SHIFT 5 |
| #define I40E_PRT_MNG_MDEF_VLAN_AND_MASK (0xFF << I40E_PRT_MNG_MDEF_VLAN_AND_SHIFT) |
| #define I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_SHIFT 13 |
| #define I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_MASK (0xF << I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_SHIFT) |
| #define I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_SHIFT 17 |
| #define I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_MASK (0xF << I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_SHIFT) |
| #define I40E_PRT_MNG_MDEF_MAC_EXACT_OR_SHIFT 21 |
| #define I40E_PRT_MNG_MDEF_MAC_EXACT_OR_MASK (0xF << I40E_PRT_MNG_MDEF_MAC_EXACT_OR_SHIFT) |
| #define I40E_PRT_MNG_MDEF_BROADCAST_OR_SHIFT 25 |
| #define I40E_PRT_MNG_MDEF_BROADCAST_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_BROADCAST_OR_SHIFT) |
| #define I40E_PRT_MNG_MDEF_MULTICAST_AND_SHIFT 26 |
| #define I40E_PRT_MNG_MDEF_MULTICAST_AND_MASK (0x1 << I40E_PRT_MNG_MDEF_MULTICAST_AND_SHIFT) |
| #define I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_SHIFT 27 |
| #define I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_SHIFT) |
| #define I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_SHIFT 28 |
| #define I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_SHIFT) |
| #define I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_SHIFT 29 |
| #define I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_SHIFT) |
| #define I40E_PRT_MNG_MDEF_PORT_0X298_OR_SHIFT 30 |
| #define I40E_PRT_MNG_MDEF_PORT_0X298_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_PORT_0X298_OR_SHIFT) |
| #define I40E_PRT_MNG_MDEF_PORT_0X26F_OR_SHIFT 31 |
| #define I40E_PRT_MNG_MDEF_PORT_0X26F_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_PORT_0X26F_OR_SHIFT) |
| #define I40E_PRT_MNG_MDEF_EXT(_i) (0x00255F00 + ((_i) * 32)) |
| #define I40E_PRT_MNG_MDEF_EXT_MAX_INDEX 7 |
| #define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_SHIFT 0 |
| #define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_MASK (0xF << I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_SHIFT) |
| #define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_SHIFT 4 |
| #define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_MASK (0xF << I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_SHIFT) |
| #define I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_SHIFT 8 |
| #define I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_MASK (0xFFFF << I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_SHIFT) |
| #define I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_SHIFT 24 |
| #define I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_SHIFT) |
| #define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_SHIFT 25 |
| #define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_SHIFT) |
| #define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_SHIFT 26 |
| #define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_SHIFT) |
| #define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_SHIFT 27 |
| #define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_SHIFT) |
| #define I40E_PRT_MNG_MDEF_EXT_ICMP_OR_SHIFT 28 |
| #define I40E_PRT_MNG_MDEF_EXT_ICMP_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_ICMP_OR_SHIFT) |
| #define I40E_PRT_MNG_MDEF_EXT_MLD_SHIFT 29 |
| #define I40E_PRT_MNG_MDEF_EXT_MLD_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_MLD_SHIFT) |
| #define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_SHIFT 30 |
| #define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_SHIFT) |
| #define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_SHIFT 31 |
| #define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_SHIFT) |
| #define I40E_PRT_MNG_MDEFVSI(_i) (0x00256580 + ((_i) * 32)) /* _i=0...3 */ |
| #define I40E_PRT_MNG_MDEFVSI_MAX_INDEX 3 |
| #define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT 0 |
| #define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_MASK (0xFFFF << I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT) |
| #define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT 16 |
| #define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_MASK (0xFFFF << I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT) |
| #define I40E_PRT_MNG_METF(_i) (0x00256780 + ((_i) * 32)) /* _i=0...3 */ |
| #define I40E_PRT_MNG_METF_MAX_INDEX 3 |
| #define I40E_PRT_MNG_METF_ETYPE_SHIFT 0 |
| #define I40E_PRT_MNG_METF_ETYPE_MASK (0xFFFF << I40E_PRT_MNG_METF_ETYPE_SHIFT) |
| #define I40E_PRT_MNG_METF_POLARITY_SHIFT 30 |
| #define I40E_PRT_MNG_METF_POLARITY_MASK (0x1 << I40E_PRT_MNG_METF_POLARITY_SHIFT) |
| #define I40E_PRT_MNG_MFUTP(_i) (0x00254E00 + ((_i) * 32)) /* _i=0...15 */ |
| #define I40E_PRT_MNG_MFUTP_MAX_INDEX 15 |
| #define I40E_PRT_MNG_MFUTP_MFUTP_N_SHIFT 0 |
| #define I40E_PRT_MNG_MFUTP_MFUTP_N_MASK (0xFFFF << I40E_PRT_MNG_MFUTP_MFUTP_N_SHIFT) |
| #define I40E_PRT_MNG_MFUTP_UDP_SHIFT 16 |
| #define I40E_PRT_MNG_MFUTP_UDP_MASK (0x1 << I40E_PRT_MNG_MFUTP_UDP_SHIFT) |
| #define I40E_PRT_MNG_MFUTP_TCP_SHIFT 17 |
| #define I40E_PRT_MNG_MFUTP_TCP_MASK (0x1 << I40E_PRT_MNG_MFUTP_TCP_SHIFT) |
| #define I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_SHIFT 18 |
| #define I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_MASK (0x1 << I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_SHIFT) |
| #define I40E_PRT_MNG_MIPAF4(_i) (0x00256280 + ((_i) * 32)) /* _i=0...3 */ |
| #define I40E_PRT_MNG_MIPAF4_MAX_INDEX 3 |
| #define I40E_PRT_MNG_MIPAF4_MIPAF_SHIFT 0 |
| #define I40E_PRT_MNG_MIPAF4_MIPAF_MASK (0xFFFFFFFF << I40E_PRT_MNG_MIPAF4_MIPAF_SHIFT) |
| #define I40E_PRT_MNG_MIPAF6(_i) (0x00254200 + ((_i) * 32)) /* _i=0...15 */ |
| #define I40E_PRT_MNG_MIPAF6_MAX_INDEX 15 |
| #define I40E_PRT_MNG_MIPAF6_MIPAF_SHIFT 0 |
| #define I40E_PRT_MNG_MIPAF6_MIPAF_MASK (0xFFFFFFFF << I40E_PRT_MNG_MIPAF6_MIPAF_SHIFT) |
| #define I40E_PRT_MNG_MMAH(_i) (0x00256380 + ((_i) * 32)) /* _i=0...3 */ |
| #define I40E_PRT_MNG_MMAH_MAX_INDEX 3 |
| #define I40E_PRT_MNG_MMAH_MMAH_SHIFT 0 |
| #define I40E_PRT_MNG_MMAH_MMAH_MASK (0xFFFF << I40E_PRT_MNG_MMAH_MMAH_SHIFT) |
| #define I40E_PRT_MNG_MMAL(_i) (0x00256480 + ((_i) * 32)) /* _i=0...3 */ |
| #define I40E_PRT_MNG_MMAL_MAX_INDEX 3 |
| #define I40E_PRT_MNG_MMAL_MMAL_SHIFT 0 |
| #define I40E_PRT_MNG_MMAL_MMAL_MASK (0xFFFFFFFF << I40E_PRT_MNG_MMAL_MMAL_SHIFT) |
| #define I40E_PRT_MNG_MNGONLY 0x00256A60 |
| #define I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_SHIFT 0 |
| #define I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_MASK (0xFF << I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_SHIFT) |
| #define I40E_PRT_MNG_MSFM 0x00256AA0 |
| #define I40E_PRT_MNG_MSFM_PORT_26F_UDP_SHIFT 0 |
| #define I40E_PRT_MNG_MSFM_PORT_26F_UDP_MASK (0x1 << I40E_PRT_MNG_MSFM_PORT_26F_UDP_SHIFT) |
| #define I40E_PRT_MNG_MSFM_PORT_26F_TCP_SHIFT 1 |
| #define I40E_PRT_MNG_MSFM_PORT_26F_TCP_MASK (0x1 << I40E_PRT_MNG_MSFM_PORT_26F_TCP_SHIFT) |
| #define I40E_PRT_MNG_MSFM_PORT_298_UDP_SHIFT 2 |
| #define I40E_PRT_MNG_MSFM_PORT_298_UDP_MASK (0x1 << I40E_PRT_MNG_MSFM_PORT_298_UDP_SHIFT) |
| #define I40E_PRT_MNG_MSFM_PORT_298_TCP_SHIFT 3 |
| #define I40E_PRT_MNG_MSFM_PORT_298_TCP_MASK (0x1 << I40E_PRT_MNG_MSFM_PORT_298_TCP_SHIFT) |
| #define I40E_PRT_MNG_MSFM_IPV6_0_MASK_SHIFT 4 |
| #define I40E_PRT_MNG_MSFM_IPV6_0_MASK_MASK (0x1 << I40E_PRT_MNG_MSFM_IPV6_0_MASK_SHIFT) |
| #define I40E_PRT_MNG_MSFM_IPV6_1_MASK_SHIFT 5 |
| #define I40E_PRT_MNG_MSFM_IPV6_1_MASK_MASK (0x1 << I40E_PRT_MNG_MSFM_IPV6_1_MASK_SHIFT) |
| #define I40E_PRT_MNG_MSFM_IPV6_2_MASK_SHIFT 6 |
| #define I40E_PRT_MNG_MSFM_IPV6_2_MASK_MASK (0x1 << I40E_PRT_MNG_MSFM_IPV6_2_MASK_SHIFT) |
| #define I40E_PRT_MNG_MSFM_IPV6_3_MASK_SHIFT 7 |
| #define I40E_PRT_MNG_MSFM_IPV6_3_MASK_MASK (0x1 << I40E_PRT_MNG_MSFM_IPV6_3_MASK_SHIFT) |
| #define I40E_MSIX_PBA(_i) (0x00004900 + ((_i) * 4)) /* _i=0...5 */ |
| #define I40E_MSIX_PBA_MAX_INDEX 5 |
| #define I40E_MSIX_PBA_PENBIT_SHIFT 0 |
| #define I40E_MSIX_PBA_PENBIT_MASK (0xFFFFFFFF << I40E_MSIX_PBA_PENBIT_SHIFT) |
| #define I40E_MSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...128 */ |
| #define I40E_MSIX_TADD_MAX_INDEX 128 |
| #define I40E_MSIX_TADD_MSIXTADD10_SHIFT 0 |
| #define I40E_MSIX_TADD_MSIXTADD10_MASK (0x3 << I40E_MSIX_TADD_MSIXTADD10_SHIFT) |
| #define I40E_MSIX_TADD_MSIXTADD_SHIFT 2 |
| #define I40E_MSIX_TADD_MSIXTADD_MASK (0x3FFFFFFF << I40E_MSIX_TADD_MSIXTADD_SHIFT) |
| #define I40E_MSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...128 */ |
| #define I40E_MSIX_TMSG_MAX_INDEX 128 |
| #define I40E_MSIX_TMSG_MSIXTMSG_SHIFT 0 |
| #define I40E_MSIX_TMSG_MSIXTMSG_MASK (0xFFFFFFFF << I40E_MSIX_TMSG_MSIXTMSG_SHIFT) |
| #define I40E_MSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...128 */ |
| #define I40E_MSIX_TUADD_MAX_INDEX 128 |
| #define I40E_MSIX_TUADD_MSIXTUADD_SHIFT 0 |
| #define I40E_MSIX_TUADD_MSIXTUADD_MASK (0xFFFFFFFF << I40E_MSIX_TUADD_MSIXTUADD_SHIFT) |
| #define I40E_MSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...128 */ |
| #define I40E_MSIX_TVCTRL_MAX_INDEX 128 |
| #define I40E_MSIX_TVCTRL_MASK_SHIFT 0 |
| #define I40E_MSIX_TVCTRL_MASK_MASK (0x1 << I40E_MSIX_TVCTRL_MASK_SHIFT) |
| #define I40E_VFMSIX_PBA1(_i) (0x00004944 + ((_i) * 4)) /* _i=0...19 */ |
| #define I40E_VFMSIX_PBA1_MAX_INDEX 19 |
| #define I40E_VFMSIX_PBA1_PENBIT_SHIFT 0 |
| #define I40E_VFMSIX_PBA1_PENBIT_MASK (0xFFFFFFFF << I40E_VFMSIX_PBA1_PENBIT_SHIFT) |
| #define I40E_VFMSIX_TADD1(_i) (0x00002100 + ((_i) * 16)) /* _i=0...639 */ |
| #define I40E_VFMSIX_TADD1_MAX_INDEX 639 |
| #define I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT 0 |
| #define I40E_VFMSIX_TADD1_MSIXTADD10_MASK (0x3 << I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT) |
| #define I40E_VFMSIX_TADD1_MSIXTADD_SHIFT 2 |
| #define I40E_VFMSIX_TADD1_MSIXTADD_MASK (0x3FFFFFFF << I40E_VFMSIX_TADD1_MSIXTADD_SHIFT) |
| #define I40E_VFMSIX_TMSG1(_i) (0x00002108 + ((_i) * 16)) /* _i=0...639 */ |
| #define I40E_VFMSIX_TMSG1_MAX_INDEX 639 |
| #define I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT 0 |
| #define I40E_VFMSIX_TMSG1_MSIXTMSG_MASK (0xFFFFFFFF << I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT) |
| #define I40E_VFMSIX_TUADD1(_i) (0x00002104 + ((_i) * 16)) /* _i=0...639 */ |
| #define I40E_VFMSIX_TUADD1_MAX_INDEX 639 |
| #define I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT 0 |
| #define I40E_VFMSIX_TUADD1_MSIXTUADD_MASK (0xFFFFFFFF << I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT) |
| #define I40E_VFMSIX_TVCTRL1(_i) (0x0000210C + ((_i) * 16)) /* _i=0...639 */ |
| #define I40E_VFMSIX_TVCTRL1_MAX_INDEX 639 |
| #define I40E_VFMSIX_TVCTRL1_MASK_SHIFT 0 |
| #define I40E_VFMSIX_TVCTRL1_MASK_MASK (0x1 << I40E_VFMSIX_TVCTRL1_MASK_SHIFT) |
| #define I40E_GLNVM_FLA 0x000B6108 |
| #define I40E_GLNVM_FLA_FL_SCK_SHIFT 0 |
| #define I40E_GLNVM_FLA_FL_SCK_MASK (0x1 << I40E_GLNVM_FLA_FL_SCK_SHIFT) |
| #define I40E_GLNVM_FLA_FL_CE_SHIFT 1 |
| #define I40E_GLNVM_FLA_FL_CE_MASK (0x1 << I40E_GLNVM_FLA_FL_CE_SHIFT) |
| #define I40E_GLNVM_FLA_FL_SI_SHIFT 2 |
| #define I40E_GLNVM_FLA_FL_SI_MASK (0x1 << I40E_GLNVM_FLA_FL_SI_SHIFT) |
| #define I40E_GLNVM_FLA_FL_SO_SHIFT 3 |
| #define I40E_GLNVM_FLA_FL_SO_MASK (0x1 << I40E_GLNVM_FLA_FL_SO_SHIFT) |
| #define I40E_GLNVM_FLA_FL_REQ_SHIFT 4 |
| #define I40E_GLNVM_FLA_FL_REQ_MASK (0x1 << I40E_GLNVM_FLA_FL_REQ_SHIFT) |
| #define I40E_GLNVM_FLA_FL_GNT_SHIFT 5 |
| #define I40E_GLNVM_FLA_FL_GNT_MASK (0x1 << I40E_GLNVM_FLA_FL_GNT_SHIFT) |
| #define I40E_GLNVM_FLA_LOCKED_SHIFT 6 |
| #define I40E_GLNVM_FLA_LOCKED_MASK (0x1 << I40E_GLNVM_FLA_LOCKED_SHIFT) |
| #define I40E_GLNVM_FLA_FL_SADDR_SHIFT 18 |
| #define I40E_GLNVM_FLA_FL_SADDR_MASK (0x7FF << I40E_GLNVM_FLA_FL_SADDR_SHIFT) |
| #define I40E_GLNVM_FLA_FL_BUSY_SHIFT 30 |
| #define I40E_GLNVM_FLA_FL_BUSY_MASK (0x1 << I40E_GLNVM_FLA_FL_BUSY_SHIFT) |
| #define I40E_GLNVM_FLA_FL_DER_SHIFT 31 |
| #define I40E_GLNVM_FLA_FL_DER_MASK (0x1 << I40E_GLNVM_FLA_FL_DER_SHIFT) |
| #define I40E_GLNVM_FLASHID 0x000B6104 |
| #define I40E_GLNVM_FLASHID_FLASHID_SHIFT 0 |
| #define I40E_GLNVM_FLASHID_FLASHID_MASK (0xFFFFFF << I40E_GLNVM_FLASHID_FLASHID_SHIFT) |
| #define I40E_GLNVM_GENS 0x000B6100 |
| #define I40E_GLNVM_GENS_NVM_PRES_SHIFT 0 |
| #define I40E_GLNVM_GENS_NVM_PRES_MASK (0x1 << I40E_GLNVM_GENS_NVM_PRES_SHIFT) |
| #define I40E_GLNVM_GENS_SR_SIZE_SHIFT 5 |
| #define I40E_GLNVM_GENS_SR_SIZE_MASK (0x7 << I40E_GLNVM_GENS_SR_SIZE_SHIFT) |
| #define I40E_GLNVM_GENS_BANK1VAL_SHIFT 8 |
| #define I40E_GLNVM_GENS_BANK1VAL_MASK (0x1 << I40E_GLNVM_GENS_BANK1VAL_SHIFT) |
| #define I40E_GLNVM_GENS_ALT_PRST_SHIFT 23 |
| #define I40E_GLNVM_GENS_ALT_PRST_MASK (0x1 << I40E_GLNVM_GENS_ALT_PRST_SHIFT) |
| #define I40E_GLNVM_GENS_FL_AUTO_RD_SHIFT 25 |
| #define I40E_GLNVM_GENS_FL_AUTO_RD_MASK (0x1 << I40E_GLNVM_GENS_FL_AUTO_RD_SHIFT) |
| #define I40E_GLNVM_PROTCSR(_i) (0x000B6010 + ((_i) * 4)) /* _i=0...59 */ |
| #define I40E_GLNVM_PROTCSR_MAX_INDEX 59 |
| #define I40E_GLNVM_PROTCSR_ADDR_BLOCK_SHIFT 0 |
| #define I40E_GLNVM_PROTCSR_ADDR_BLOCK_MASK (0xFFFFFF << I40E_GLNVM_PROTCSR_ADDR_BLOCK_SHIFT) |
| #define I40E_GLNVM_SRCTL 0x000B6110 |
| #define I40E_GLNVM_SRCTL_SRBUSY_SHIFT 0 |
| #define I40E_GLNVM_SRCTL_SRBUSY_MASK (0x1 << I40E_GLNVM_SRCTL_SRBUSY_SHIFT) |
| #define I40E_GLNVM_SRCTL_ADDR_SHIFT 14 |
| #define I40E_GLNVM_SRCTL_ADDR_MASK (0x7FFF << I40E_GLNVM_SRCTL_ADDR_SHIFT) |
| #define I40E_GLNVM_SRCTL_WRITE_SHIFT 29 |
| #define I40E_GLNVM_SRCTL_WRITE_MASK (0x1 << I40E_GLNVM_SRCTL_WRITE_SHIFT) |
| #define I40E_GLNVM_SRCTL_START_SHIFT 30 |
| #define I40E_GLNVM_SRCTL_START_MASK (0x1 << I40E_GLNVM_SRCTL_START_SHIFT) |
| #define I40E_GLNVM_SRCTL_DONE_SHIFT 31 |
| #define I40E_GLNVM_SRCTL_DONE_MASK (0x1 << I40E_GLNVM_SRCTL_DONE_SHIFT) |
| #define I40E_GLNVM_SRDATA 0x000B6114 |
| #define I40E_GLNVM_SRDATA_WRDATA_SHIFT 0 |
| #define I40E_GLNVM_SRDATA_WRDATA_MASK (0xFFFF << I40E_GLNVM_SRDATA_WRDATA_SHIFT) |
| #define I40E_GLNVM_SRDATA_RDDATA_SHIFT 16 |
| #define I40E_GLNVM_SRDATA_RDDATA_MASK (0xFFFF << I40E_GLNVM_SRDATA_RDDATA_SHIFT) |
| #define I40E_GLNVM_ULD 0x000B6008 |
| #define I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT 0 |
| #define I40E_GLNVM_ULD_CONF_PCIR_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT) |
| #define I40E_GLNVM_ULD_CONF_PCIRTL_DONE_SHIFT 1 |
| #define I40E_GLNVM_ULD_CONF_PCIRTL_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_PCIRTL_DONE_SHIFT) |
| #define I40E_GLNVM_ULD_CONF_LCB_DONE_SHIFT 2 |
| #define I40E_GLNVM_ULD_CONF_LCB_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_LCB_DONE_SHIFT) |
| #define I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT 3 |
| #define I40E_GLNVM_ULD_CONF_CORE_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT) |
| #define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT 4 |
| #define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT) |
| #define I40E_GLNVM_ULD_CONF_POR_DONE_SHIFT 5 |
| #define I40E_GLNVM_ULD_CONF_POR_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_POR_DONE_SHIFT) |
| #define I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_SHIFT 6 |
| #define I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_SHIFT) |
| #define I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_SHIFT 7 |
| #define I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_SHIFT) |
| #define I40E_GLNVM_ULD_CONF_EMP_DONE_SHIFT 8 |
| #define I40E_GLNVM_ULD_CONF_EMP_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_EMP_DONE_SHIFT) |
| #define I40E_GLNVM_ULD_CONF_PCIALT_DONE_SHIFT 9 |
| #define I40E_GLNVM_ULD_CONF_PCIALT_DONE_MASK (0x1 << I40E_GLNVM_ULD_CONF_PCIALT_DONE_SHIFT) |
| |
| #define I40E_GLPCI_BYTCTH 0x0009C484 |
| #define I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_SHIFT 0 |
| #define I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_MASK (0xFFFFFFFF << I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_SHIFT) |
| #define I40E_GLPCI_BYTCTL 0x0009C488 |
| #define I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_SHIFT 0 |
| #define I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_MASK (0xFFFFFFFF << I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_SHIFT) |
| #define I40E_GLPCI_CAPCTRL 0x000BE4A4 |
| #define I40E_GLPCI_CAPCTRL_VPD_EN_SHIFT 0 |
| #define I40E_GLPCI_CAPCTRL_VPD_EN_MASK (0x1 << I40E_GLPCI_CAPCTRL_VPD_EN_SHIFT) |
| #define I40E_GLPCI_CAPSUP 0x000BE4A8 |
| #define I40E_GLPCI_CAPSUP_PCIE_VER_SHIFT 0 |
| #define I40E_GLPCI_CAPSUP_PCIE_VER_MASK (0x1 << I40E_GLPCI_CAPSUP_PCIE_VER_SHIFT) |
| #define I40E_GLPCI_CAPSUP_LTR_EN_SHIFT 2 |
| #define I40E_GLPCI_CAPSUP_LTR_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_LTR_EN_SHIFT) |
| #define I40E_GLPCI_CAPSUP_TPH_EN_SHIFT 3 |
| #define I40E_GLPCI_CAPSUP_TPH_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_TPH_EN_SHIFT) |
| #define I40E_GLPCI_CAPSUP_ARI_EN_SHIFT 4 |
| #define I40E_GLPCI_CAPSUP_ARI_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_ARI_EN_SHIFT) |
| #define I40E_GLPCI_CAPSUP_IOV_EN_SHIFT 5 |
| #define I40E_GLPCI_CAPSUP_IOV_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_IOV_EN_SHIFT) |
| #define I40E_GLPCI_CAPSUP_ACS_EN_SHIFT 6 |
| #define I40E_GLPCI_CAPSUP_ACS_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_ACS_EN_SHIFT) |
| #define I40E_GLPCI_CAPSUP_SEC_EN_SHIFT 7 |
| #define I40E_GLPCI_CAPSUP_SEC_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_SEC_EN_SHIFT) |
| #define I40E_GLPCI_CAPSUP_ECRC_GEN_EN_SHIFT 16 |
| #define I40E_GLPCI_CAPSUP_ECRC_GEN_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_ECRC_GEN_EN_SHIFT) |
| #define I40E_GLPCI_CAPSUP_ECRC_CHK_EN_SHIFT 17 |
| #define I40E_GLPCI_CAPSUP_ECRC_CHK_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_ECRC_CHK_EN_SHIFT) |
| #define I40E_GLPCI_CAPSUP_IDO_EN_SHIFT 18 |
| #define I40E_GLPCI_CAPSUP_IDO_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_IDO_EN_SHIFT) |
| #define I40E_GLPCI_CAPSUP_MSI_MASK_SHIFT 19 |
| #define I40E_GLPCI_CAPSUP_MSI_MASK_MASK (0x1 << I40E_GLPCI_CAPSUP_MSI_MASK_SHIFT) |
| #define I40E_GLPCI_CAPSUP_CSR_CONF_EN_SHIFT 20 |
| #define I40E_GLPCI_CAPSUP_CSR_CONF_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_CSR_CONF_EN_SHIFT) |
| #define I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_SHIFT 30 |
| #define I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_MASK (0x1 << I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_SHIFT) |
| #define I40E_GLPCI_CAPSUP_LOAD_DEV_ID_SHIFT 31 |
| #define I40E_GLPCI_CAPSUP_LOAD_DEV_ID_MASK (0x1 << I40E_GLPCI_CAPSUP_LOAD_DEV_ID_SHIFT) |
| #define I40E_GLPCI_CNF 0x000BE4C0 |
| #define I40E_GLPCI_CNF_FLEX10_SHIFT 1 |
| #define I40E_GLPCI_CNF_FLEX10_MASK (0x1 << I40E_GLPCI_CNF_FLEX10_SHIFT) |
| #define I40E_GLPCI_CNF_WAKE_PIN_EN_SHIFT 2 |
| #define I40E_GLPCI_CNF_WAKE_PIN_EN_MASK (0x1 << I40E_GLPCI_CNF_WAKE_PIN_EN_SHIFT) |
| #define I40E_GLPCI_CNF2 0x000BE494 |
| #define I40E_GLPCI_CNF2_RO_DIS_SHIFT 0 |
| #define I40E_GLPCI_CNF2_RO_DIS_MASK (0x1 << I40E_GLPCI_CNF2_RO_DIS_SHIFT) |
| #define I40E_GLPCI_CNF2_CACHELINE_SIZE_SHIFT 1 |
| #define I40E_GLPCI_CNF2_CACHELINE_SIZE_MASK (0x1 << I40E_GLPCI_CNF2_CACHELINE_SIZE_SHIFT) |
| #define I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT 2 |
| #define I40E_GLPCI_CNF2_MSI_X_PF_N_MASK (0x7FF << I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT) |
| #define I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT 13 |
| #define I40E_GLPCI_CNF2_MSI_X_VF_N_MASK (0x7FF << I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT) |
| #define I40E_GLPCI_DREVID 0x0009C480 |
| #define I40E_GLPCI_DREVID_DEFAULT_REVID_SHIFT 0 |
| #define I40E_GLPCI_DREVID_DEFAULT_REVID_MASK (0xFF << I40E_GLPCI_DREVID_DEFAULT_REVID_SHIFT) |
| #define I40E_GLPCI_GSCL_1 0x0009C48C |
| #define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_SHIFT 0 |
| #define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_SHIFT) |
| #define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_SHIFT 1 |
| #define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_SHIFT) |
| #define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_SHIFT 2 |
| #define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_SHIFT) |
| #define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_SHIFT 3 |
| #define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_SHIFT) |
| #define I40E_GLPCI_GSCL_1_LBC_ENABLE_0_SHIFT 4 |
| #define I40E_GLPCI_GSCL_1_LBC_ENABLE_0_MASK (0x1 << I40E_GLPCI_GSCL_1_LBC_ENABLE_0_SHIFT) |
| #define I40E_GLPCI_GSCL_1_LBC_ENABLE_1_SHIFT 5 |
| #define I40E_GLPCI_GSCL_1_LBC_ENABLE_1_MASK (0x1 << I40E_GLPCI_GSCL_1_LBC_ENABLE_1_SHIFT) |
| #define I40E_GLPCI_GSCL_1_LBC_ENABLE_2_SHIFT 6 |
| #define I40E_GLPCI_GSCL_1_LBC_ENABLE_2_MASK (0x1 << I40E_GLPCI_GSCL_1_LBC_ENABLE_2_SHIFT) |
| #define I40E_GLPCI_GSCL_1_LBC_ENABLE_3_SHIFT 7 |
| #define I40E_GLPCI_GSCL_1_LBC_ENABLE_3_MASK (0x1 << I40E_GLPCI_GSCL_1_LBC_ENABLE_3_SHIFT) |
| #define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_SHIFT 8 |
| #define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_MASK (0x1 << I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_SHIFT) |
| #define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_SHIFT 9 |
| #define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_MASK (0x1F << I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_SHIFT) |
| #define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_SHIFT 14 |
| #define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_MASK (0x1 << I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_SHIFT) |
| #define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_SHIFT 15 |
| #define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_MASK (0x1F << I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_SHIFT) |
| #define I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_SHIFT 28 |
| #define I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_SHIFT) |
| #define I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_SHIFT 29 |
| #define I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_SHIFT) |
| #define I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_SHIFT 30 |
| #define I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_SHIFT) |
| #define I40E_GLPCI_GSCL_1_GIO_COUNT_START_SHIFT 31 |
| #define I40E_GLPCI_GSCL_1_GIO_COUNT_START_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_START_SHIFT) |
| #define I40E_GLPCI_GSCL_2 0x0009C490 |
| #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_SHIFT 0 |
| #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_MASK (0xFF << I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_SHIFT) |
| #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_SHIFT 8 |
| #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_MASK (0xFF << I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_SHIFT) |
| #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_SHIFT 16 |
| #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_MASK (0xFF << I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_SHIFT) |
| #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_SHIFT 24 |
| #define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_MASK (0xFF << I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_SHIFT) |
| #define I40E_GLPCI_GSCL_5_8(_i) (0x0009C494 + ((_i) * 4)) /* _i=0...3 */ |
| #define I40E_GLPCI_GSCL_5_8_MAX_INDEX 3 |
| #define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT 0 |
| #define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_MASK (0xFFFF << I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT) |
| #define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT 16 |
| #define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_MASK (0xFFFF << I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT) |
| #define I40E_GLPCI_GSCN_0_3(_i) (0x0009C4A4 + ((_i) * 4)) /* _i=0...3 */ |
| #define I40E_GLPCI_GSCN_0_3_MAX_INDEX 3 |
| #define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT 0 |
| #define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_MASK (0xFFFFFFFF << I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT) |
| #define I40E_GLPCI_LATCT 0x0009C4B4 |
| #define I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_SHIFT 0 |
| #define I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_MASK (0xFFFFFFFF << I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_SHIFT) |
| #define I40E_GLPCI_LBARCTRL 0x000BE484 |
| #define I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT 0 |
| #define I40E_GLPCI_LBARCTRL_PREFBAR_MASK (0x1 << I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT) |
| #define I40E_GLPCI_LBARCTRL_BAR32_SHIFT 1 |
| #define I40E_GLPCI_LBARCTRL_BAR32_MASK (0x1 << I40E_GLPCI_LBARCTRL_BAR32_SHIFT) |
| #define I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT 3 |
| #define I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_MASK (0x1 << I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT) |
| #define I40E_GLPCI_LBARCTRL_PE_DB_SIZE_SHIFT 4 |
| #define I40E_GLPCI_LBARCTRL_PE_DB_SIZE_MASK (0x3 << I40E_GLPCI_LBARCTRL_PE_DB_SIZE_SHIFT) |
| #define I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT 6 |
| #define I40E_GLPCI_LBARCTRL_FL_SIZE_MASK (0x7 << I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT) |
| #define I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_SHIFT 10 |
| #define I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_MASK (0x1 << I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_SHIFT) |
| #define I40E_GLPCI_LBARCTRL_EXROM_SIZE_SHIFT 11 |
| #define I40E_GLPCI_LBARCTRL_EXROM_SIZE_MASK (0x7 << I40E_GLPCI_LBARCTRL_EXROM_SIZE_SHIFT) |
| #define I40E_GLPCI_LINKCAP 0x000BE4AC |
| #define I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_SHIFT 0 |
| #define I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_MASK (0x3F << I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_SHIFT) |
| #define I40E_GLPCI_LINKCAP_MAX_PAYLOAD_SHIFT 6 |
| #define I40E_GLPCI_LINKCAP_MAX_PAYLOAD_MASK (0x7 << I40E_GLPCI_LINKCAP_MAX_PAYLOAD_SHIFT) |
| #define I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_SHIFT 9 |
| #define I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_MASK (0xF << I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_SHIFT) |
| #define I40E_GLPCI_PCIERR 0x000BE4FC |
| #define I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT 0 |
| #define I40E_GLPCI_PCIERR_PCIE_ERR_REP_MASK (0xFFFFFFFF << I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT) |
| #define I40E_GLPCI_PCITEST2 0x000BE4BC |
| #define I40E_GLPCI_PCITEST2_IOV_TEST_MODE_SHIFT 0 |
| #define I40E_GLPCI_PCITEST2_IOV_TEST_MODE_MASK (0x1 << I40E_GLPCI_PCITEST2_IOV_TEST_MODE_SHIFT) |
| #define I40E_GLPCI_PCITEST2_TAG_ALLOC_SHIFT 1 |
| #define I40E_GLPCI_PCITEST2_TAG_ALLOC_MASK (0x1 << I40E_GLPCI_PCITEST2_TAG_ALLOC_SHIFT) |
| |
| #define I40E_GLPCI_PKTCT 0x0009C4BC |
| #define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT 0 |
| #define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_MASK (0xFFFFFFFF << I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT) |
| #define I40E_GLPCI_PMSUP 0x000BE4B0 |
| #define I40E_GLPCI_PMSUP_ASPM_SUP_SHIFT 0 |
| #define I40E_GLPCI_PMSUP_ASPM_SUP_MASK (0x3 << I40E_GLPCI_PMSUP_ASPM_SUP_SHIFT) |
| #define I40E_GLPCI_PMSUP_L0S_EXIT_LAT_SHIFT 2 |
| #define I40E_GLPCI_PMSUP_L0S_EXIT_LAT_MASK (0x7 << I40E_GLPCI_PMSUP_L0S_EXIT_LAT_SHIFT) |
| #define I40E_GLPCI_PMSUP_L1_EXIT_LAT_SHIFT 5 |
| #define I40E_GLPCI_PMSUP_L1_EXIT_LAT_MASK (0x7 << I40E_GLPCI_PMSUP_L1_EXIT_LAT_SHIFT) |
| #define I40E_GLPCI_PMSUP_L0S_ACC_LAT_SHIFT 8 |
| #define I40E_GLPCI_PMSUP_L0S_ACC_LAT_MASK (0x7 << I40E_GLPCI_PMSUP_L0S_ACC_LAT_SHIFT) |
| #define I40E_GLPCI_PMSUP_L1_ACC_LAT_SHIFT 11 |
| #define I40E_GLPCI_PMSUP_L1_ACC_LAT_MASK (0x7 << I40E_GLPCI_PMSUP_L1_ACC_LAT_SHIFT) |
| #define I40E_GLPCI_PMSUP_SLOT_CLK_SHIFT 14 |
| #define I40E_GLPCI_PMSUP_SLOT_CLK_MASK (0x1 << I40E_GLPCI_PMSUP_SLOT_CLK_SHIFT) |
| #define I40E_GLPCI_PMSUP_OBFF_SUP_SHIFT 15 |
| #define I40E_GLPCI_PMSUP_OBFF_SUP_MASK (0x3 << I40E_GLPCI_PMSUP_OBFF_SUP_SHIFT) |
| #define I40E_GLPCI_PWRDATA 0x000BE490 |
| #define I40E_GLPCI_PWRDATA_D0_POWER_SHIFT 0 |
| #define I40E_GLPCI_PWRDATA_D0_POWER_MASK (0xFF << I40E_GLPCI_PWRDATA_D0_POWER_SHIFT) |
| #define I40E_GLPCI_PWRDATA_COMM_POWER_SHIFT 8 |
| #define I40E_GLPCI_PWRDATA_COMM_POWER_MASK (0xFF << I40E_GLPCI_PWRDATA_COMM_POWER_SHIFT) |
| #define I40E_GLPCI_PWRDATA_D3_POWER_SHIFT 16 |
| #define I40E_GLPCI_PWRDATA_D3_POWER_MASK (0xFF << I40E_GLPCI_PWRDATA_D3_POWER_SHIFT) |
| #define I40E_GLPCI_PWRDATA_DATA_SCALE_SHIFT 24 |
| #define I40E_GLPCI_PWRDATA_DATA_SCALE_MASK (0x3 << I40E_GLPCI_PWRDATA_DATA_SCALE_SHIFT) |
| #define I40E_GLPCI_REVID 0x000BE4B4 |
| #define I40E_GLPCI_REVID_NVM_REVID_SHIFT 0 |
| #define I40E_GLPCI_REVID_NVM_REVID_MASK (0xFF << I40E_GLPCI_REVID_NVM_REVID_SHIFT) |
| #define I40E_GLPCI_SERH 0x000BE49C |
| #define I40E_GLPCI_SERH_SER_NUM_H_SHIFT 0 |
| #define I40E_GLPCI_SERH_SER_NUM_H_MASK (0xFFFF << I40E_GLPCI_SERH_SER_NUM_H_SHIFT) |
| #define I40E_GLPCI_SERL 0x000BE498 |
| #define I40E_GLPCI_SERL_SER_NUM_L_SHIFT 0 |
| #define I40E_GLPCI_SERL_SER_NUM_L_MASK (0xFFFFFFFF << I40E_GLPCI_SERL_SER_NUM_L_SHIFT) |
| #define I40E_GLPCI_SUBSYSID 0x000BE48C |
| #define I40E_GLPCI_SUBSYSID_SUB_VEN_ID_SHIFT 0 |
| #define I40E_GLPCI_SUBSYSID_SUB_VEN_ID_MASK (0xFFFF << I40E_GLPCI_SUBSYSID_SUB_VEN_ID_SHIFT) |
| #define I40E_GLPCI_SUBSYSID_SUB_ID_SHIFT 16 |
| #define I40E_GLPCI_SUBSYSID_SUB_ID_MASK (0xFFFF << I40E_GLPCI_SUBSYSID_SUB_ID_SHIFT) |
| #define I40E_GLPCI_UPADD 0x000BE4F8 |
| #define I40E_GLPCI_UPADD_ADDRESS_SHIFT 1 |
| #define I40E_GLPCI_UPADD_ADDRESS_MASK (0x7FFFFFFF << I40E_GLPCI_UPADD_ADDRESS_SHIFT) |
| #define I40E_GLPCI_VFSUP 0x000BE4B8 |
| #define I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT 0 |
| #define I40E_GLPCI_VFSUP_VF_PREFETCH_MASK (0x1 << I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT) |
| #define I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT 1 |
| #define I40E_GLPCI_VFSUP_VR_BAR_TYPE_MASK (0x1 << I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT) |
| #define I40E_PF_FUNC_RID 0x0009C000 |
| #define I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT 0 |
| #define I40E_PF_FUNC_RID_FUNCTION_NUMBER_MASK (0x7 << I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT) |
| #define I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT 3 |
| #define I40E_PF_FUNC_RID_DEVICE_NUMBER_MASK (0x1F << I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT) |
| #define I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT 8 |
| #define I40E_PF_FUNC_RID_BUS_NUMBER_MASK (0xFF << I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT) |
| #define I40E_PF_PCI_CIAA 0x0009C080 |
| #define I40E_PF_PCI_CIAA_ADDRESS_SHIFT 0 |
| #define I40E_PF_PCI_CIAA_ADDRESS_MASK (0xFFF << I40E_PF_PCI_CIAA_ADDRESS_SHIFT) |
| #define I40E_PF_PCI_CIAA_VF_NUM_SHIFT 12 |
| #define I40E_PF_PCI_CIAA_VF_NUM_MASK (0x7F << I40E_PF_PCI_CIAA_VF_NUM_SHIFT) |
| #define I40E_PF_PCI_CIAD 0x0009C100 |
| #define I40E_PF_PCI_CIAD_DATA_SHIFT 0 |
| #define I40E_PF_PCI_CIAD_DATA_MASK (0xFFFFFFFF << I40E_PF_PCI_CIAD_DATA_SHIFT) |
| #define I40E_PFPCI_CLASS 0x000BE400 |
| #define I40E_PFPCI_CLASS_STORAGE_CLASS_SHIFT 0 |
| #define I40E_PFPCI_CLASS_STORAGE_CLASS_MASK (0x1 << I40E_PFPCI_CLASS_STORAGE_CLASS_SHIFT) |
| #define I40E_PFPCI_CNF 0x000BE000 |
| #define I40E_PFPCI_CNF_MSI_EN_SHIFT 2 |
| #define I40E_PFPCI_CNF_MSI_EN_MASK (0x1 << I40E_PFPCI_CNF_MSI_EN_SHIFT) |
| #define I40E_PFPCI_CNF_EXROM_DIS_SHIFT 3 |
| #define I40E_PFPCI_CNF_EXROM_DIS_MASK (0x1 << I40E_PFPCI_CNF_EXROM_DIS_SHIFT) |
| #define I40E_PFPCI_CNF_IO_BAR_SHIFT 4 |
| #define I40E_PFPCI_CNF_IO_BAR_MASK (0x1 << I40E_PFPCI_CNF_IO_BAR_SHIFT) |
| #define I40E_PFPCI_CNF_INT_PIN_SHIFT 5 |
| #define I40E_PFPCI_CNF_INT_PIN_MASK (0x3 << I40E_PFPCI_CNF_INT_PIN_SHIFT) |
| #define I40E_PFPCI_FACTPS 0x0009C180 |
| #define I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT 0 |
| #define I40E_PFPCI_FACTPS_FUNC_POWER_STATE_MASK (0x3 << I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT) |
| #define I40E_PFPCI_FACTPS_FUNC_AUX_EN_SHIFT 3 |
| #define I40E_PFPCI_FACTPS_FUNC_AUX_EN_MASK (0x1 << I40E_PFPCI_FACTPS_FUNC_AUX_EN_SHIFT) |
| #define I40E_PFPCI_FUNC 0x000BE200 |
| #define I40E_PFPCI_FUNC_FUNC_DIS_SHIFT 0 |
| #define I40E_PFPCI_FUNC_FUNC_DIS_MASK (0x1 << I40E_PFPCI_FUNC_FUNC_DIS_SHIFT) |
| #define I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_SHIFT 1 |
| #define I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_MASK (0x1 << I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_SHIFT) |
| #define I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_SHIFT 2 |
| #define I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_MASK (0x1 << I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_SHIFT) |
| #define I40E_PFPCI_FUNC2 0x000BE180 |
| #define I40E_PFPCI_FUNC2_EMP_FUNC_DIS_SHIFT 0 |
| #define I40E_PFPCI_FUNC2_EMP_FUNC_DIS_MASK (0x1 << I40E_PFPCI_FUNC2_EMP_FUNC_DIS_SHIFT) |
| #define I40E_PFPCI_ICAUSE 0x0009C200 |
| #define I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_SHIFT 0 |
| #define I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_MASK (0xFFFFFFFF << I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_SHIFT) |
| #define I40E_PFPCI_IENA 0x0009C280 |
| #define I40E_PFPCI_IENA_PCIE_ERR_EN_SHIFT 0 |
| #define I40E_PFPCI_IENA_PCIE_ERR_EN_MASK (0xFFFFFFFF << I40E_PFPCI_IENA_PCIE_ERR_EN_SHIFT) |
| #define I40E_PFPCI_PFDEVID 0x000BE080 |
| #define I40E_PFPCI_PFDEVID_PF_DEV_ID_LAN_SHIFT 0 |
| #define I40E_PFPCI_PFDEVID_PF_DEV_ID_LAN_MASK (0xFFFF << I40E_PFPCI_PFDEVID_PF_DEV_ID_LAN_SHIFT) |
| #define I40E_PFPCI_PFDEVID_PF_DEV_ID_SAN_SHIFT 16 |
| #define I40E_PFPCI_PFDEVID_PF_DEV_ID_SAN_MASK (0xFFFF << I40E_PFPCI_PFDEVID_PF_DEV_ID_SAN_SHIFT) |
| #define I40E_PFPCI_PM 0x000BE300 |
| #define I40E_PFPCI_PM_PME_EN_SHIFT 0 |
| #define I40E_PFPCI_PM_PME_EN_MASK (0x1 << I40E_PFPCI_PM_PME_EN_SHIFT) |
| #define I40E_PFPCI_STATUS1 0x000BE280 |
| #define I40E_PFPCI_STATUS1_FUNC_VALID_SHIFT 0 |
| #define I40E_PFPCI_STATUS1_FUNC_VALID_MASK (0x1 << I40E_PFPCI_STATUS1_FUNC_VALID_SHIFT) |
| #define I40E_PFPCI_VFDEVID 0x000BE100 |
| #define I40E_PFPCI_VFDEVID_VF_DEV_ID_LAN_SHIFT 0 |
| #define I40E_PFPCI_VFDEVID_VF_DEV_ID_LAN_MASK (0xFFFF << I40E_PFPCI_VFDEVID_VF_DEV_ID_LAN_SHIFT) |
| #define I40E_PFPCI_VFDEVID_VF_DEV_ID_SAN_SHIFT 16 |
| #define I40E_PFPCI_VFDEVID_VF_DEV_ID_SAN_MASK (0xFFFF << I40E_PFPCI_VFDEVID_VF_DEV_ID_SAN_SHIFT) |
| #define I40E_PFPCI_VMINDEX 0x0009C300 |
| #define I40E_PFPCI_VMINDEX_VMINDEX_SHIFT 0 |
| #define I40E_PFPCI_VMINDEX_VMINDEX_MASK (0x1FF << I40E_PFPCI_VMINDEX_VMINDEX_SHIFT) |
| #define I40E_PFPCI_VMPEND 0x0009C380 |
| #define I40E_PFPCI_VMPEND_PENDING_SHIFT 0 |
| #define I40E_PFPCI_VMPEND_PENDING_MASK (0x1 << I40E_PFPCI_VMPEND_PENDING_SHIFT) |
| #define I40E_GLPE_CPUSTATUS0 0x0000D040 |
| #define I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_SHIFT 0 |
| #define I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_MASK (0xFFFFFFFF << I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_SHIFT) |
| #define I40E_GLPE_CPUSTATUS1 0x0000D044 |
| #define I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_SHIFT 0 |
| #define I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_MASK (0xFFFFFFFF << I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_SHIFT) |
| #define I40E_GLPE_CPUSTATUS2 0x0000D048 |
| #define I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_SHIFT 0 |
| #define I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_MASK (0xFFFFFFFF << I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_SHIFT) |
| #define I40E_GLPE_PFFLMOBJCTRL(_i) (0x0000D480 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLPE_PFFLMOBJCTRL_MAX_INDEX 15 |
| #define I40E_GLPE_PFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT 0 |
| #define I40E_GLPE_PFFLMOBJCTRL_XMIT_BLOCKSIZE_MASK (0x7 << I40E_GLPE_PFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT) |
| #define I40E_GLPE_PFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT 8 |
| #define I40E_GLPE_PFFLMOBJCTRL_Q1_BLOCKSIZE_MASK (0x7 << I40E_GLPE_PFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT) |
| #define I40E_GLPE_VFFLMOBJCTRL(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPE_VFFLMOBJCTRL_MAX_INDEX 31 |
| #define I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT 0 |
| #define I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_MASK (0x7 << I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT) |
| #define I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT 8 |
| #define I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_MASK (0x7 << I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT) |
| #define I40E_GLPE_VFFLMQ1ALLOCERR(_i) (0x0000C700 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPE_VFFLMQ1ALLOCERR_MAX_INDEX 31 |
| #define I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_SHIFT 0 |
| #define I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_MASK (0xFFFF << I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_SHIFT) |
| #define I40E_GLPE_VFFLMXMITALLOCERR(_i) (0x0000C600 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPE_VFFLMXMITALLOCERR_MAX_INDEX 31 |
| #define I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_SHIFT 0 |
| #define I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_MASK (0xFFFF << I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_SHIFT) |
| #define I40E_GLPE_VFUDACTRL(_i) (0x0000C000 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPE_VFUDACTRL_MAX_INDEX 31 |
| #define I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_SHIFT 0 |
| #define I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_MASK (0x1 << I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_SHIFT) |
| #define I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_SHIFT 1 |
| #define I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_MASK (0x1 << I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_SHIFT) |
| #define I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_SHIFT 2 |
| #define I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_MASK (0x1 << I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_SHIFT) |
| #define I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_SHIFT 3 |
| #define I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_MASK (0x1 << I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_SHIFT) |
| #define I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_SHIFT 4 |
| #define I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_MASK (0x1 << I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_SHIFT) |
| #define I40E_GLPE_VFUDAUCFBQPN(_i) (0x0000C100 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPE_VFUDAUCFBQPN_MAX_INDEX 31 |
| #define I40E_GLPE_VFUDAUCFBQPN_QPN_SHIFT 0 |
| #define I40E_GLPE_VFUDAUCFBQPN_QPN_MASK (0x3FFFF << I40E_GLPE_VFUDAUCFBQPN_QPN_SHIFT) |
| #define I40E_GLPE_VFUDAUCFBQPN_VALID_SHIFT 31 |
| #define I40E_GLPE_VFUDAUCFBQPN_VALID_MASK (0x1 << I40E_GLPE_VFUDAUCFBQPN_VALID_SHIFT) |
| #define I40E_PFPE_AEQALLOC 0x00131180 |
| #define I40E_PFPE_AEQALLOC_AECOUNT_SHIFT 0 |
| #define I40E_PFPE_AEQALLOC_AECOUNT_MASK (0xFFFFFFFF << I40E_PFPE_AEQALLOC_AECOUNT_SHIFT) |
| #define I40E_PFPE_CCQPHIGH 0x00008200 |
| #define I40E_PFPE_CCQPHIGH_PECCQPHIGH_SHIFT 0 |
| #define I40E_PFPE_CCQPHIGH_PECCQPHIGH_MASK (0xFFFFFFFF << I40E_PFPE_CCQPHIGH_PECCQPHIGH_SHIFT) |
| #define I40E_PFPE_CCQPLOW 0x00008180 |
| #define I40E_PFPE_CCQPLOW_PECCQPLOW_SHIFT 0 |
| #define I40E_PFPE_CCQPLOW_PECCQPLOW_MASK (0xFFFFFFFF << I40E_PFPE_CCQPLOW_PECCQPLOW_SHIFT) |
| #define I40E_PFPE_CCQPSTATUS 0x00008100 |
| #define I40E_PFPE_CCQPSTATUS_CCQP_DONE_SHIFT 0 |
| #define I40E_PFPE_CCQPSTATUS_CCQP_DONE_MASK (0x1 << I40E_PFPE_CCQPSTATUS_CCQP_DONE_SHIFT) |
| #define I40E_PFPE_CCQPSTATUS_CCQP_ERR_SHIFT 31 |
| #define I40E_PFPE_CCQPSTATUS_CCQP_ERR_MASK (0x1 << I40E_PFPE_CCQPSTATUS_CCQP_ERR_SHIFT) |
| #define I40E_PFPE_CQACK 0x00131100 |
| #define I40E_PFPE_CQACK_PECQID_SHIFT 0 |
| #define I40E_PFPE_CQACK_PECQID_MASK (0x1FFFF << I40E_PFPE_CQACK_PECQID_SHIFT) |
| #define I40E_PFPE_CQARM 0x00131080 |
| #define I40E_PFPE_CQARM_PECQID_SHIFT 0 |
| #define I40E_PFPE_CQARM_PECQID_MASK (0x1FFFF << I40E_PFPE_CQARM_PECQID_SHIFT) |
| #define I40E_PFPE_CQPDB 0x00008000 |
| #define I40E_PFPE_CQPDB_WQHEAD_SHIFT 0 |
| #define I40E_PFPE_CQPDB_WQHEAD_MASK (0x7FF << I40E_PFPE_CQPDB_WQHEAD_SHIFT) |
| #define I40E_PFPE_CQPERRCODES 0x00008880 |
| #define I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT 0 |
| #define I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_MASK (0xFFFF << I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT) |
| #define I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT 16 |
| #define I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK (0xFFFF << I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT) |
| #define I40E_PFPE_CQPTAIL 0x00008080 |
| #define I40E_PFPE_CQPTAIL_WQTAIL_SHIFT 0 |
| #define I40E_PFPE_CQPTAIL_WQTAIL_MASK (0x7FF << I40E_PFPE_CQPTAIL_WQTAIL_SHIFT) |
| #define I40E_PFPE_CQPTAIL_CQP_OP_ERR_SHIFT 31 |
| #define I40E_PFPE_CQPTAIL_CQP_OP_ERR_MASK (0x1 << I40E_PFPE_CQPTAIL_CQP_OP_ERR_SHIFT) |
| #define I40E_PFPE_FLMQ1ALLOCERR 0x00008980 |
| #define I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_SHIFT 0 |
| #define I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_MASK (0xFFFF << I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_SHIFT) |
| #define I40E_PFPE_FLMXMITALLOCERR 0x00008900 |
| #define I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_SHIFT 0 |
| #define I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_MASK (0xFFFF << I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_SHIFT) |
| #define I40E_PFPE_IPCONFIG0 0x00008280 |
| #define I40E_PFPE_IPCONFIG0_PEIPID_SHIFT 0 |
| #define I40E_PFPE_IPCONFIG0_PEIPID_MASK (0xFFFF << I40E_PFPE_IPCONFIG0_PEIPID_SHIFT) |
| #define I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT 16 |
| #define I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_MASK (0x1 << I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT) |
| |
| #define I40E_PFPE_MRTEIDXMASK 0x00008600 |
| #define I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT 0 |
| #define I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_MASK (0x1F << I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT) |
| #define I40E_PFPE_RCVUNEXPECTEDERROR 0x00008680 |
| #define I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT 0 |
| #define I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_MASK (0xFFFFFF << I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT) |
| #define I40E_PFPE_TCPNOWTIMER 0x00008580 |
| #define I40E_PFPE_TCPNOWTIMER_TCP_NOW_SHIFT 0 |
| #define I40E_PFPE_TCPNOWTIMER_TCP_NOW_MASK (0xFFFFFFFF << I40E_PFPE_TCPNOWTIMER_TCP_NOW_SHIFT) |
| #define I40E_PFPE_UDACTRL 0x00008700 |
| #define I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_SHIFT 0 |
| #define I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_MASK (0x1 << I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_SHIFT) |
| #define I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_SHIFT 1 |
| #define I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_MASK (0x1 << I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_SHIFT) |
| #define I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_SHIFT 2 |
| #define I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_MASK (0x1 << I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_SHIFT) |
| #define I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_SHIFT 3 |
| #define I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_MASK (0x1 << I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_SHIFT) |
| #define I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_SHIFT 4 |
| #define I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_MASK (0x1 << I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_SHIFT) |
| #define I40E_PFPE_UDAUCFBQPN 0x00008780 |
| #define I40E_PFPE_UDAUCFBQPN_QPN_SHIFT 0 |
| #define I40E_PFPE_UDAUCFBQPN_QPN_MASK (0x3FFFF << I40E_PFPE_UDAUCFBQPN_QPN_SHIFT) |
| #define I40E_PFPE_UDAUCFBQPN_VALID_SHIFT 31 |
| #define I40E_PFPE_UDAUCFBQPN_VALID_MASK (0x1 << I40E_PFPE_UDAUCFBQPN_VALID_SHIFT) |
| #define I40E_PFPE_WQEALLOC 0x00138C00 |
| #define I40E_PFPE_WQEALLOC_PEQPID_SHIFT 0 |
| #define I40E_PFPE_WQEALLOC_PEQPID_MASK (0x3FFFF << I40E_PFPE_WQEALLOC_PEQPID_SHIFT) |
| #define I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT 20 |
| #define I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_MASK (0xFFF << I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT) |
| #define I40E_VFPE_AEQALLOC(_VF) (0x00130C00 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VFPE_AEQALLOC_MAX_INDEX 127 |
| #define I40E_VFPE_AEQALLOC_AECOUNT_SHIFT 0 |
| #define I40E_VFPE_AEQALLOC_AECOUNT_MASK (0xFFFFFFFF << I40E_VFPE_AEQALLOC_AECOUNT_SHIFT) |
| #define I40E_VFPE_CCQPHIGH(_VF) (0x00001000 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VFPE_CCQPHIGH_MAX_INDEX 127 |
| #define I40E_VFPE_CCQPHIGH_PECCQPHIGH_SHIFT 0 |
| #define I40E_VFPE_CCQPHIGH_PECCQPHIGH_MASK (0xFFFFFFFF << I40E_VFPE_CCQPHIGH_PECCQPHIGH_SHIFT) |
| #define I40E_VFPE_CCQPLOW(_VF) (0x00000C00 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VFPE_CCQPLOW_MAX_INDEX 127 |
| #define I40E_VFPE_CCQPLOW_PECCQPLOW_SHIFT 0 |
| #define I40E_VFPE_CCQPLOW_PECCQPLOW_MASK (0xFFFFFFFF << I40E_VFPE_CCQPLOW_PECCQPLOW_SHIFT) |
| #define I40E_VFPE_CCQPSTATUS(_VF) (0x00000800 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VFPE_CCQPSTATUS_MAX_INDEX 127 |
| #define I40E_VFPE_CCQPSTATUS_CCQP_DONE_SHIFT 0 |
| #define I40E_VFPE_CCQPSTATUS_CCQP_DONE_MASK (0x1 << I40E_VFPE_CCQPSTATUS_CCQP_DONE_SHIFT) |
| #define I40E_VFPE_CCQPSTATUS_CCQP_ERR_SHIFT 31 |
| #define I40E_VFPE_CCQPSTATUS_CCQP_ERR_MASK (0x1 << I40E_VFPE_CCQPSTATUS_CCQP_ERR_SHIFT) |
| #define I40E_VFPE_CQACK(_VF) (0x00130800 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VFPE_CQACK_MAX_INDEX 127 |
| #define I40E_VFPE_CQACK_PECQID_SHIFT 0 |
| #define I40E_VFPE_CQACK_PECQID_MASK (0x1FFFF << I40E_VFPE_CQACK_PECQID_SHIFT) |
| #define I40E_VFPE_CQARM(_VF) (0x00130400 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VFPE_CQARM_MAX_INDEX 127 |
| #define I40E_VFPE_CQARM_PECQID_SHIFT 0 |
| #define I40E_VFPE_CQARM_PECQID_MASK (0x1FFFF << I40E_VFPE_CQARM_PECQID_SHIFT) |
| #define I40E_VFPE_CQPDB(_VF) (0x00000000 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VFPE_CQPDB_MAX_INDEX 127 |
| #define I40E_VFPE_CQPDB_WQHEAD_SHIFT 0 |
| #define I40E_VFPE_CQPDB_WQHEAD_MASK (0x7FF << I40E_VFPE_CQPDB_WQHEAD_SHIFT) |
| #define I40E_VFPE_CQPERRCODES(_VF) (0x00001800 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VFPE_CQPERRCODES_MAX_INDEX 127 |
| #define I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT 0 |
| #define I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_MASK (0xFFFF << I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT) |
| #define I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT 16 |
| #define I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK (0xFFFF << I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT) |
| #define I40E_VFPE_CQPTAIL(_VF) (0x00000400 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VFPE_CQPTAIL_MAX_INDEX 127 |
| #define I40E_VFPE_CQPTAIL_WQTAIL_SHIFT 0 |
| #define I40E_VFPE_CQPTAIL_WQTAIL_MASK (0x7FF << I40E_VFPE_CQPTAIL_WQTAIL_SHIFT) |
| #define I40E_VFPE_CQPTAIL_CQP_OP_ERR_SHIFT 31 |
| #define I40E_VFPE_CQPTAIL_CQP_OP_ERR_MASK (0x1 << I40E_VFPE_CQPTAIL_CQP_OP_ERR_SHIFT) |
| #define I40E_VFPE_IPCONFIG0(_VF) (0x00001400 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VFPE_IPCONFIG0_MAX_INDEX 127 |
| #define I40E_VFPE_IPCONFIG0_PEIPID_SHIFT 0 |
| #define I40E_VFPE_IPCONFIG0_PEIPID_MASK (0xFFFF << I40E_VFPE_IPCONFIG0_PEIPID_SHIFT) |
| #define I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT 16 |
| #define I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_MASK (0x1 << I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT) |
| #define I40E_VFPE_MRTEIDXMASK(_VF) (0x00003000 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VFPE_MRTEIDXMASK_MAX_INDEX 127 |
| #define I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT 0 |
| #define I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_MASK (0x1F << I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT) |
| #define I40E_VFPE_RCVUNEXPECTEDERROR(_VF) (0x00003400 + ((_VF) * 4)) |
| #define I40E_VFPE_RCVUNEXPECTEDERROR_MAX_INDEX 127 |
| #define I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT 0 |
| #define I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_MASK (0xFFFFFF << I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT) |
| #define I40E_VFPE_TCPNOWTIMER(_VF) (0x00002C00 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VFPE_TCPNOWTIMER_MAX_INDEX 127 |
| #define I40E_VFPE_TCPNOWTIMER_TCP_NOW_SHIFT 0 |
| #define I40E_VFPE_TCPNOWTIMER_TCP_NOW_MASK (0xFFFFFFFF << I40E_VFPE_TCPNOWTIMER_TCP_NOW_SHIFT) |
| #define I40E_VFPE_WQEALLOC(_VF) (0x00138000 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VFPE_WQEALLOC_MAX_INDEX 127 |
| #define I40E_VFPE_WQEALLOC_PEQPID_SHIFT 0 |
| #define I40E_VFPE_WQEALLOC_PEQPID_MASK (0x3FFFF << I40E_VFPE_WQEALLOC_PEQPID_SHIFT) |
| #define I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT 20 |
| #define I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_MASK (0xFFF << I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT) |
| #define I40E_GLPES_PFIP4RXDISCARD(_i) (0x00010600 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP4RXDISCARD_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_SHIFT 0 |
| #define I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_SHIFT) |
| #define I40E_GLPES_PFIP4RXFRAGSHI(_i) (0x00010804 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP4RXFRAGSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT 0 |
| #define I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_MASK (0xFFFF << I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT) |
| #define I40E_GLPES_PFIP4RXFRAGSLO(_i) (0x00010800 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP4RXFRAGSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT 0 |
| #define I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT) |
| #define I40E_GLPES_PFIP4RXMCOCTSHI(_i) (0x00010A04 + ((_i) * 8)) |
| #define I40E_GLPES_PFIP4RXMCOCTSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT 0 |
| #define I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT) |
| #define I40E_GLPES_PFIP4RXMCOCTSLO(_i) (0x00010A00 + ((_i) * 8)) |
| #define I40E_GLPES_PFIP4RXMCOCTSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT 0 |
| #define I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT) |
| #define I40E_GLPES_PFIP4RXMCPKTSHI(_i) (0x00010C04 + ((_i) * 8)) |
| #define I40E_GLPES_PFIP4RXMCPKTSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT 0 |
| #define I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT) |
| #define I40E_GLPES_PFIP4RXMCPKTSLO(_i) (0x00010C00 + ((_i) * 8)) |
| #define I40E_GLPES_PFIP4RXMCPKTSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT 0 |
| #define I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT) |
| #define I40E_GLPES_PFIP4RXOCTSHI(_i) (0x00010204 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP4RXOCTSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT 0 |
| #define I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT) |
| #define I40E_GLPES_PFIP4RXOCTSLO(_i) (0x00010200 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP4RXOCTSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT 0 |
| #define I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT) |
| #define I40E_GLPES_PFIP4RXPKTSHI(_i) (0x00010404 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP4RXPKTSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT 0 |
| #define I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT) |
| #define I40E_GLPES_PFIP4RXPKTSLO(_i) (0x00010400 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP4RXPKTSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT 0 |
| #define I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT) |
| #define I40E_GLPES_PFIP4RXTRUNC(_i) (0x00010700 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP4RXTRUNC_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_SHIFT 0 |
| #define I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_SHIFT) |
| #define I40E_GLPES_PFIP4TXFRAGSHI(_i) (0x00011E04 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP4TXFRAGSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT 0 |
| #define I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_MASK (0xFFFF << I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT) |
| #define I40E_GLPES_PFIP4TXFRAGSLO(_i) (0x00011E00 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP4TXFRAGSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT 0 |
| #define I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT) |
| #define I40E_GLPES_PFIP4TXMCOCTSHI(_i) (0x00012004 + ((_i) * 8)) |
| #define I40E_GLPES_PFIP4TXMCOCTSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT 0 |
| #define I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT) |
| #define I40E_GLPES_PFIP4TXMCOCTSLO(_i) (0x00012000 + ((_i) * 8)) |
| #define I40E_GLPES_PFIP4TXMCOCTSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT 0 |
| #define I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT) |
| #define I40E_GLPES_PFIP4TXMCPKTSHI(_i) (0x00012204 + ((_i) * 8)) |
| #define I40E_GLPES_PFIP4TXMCPKTSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT 0 |
| #define I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT) |
| #define I40E_GLPES_PFIP4TXMCPKTSLO(_i) (0x00012200 + ((_i) * 8)) |
| #define I40E_GLPES_PFIP4TXMCPKTSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT 0 |
| #define I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT) |
| #define I40E_GLPES_PFIP4TXNOROUTE(_i) (0x00012E00 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP4TXNOROUTE_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT 0 |
| #define I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_MASK (0xFFFFFF << I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT) |
| #define I40E_GLPES_PFIP4TXOCTSHI(_i) (0x00011A04 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP4TXOCTSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT 0 |
| #define I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT) |
| #define I40E_GLPES_PFIP4TXOCTSLO(_i) (0x00011A00 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP4TXOCTSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT 0 |
| #define I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT) |
| #define I40E_GLPES_PFIP4TXPKTSHI(_i) (0x00011C04 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP4TXPKTSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT 0 |
| #define I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT) |
| #define I40E_GLPES_PFIP4TXPKTSLO(_i) (0x00011C00 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP4TXPKTSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT 0 |
| #define I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT) |
| #define I40E_GLPES_PFIP6RXDISCARD(_i) (0x00011200 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP6RXDISCARD_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_SHIFT 0 |
| #define I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_SHIFT) |
| #define I40E_GLPES_PFIP6RXFRAGSHI(_i) (0x00011404 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP6RXFRAGSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT 0 |
| #define I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_MASK (0xFFFF << I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT) |
| #define I40E_GLPES_PFIP6RXFRAGSLO(_i) (0x00011400 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP6RXFRAGSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT 0 |
| #define I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT) |
| #define I40E_GLPES_PFIP6RXMCOCTSHI(_i) (0x00011604 + ((_i) * 8)) |
| #define I40E_GLPES_PFIP6RXMCOCTSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT 0 |
| #define I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT) |
| #define I40E_GLPES_PFIP6RXMCOCTSLO(_i) (0x00011600 + ((_i) * 8)) |
| #define I40E_GLPES_PFIP6RXMCOCTSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT 0 |
| #define I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT) |
| #define I40E_GLPES_PFIP6RXMCPKTSHI(_i) (0x00011804 + ((_i) * 8)) |
| #define I40E_GLPES_PFIP6RXMCPKTSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT 0 |
| #define I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT) |
| #define I40E_GLPES_PFIP6RXMCPKTSLO(_i) (0x00011800 + ((_i) * 8)) |
| #define I40E_GLPES_PFIP6RXMCPKTSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT 0 |
| #define I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT) |
| #define I40E_GLPES_PFIP6RXOCTSHI(_i) (0x00010E04 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP6RXOCTSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT 0 |
| #define I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT) |
| #define I40E_GLPES_PFIP6RXOCTSLO(_i) (0x00010E00 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP6RXOCTSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT 0 |
| #define I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT) |
| #define I40E_GLPES_PFIP6RXPKTSHI(_i) (0x00011004 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP6RXPKTSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT 0 |
| #define I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT) |
| #define I40E_GLPES_PFIP6RXPKTSLO(_i) (0x00011000 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP6RXPKTSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT 0 |
| #define I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT) |
| #define I40E_GLPES_PFIP6RXTRUNC(_i) (0x00011300 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP6RXTRUNC_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_SHIFT 0 |
| #define I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_SHIFT) |
| #define I40E_GLPES_PFIP6TXFRAGSHI(_i) (0x00012804 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP6TXFRAGSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT 0 |
| #define I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_MASK (0xFFFF << I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT) |
| #define I40E_GLPES_PFIP6TXFRAGSLO(_i) (0x00012800 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP6TXFRAGSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT 0 |
| #define I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT) |
| #define I40E_GLPES_PFIP6TXMCOCTSHI(_i) (0x00012A04 + ((_i) * 8)) |
| #define I40E_GLPES_PFIP6TXMCOCTSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT 0 |
| #define I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT) |
| #define I40E_GLPES_PFIP6TXMCOCTSLO(_i) (0x00012A00 + ((_i) * 8)) |
| #define I40E_GLPES_PFIP6TXMCOCTSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT 0 |
| #define I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT) |
| #define I40E_GLPES_PFIP6TXMCPKTSHI(_i) (0x00012C04 + ((_i) * 8)) |
| #define I40E_GLPES_PFIP6TXMCPKTSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT 0 |
| #define I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT) |
| #define I40E_GLPES_PFIP6TXMCPKTSLO(_i) (0x00012C00 + ((_i) * 8)) |
| #define I40E_GLPES_PFIP6TXMCPKTSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT 0 |
| #define I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT) |
| #define I40E_GLPES_PFIP6TXNOROUTE(_i) (0x00012F00 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP6TXNOROUTE_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT 0 |
| #define I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_MASK (0xFFFFFF << I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT) |
| #define I40E_GLPES_PFIP6TXOCTSHI(_i) (0x00012404 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP6TXOCTSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT 0 |
| #define I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT) |
| #define I40E_GLPES_PFIP6TXOCTSLO(_i) (0x00012400 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP6TXOCTSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT 0 |
| #define I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT) |
| #define I40E_GLPES_PFIP6TXPKTSHI(_i) (0x00012604 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP6TXPKTSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT 0 |
| #define I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT) |
| #define I40E_GLPES_PFIP6TXPKTSLO(_i) (0x00012600 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFIP6TXPKTSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT 0 |
| #define I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT) |
| #define I40E_GLPES_PFRDMARXRDSHI(_i) (0x00013E04 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFRDMARXRDSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_SHIFT 0 |
| #define I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_MASK (0xFFFF << I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_SHIFT) |
| #define I40E_GLPES_PFRDMARXRDSLO(_i) (0x00013E00 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFRDMARXRDSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_SHIFT 0 |
| #define I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_SHIFT) |
| #define I40E_GLPES_PFRDMARXSNDSHI(_i) (0x00014004 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFRDMARXSNDSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT 0 |
| #define I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_MASK (0xFFFF << I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT) |
| #define I40E_GLPES_PFRDMARXSNDSLO(_i) (0x00014000 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFRDMARXSNDSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT 0 |
| #define I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT) |
| #define I40E_GLPES_PFRDMARXWRSHI(_i) (0x00013C04 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFRDMARXWRSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_SHIFT 0 |
| #define I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_MASK (0xFFFF << I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_SHIFT) |
| #define I40E_GLPES_PFRDMARXWRSLO(_i) (0x00013C00 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFRDMARXWRSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_SHIFT 0 |
| #define I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_SHIFT) |
| #define I40E_GLPES_PFRDMATXRDSHI(_i) (0x00014404 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFRDMATXRDSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_SHIFT 0 |
| #define I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_MASK (0xFFFF << I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_SHIFT) |
| #define I40E_GLPES_PFRDMATXRDSLO(_i) (0x00014400 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFRDMATXRDSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_SHIFT 0 |
| #define I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_SHIFT) |
| #define I40E_GLPES_PFRDMATXSNDSHI(_i) (0x00014604 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFRDMATXSNDSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT 0 |
| #define I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_MASK (0xFFFF << I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT) |
| #define I40E_GLPES_PFRDMATXSNDSLO(_i) (0x00014600 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFRDMATXSNDSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT 0 |
| #define I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT) |
| #define I40E_GLPES_PFRDMATXWRSHI(_i) (0x00014204 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFRDMATXWRSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_SHIFT 0 |
| #define I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_MASK (0xFFFF << I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_SHIFT) |
| #define I40E_GLPES_PFRDMATXWRSLO(_i) (0x00014200 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFRDMATXWRSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_SHIFT 0 |
| #define I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_SHIFT) |
| #define I40E_GLPES_PFRDMAVBNDHI(_i) (0x00014804 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFRDMAVBNDHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_SHIFT 0 |
| #define I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_SHIFT) |
| #define I40E_GLPES_PFRDMAVBNDLO(_i) (0x00014800 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFRDMAVBNDLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_SHIFT 0 |
| #define I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_SHIFT) |
| #define I40E_GLPES_PFRDMAVINVHI(_i) (0x00014A04 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFRDMAVINVHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_SHIFT 0 |
| #define I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_SHIFT) |
| #define I40E_GLPES_PFRDMAVINVLO(_i) (0x00014A00 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFRDMAVINVLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_SHIFT 0 |
| #define I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_SHIFT) |
| #define I40E_GLPES_PFRXVLANERR(_i) (0x00010000 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLPES_PFRXVLANERR_MAX_INDEX 15 |
| #define I40E_GLPES_PFRXVLANERR_RXVLANERR_SHIFT 0 |
| #define I40E_GLPES_PFRXVLANERR_RXVLANERR_MASK (0xFFFFFF << I40E_GLPES_PFRXVLANERR_RXVLANERR_SHIFT) |
| #define I40E_GLPES_PFTCPRTXSEG(_i) (0x00013600 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLPES_PFTCPRTXSEG_MAX_INDEX 15 |
| #define I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_SHIFT 0 |
| #define I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_MASK (0xFFFFFFFF << I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_SHIFT) |
| #define I40E_GLPES_PFTCPRXOPTERR(_i) (0x00013200 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_GLPES_PFTCPRXOPTERR_MAX_INDEX 15 |
| #define I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_SHIFT 0 |
| #define I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_MASK (0xFFFFFF << I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_SHIFT) |
| #define I40E_GLPES_PFTCPRXPROTOERR(_i) (0x00013300 + ((_i) * 4)) |
| #define I40E_GLPES_PFTCPRXPROTOERR_MAX_INDEX 15 |
| #define I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT 0 |
| #define I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_MASK (0xFFFFFF << I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT) |
| #define I40E_GLPES_PFTCPRXSEGSHI(_i) (0x00013004 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFTCPRXSEGSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT 0 |
| #define I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_MASK (0xFFFF << I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT) |
| #define I40E_GLPES_PFTCPRXSEGSLO(_i) (0x00013000 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFTCPRXSEGSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT 0 |
| #define I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT) |
| #define I40E_GLPES_PFTCPTXSEGHI(_i) (0x00013404 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFTCPTXSEGHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_SHIFT 0 |
| #define I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_MASK (0xFFFF << I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_SHIFT) |
| #define I40E_GLPES_PFTCPTXSEGLO(_i) (0x00013400 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFTCPTXSEGLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_SHIFT 0 |
| #define I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_MASK (0xFFFFFFFF << I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_SHIFT) |
| #define I40E_GLPES_PFUDPRXPKTSHI(_i) (0x00013804 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFUDPRXPKTSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT 0 |
| #define I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT) |
| #define I40E_GLPES_PFUDPRXPKTSLO(_i) (0x00013800 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFUDPRXPKTSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT 0 |
| #define I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT) |
| #define I40E_GLPES_PFUDPTXPKTSHI(_i) (0x00013A04 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFUDPTXPKTSHI_MAX_INDEX 15 |
| #define I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT 0 |
| #define I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT) |
| #define I40E_GLPES_PFUDPTXPKTSLO(_i) (0x00013A00 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLPES_PFUDPTXPKTSLO_MAX_INDEX 15 |
| #define I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT 0 |
| #define I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT) |
| #define I40E_GLPES_RDMARXMULTFPDUSHI 0x0001E014 |
| #define I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_SHIFT 0 |
| #define I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_MASK (0xFFFFFF << I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_SHIFT) |
| #define I40E_GLPES_RDMARXMULTFPDUSLO 0x0001E010 |
| #define I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_SHIFT 0 |
| #define I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_MASK (0xFFFFFFFF << I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_SHIFT) |
| #define I40E_GLPES_RDMARXOOODDPHI 0x0001E01C |
| #define I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_SHIFT 0 |
| #define I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_MASK (0xFFFFFF << I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_SHIFT) |
| #define I40E_GLPES_RDMARXOOODDPLO 0x0001E018 |
| #define I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_SHIFT 0 |
| #define I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_MASK (0xFFFFFFFF << I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_SHIFT) |
| #define I40E_GLPES_RDMARXOOONOMARK 0x0001E004 |
| #define I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_SHIFT 0 |
| #define I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_MASK (0xFFFFFFFF << I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_SHIFT) |
| #define I40E_GLPES_RDMARXUNALIGN 0x0001E000 |
| #define I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_SHIFT 0 |
| #define I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_MASK (0xFFFFFFFF << I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_SHIFT) |
| #define I40E_GLPES_TCPRXFOURHOLEHI 0x0001E044 |
| #define I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_SHIFT 0 |
| #define I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_MASK (0xFFFFFF << I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_SHIFT) |
| #define I40E_GLPES_TCPRXFOURHOLELO 0x0001E040 |
| #define I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_SHIFT 0 |
| #define I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_MASK (0xFFFFFFFF << I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_SHIFT) |
| #define I40E_GLPES_TCPRXONEHOLEHI 0x0001E02C |
| #define I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_SHIFT 0 |
| #define I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_MASK (0xFFFFFF << I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_SHIFT) |
| #define I40E_GLPES_TCPRXONEHOLELO 0x0001E028 |
| #define I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_SHIFT 0 |
| #define I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_MASK (0xFFFFFFFF << I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_SHIFT) |
| #define I40E_GLPES_TCPRXPUREACKHI 0x0001E024 |
| #define I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_SHIFT 0 |
| #define I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_MASK (0xFFFFFF << I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_SHIFT) |
| #define I40E_GLPES_TCPRXPUREACKSLO 0x0001E020 |
| #define I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_SHIFT 0 |
| #define I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_MASK (0xFFFFFFFF << I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_SHIFT) |
| #define I40E_GLPES_TCPRXTHREEHOLEHI 0x0001E03C |
| #define I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_SHIFT 0 |
| #define I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_MASK (0xFFFFFF << I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_SHIFT) |
| #define I40E_GLPES_TCPRXTHREEHOLELO 0x0001E038 |
| #define I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_SHIFT 0 |
| #define I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_MASK (0xFFFFFFFF << I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_SHIFT) |
| #define I40E_GLPES_TCPRXTWOHOLEHI 0x0001E034 |
| #define I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_SHIFT 0 |
| #define I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_MASK (0xFFFFFF << I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_SHIFT) |
| #define I40E_GLPES_TCPRXTWOHOLELO 0x0001E030 |
| #define I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_SHIFT 0 |
| #define I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_MASK (0xFFFFFFFF << I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_SHIFT) |
| #define I40E_GLPES_TCPRXUNEXPERR 0x0001E008 |
| #define I40E_GLPES_TCPRXUNEXPERR_TCPRXUNEXPERR_SHIFT 0 |
| #define I40E_GLPES_TCPRXUNEXPERR_TCPRXUNEXPERR_MASK (0xFFFFFF << I40E_GLPES_TCPRXUNEXPERR_TCPRXUNEXPERR_SHIFT) |
| #define I40E_GLPES_TCPTXRETRANSFASTHI 0x0001E04C |
| #define I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_SHIFT 0 |
| #define I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_MASK (0xFFFFFF << I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_SHIFT) |
| #define I40E_GLPES_TCPTXRETRANSFASTLO 0x0001E048 |
| #define I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_SHIFT 0 |
| #define I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_MASK (0xFFFFFFFF << I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_SHIFT) |
| #define I40E_GLPES_TCPTXTOUTSFASTHI 0x0001E054 |
| #define I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_SHIFT 0 |
| #define I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_MASK (0xFFFFFF << I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_SHIFT) |
| #define I40E_GLPES_TCPTXTOUTSFASTLO 0x0001E050 |
| #define I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_SHIFT 0 |
| #define I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_MASK (0xFFFFFFFF << I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_SHIFT) |
| #define I40E_GLPES_TCPTXTOUTSHI 0x0001E05C |
| #define I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_SHIFT 0 |
| #define I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_MASK (0xFFFFFF << I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_SHIFT) |
| #define I40E_GLPES_TCPTXTOUTSLO 0x0001E058 |
| #define I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_SHIFT 0 |
| #define I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_MASK (0xFFFFFFFF << I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_SHIFT) |
| #define I40E_GLPES_VFIP4RXDISCARD(_i) (0x00018600 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP4RXDISCARD_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_SHIFT 0 |
| #define I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_SHIFT) |
| #define I40E_GLPES_VFIP4RXFRAGSHI(_i) (0x00018804 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP4RXFRAGSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT 0 |
| #define I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_MASK (0xFFFF << I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT) |
| #define I40E_GLPES_VFIP4RXFRAGSLO(_i) (0x00018800 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP4RXFRAGSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT 0 |
| #define I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT) |
| #define I40E_GLPES_VFIP4RXMCOCTSHI(_i) (0x00018A04 + ((_i) * 4)) |
| #define I40E_GLPES_VFIP4RXMCOCTSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT 0 |
| #define I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT) |
| #define I40E_GLPES_VFIP4RXMCOCTSLO(_i) (0x00018A00 + ((_i) * 4)) |
| #define I40E_GLPES_VFIP4RXMCOCTSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT 0 |
| #define I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT) |
| #define I40E_GLPES_VFIP4RXMCPKTSHI(_i) (0x00018C04 + ((_i) * 4)) |
| #define I40E_GLPES_VFIP4RXMCPKTSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT 0 |
| #define I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT) |
| #define I40E_GLPES_VFIP4RXMCPKTSLO(_i) (0x00018C00 + ((_i) * 4)) |
| #define I40E_GLPES_VFIP4RXMCPKTSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT 0 |
| #define I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT) |
| #define I40E_GLPES_VFIP4RXOCTSHI(_i) (0x00018204 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP4RXOCTSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT 0 |
| #define I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT) |
| #define I40E_GLPES_VFIP4RXOCTSLO(_i) (0x00018200 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP4RXOCTSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT 0 |
| #define I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT) |
| #define I40E_GLPES_VFIP4RXPKTSHI(_i) (0x00018404 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP4RXPKTSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT 0 |
| #define I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT) |
| #define I40E_GLPES_VFIP4RXPKTSLO(_i) (0x00018400 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP4RXPKTSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT 0 |
| #define I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT) |
| #define I40E_GLPES_VFIP4RXTRUNC(_i) (0x00018700 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP4RXTRUNC_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_SHIFT 0 |
| #define I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_SHIFT) |
| #define I40E_GLPES_VFIP4TXFRAGSHI(_i) (0x00019E04 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP4TXFRAGSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT 0 |
| #define I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_MASK (0xFFFF << I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT) |
| #define I40E_GLPES_VFIP4TXFRAGSLO(_i) (0x00019E00 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP4TXFRAGSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT 0 |
| #define I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT) |
| #define I40E_GLPES_VFIP4TXMCOCTSHI(_i) (0x0001A004 + ((_i) * 4)) |
| #define I40E_GLPES_VFIP4TXMCOCTSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT 0 |
| #define I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT) |
| #define I40E_GLPES_VFIP4TXMCOCTSLO(_i) (0x0001A000 + ((_i) * 4)) |
| #define I40E_GLPES_VFIP4TXMCOCTSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT 0 |
| #define I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT) |
| #define I40E_GLPES_VFIP4TXMCPKTSHI(_i) (0x0001A204 + ((_i) * 4)) |
| #define I40E_GLPES_VFIP4TXMCPKTSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT 0 |
| #define I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT) |
| #define I40E_GLPES_VFIP4TXMCPKTSLO(_i) (0x0001A200 + ((_i) * 4)) |
| #define I40E_GLPES_VFIP4TXMCPKTSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT 0 |
| #define I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT) |
| #define I40E_GLPES_VFIP4TXNOROUTE(_i) (0x0001AE00 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP4TXNOROUTE_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT 0 |
| #define I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_MASK (0xFFFFFF << I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT) |
| #define I40E_GLPES_VFIP4TXOCTSHI(_i) (0x00019A04 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP4TXOCTSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT 0 |
| #define I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT) |
| #define I40E_GLPES_VFIP4TXOCTSLO(_i) (0x00019A00 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP4TXOCTSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT 0 |
| #define I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT) |
| #define I40E_GLPES_VFIP4TXPKTSHI(_i) (0x00019C04 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP4TXPKTSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT 0 |
| #define I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT) |
| #define I40E_GLPES_VFIP4TXPKTSLO(_i) (0x00019C00 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP4TXPKTSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT 0 |
| #define I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT) |
| #define I40E_GLPES_VFIP6RXDISCARD(_i) (0x00019200 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP6RXDISCARD_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_SHIFT 0 |
| #define I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_SHIFT) |
| #define I40E_GLPES_VFIP6RXFRAGSHI(_i) (0x00019404 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP6RXFRAGSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT 0 |
| #define I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_MASK (0xFFFF << I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT) |
| #define I40E_GLPES_VFIP6RXFRAGSLO(_i) (0x00019400 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP6RXFRAGSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT 0 |
| #define I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT) |
| #define I40E_GLPES_VFIP6RXMCOCTSHI(_i) (0x00019604 + ((_i) * 4)) |
| #define I40E_GLPES_VFIP6RXMCOCTSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT 0 |
| #define I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT) |
| #define I40E_GLPES_VFIP6RXMCOCTSLO(_i) (0x00019600 + ((_i) * 4)) |
| #define I40E_GLPES_VFIP6RXMCOCTSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT 0 |
| #define I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT) |
| #define I40E_GLPES_VFIP6RXMCPKTSHI(_i) (0x00019804 + ((_i) * 4)) |
| #define I40E_GLPES_VFIP6RXMCPKTSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT 0 |
| #define I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT) |
| #define I40E_GLPES_VFIP6RXMCPKTSLO(_i) (0x00019800 + ((_i) * 4)) |
| #define I40E_GLPES_VFIP6RXMCPKTSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT 0 |
| #define I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT) |
| #define I40E_GLPES_VFIP6RXOCTSHI(_i) (0x00018E04 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP6RXOCTSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT 0 |
| #define I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT) |
| #define I40E_GLPES_VFIP6RXOCTSLO(_i) (0x00018E00 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP6RXOCTSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT 0 |
| #define I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT) |
| #define I40E_GLPES_VFIP6RXPKTSHI(_i) (0x00019004 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP6RXPKTSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT 0 |
| #define I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT) |
| #define I40E_GLPES_VFIP6RXPKTSLO(_i) (0x00019000 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP6RXPKTSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT 0 |
| #define I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT) |
| #define I40E_GLPES_VFIP6RXTRUNC(_i) (0x00019300 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP6RXTRUNC_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_SHIFT 0 |
| #define I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_SHIFT) |
| #define I40E_GLPES_VFIP6TXFRAGSHI(_i) (0x0001A804 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP6TXFRAGSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT 0 |
| #define I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_MASK (0xFFFF << I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT) |
| #define I40E_GLPES_VFIP6TXFRAGSLO(_i) (0x0001A800 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP6TXFRAGSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT 0 |
| #define I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT) |
| #define I40E_GLPES_VFIP6TXMCOCTSHI(_i) (0x0001AA04 + ((_i) * 4)) |
| #define I40E_GLPES_VFIP6TXMCOCTSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT 0 |
| #define I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT) |
| #define I40E_GLPES_VFIP6TXMCOCTSLO(_i) (0x0001AA00 + ((_i) * 4)) |
| #define I40E_GLPES_VFIP6TXMCOCTSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT 0 |
| #define I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT) |
| #define I40E_GLPES_VFIP6TXMCPKTSHI(_i) (0x0001AC04 + ((_i) * 4)) |
| #define I40E_GLPES_VFIP6TXMCPKTSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT 0 |
| #define I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT) |
| #define I40E_GLPES_VFIP6TXMCPKTSLO(_i) (0x0001AC00 + ((_i) * 4)) |
| #define I40E_GLPES_VFIP6TXMCPKTSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT 0 |
| #define I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT) |
| #define I40E_GLPES_VFIP6TXNOROUTE(_i) (0x0001AF00 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP6TXNOROUTE_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT 0 |
| #define I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_MASK (0xFFFFFF << I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT) |
| #define I40E_GLPES_VFIP6TXOCTSHI(_i) (0x0001A404 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP6TXOCTSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT 0 |
| #define I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT) |
| #define I40E_GLPES_VFIP6TXOCTSLO(_i) (0x0001A400 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP6TXOCTSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT 0 |
| #define I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT) |
| #define I40E_GLPES_VFIP6TXPKTSHI(_i) (0x0001A604 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP6TXPKTSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT 0 |
| #define I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT) |
| #define I40E_GLPES_VFIP6TXPKTSLO(_i) (0x0001A600 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFIP6TXPKTSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT 0 |
| #define I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT) |
| #define I40E_GLPES_VFRDMARXRDSHI(_i) (0x0001BE04 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFRDMARXRDSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_SHIFT 0 |
| #define I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_MASK (0xFFFF << I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_SHIFT) |
| #define I40E_GLPES_VFRDMARXRDSLO(_i) (0x0001BE00 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFRDMARXRDSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_SHIFT 0 |
| #define I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_SHIFT) |
| #define I40E_GLPES_VFRDMARXSNDSHI(_i) (0x0001C004 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFRDMARXSNDSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT 0 |
| #define I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_MASK (0xFFFF << I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT) |
| #define I40E_GLPES_VFRDMARXSNDSLO(_i) (0x0001C000 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFRDMARXSNDSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT 0 |
| #define I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT) |
| #define I40E_GLPES_VFRDMARXWRSHI(_i) (0x0001BC04 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFRDMARXWRSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_SHIFT 0 |
| #define I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_MASK (0xFFFF << I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_SHIFT) |
| #define I40E_GLPES_VFRDMARXWRSLO(_i) (0x0001BC00 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFRDMARXWRSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_SHIFT 0 |
| #define I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_SHIFT) |
| #define I40E_GLPES_VFRDMATXRDSHI(_i) (0x0001C404 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFRDMATXRDSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_SHIFT 0 |
| #define I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_MASK (0xFFFF << I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_SHIFT) |
| #define I40E_GLPES_VFRDMATXRDSLO(_i) (0x0001C400 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFRDMATXRDSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_SHIFT 0 |
| #define I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_SHIFT) |
| #define I40E_GLPES_VFRDMATXSNDSHI(_i) (0x0001C604 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFRDMATXSNDSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT 0 |
| #define I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_MASK (0xFFFF << I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT) |
| #define I40E_GLPES_VFRDMATXSNDSLO(_i) (0x0001C600 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFRDMATXSNDSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT 0 |
| #define I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT) |
| #define I40E_GLPES_VFRDMATXWRSHI(_i) (0x0001C204 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFRDMATXWRSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_SHIFT 0 |
| #define I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_MASK (0xFFFF << I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_SHIFT) |
| #define I40E_GLPES_VFRDMATXWRSLO(_i) (0x0001C200 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFRDMATXWRSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_SHIFT 0 |
| #define I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_SHIFT) |
| #define I40E_GLPES_VFRDMAVBNDHI(_i) (0x0001C804 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFRDMAVBNDHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_SHIFT 0 |
| #define I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_SHIFT) |
| #define I40E_GLPES_VFRDMAVBNDLO(_i) (0x0001C800 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFRDMAVBNDLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_SHIFT 0 |
| #define I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_SHIFT) |
| #define I40E_GLPES_VFRDMAVINVHI(_i) (0x0001CA04 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFRDMAVINVHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_SHIFT 0 |
| #define I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_SHIFT) |
| #define I40E_GLPES_VFRDMAVINVLO(_i) (0x0001CA00 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFRDMAVINVLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_SHIFT 0 |
| #define I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_SHIFT) |
| #define I40E_GLPES_VFRXVLANERR(_i) (0x00018000 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFRXVLANERR_MAX_INDEX 31 |
| #define I40E_GLPES_VFRXVLANERR_RXVLANERR_SHIFT 0 |
| #define I40E_GLPES_VFRXVLANERR_RXVLANERR_MASK (0xFFFFFF << I40E_GLPES_VFRXVLANERR_RXVLANERR_SHIFT) |
| #define I40E_GLPES_VFTCPRTXSEG(_i) (0x0001B600 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFTCPRTXSEG_MAX_INDEX 31 |
| #define I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_SHIFT 0 |
| #define I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_MASK (0xFFFFFFFF << I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_SHIFT) |
| #define I40E_GLPES_VFTCPRXOPTERR(_i) (0x0001B200 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFTCPRXOPTERR_MAX_INDEX 31 |
| #define I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_SHIFT 0 |
| #define I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_MASK (0xFFFFFF << I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_SHIFT) |
| #define I40E_GLPES_VFTCPRXPROTOERR(_i) (0x0001B300 + ((_i) * 4)) |
| #define I40E_GLPES_VFTCPRXPROTOERR_MAX_INDEX 31 |
| #define I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT 0 |
| #define I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_MASK (0xFFFFFF << I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT) |
| #define I40E_GLPES_VFTCPRXSEGSHI(_i) (0x0001B004 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFTCPRXSEGSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT 0 |
| #define I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_MASK (0xFFFF << I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT) |
| #define I40E_GLPES_VFTCPRXSEGSLO(_i) (0x0001B000 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFTCPRXSEGSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT 0 |
| #define I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT) |
| #define I40E_GLPES_VFTCPTXSEGHI(_i) (0x0001B404 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFTCPTXSEGHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_SHIFT 0 |
| #define I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_MASK (0xFFFF << I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_SHIFT) |
| #define I40E_GLPES_VFTCPTXSEGLO(_i) (0x0001B400 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFTCPTXSEGLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_SHIFT 0 |
| #define I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_MASK (0xFFFFFFFF << I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_SHIFT) |
| #define I40E_GLPES_VFUDPRXPKTSHI(_i) (0x0001B804 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFUDPRXPKTSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT 0 |
| #define I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT) |
| #define I40E_GLPES_VFUDPRXPKTSLO(_i) (0x0001B800 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFUDPRXPKTSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT 0 |
| #define I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT) |
| #define I40E_GLPES_VFUDPTXPKTSHI(_i) (0x0001BA04 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFUDPTXPKTSHI_MAX_INDEX 31 |
| #define I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT 0 |
| #define I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT) |
| #define I40E_GLPES_VFUDPTXPKTSLO(_i) (0x0001BA00 + ((_i) * 4)) /* _i=0...31 */ |
| #define I40E_GLPES_VFUDPTXPKTSLO_MAX_INDEX 31 |
| #define I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT 0 |
| #define I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT) |
| #define I40E_PRTPM_EEE_STAT 0x001E4320 |
| #define I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT 29 |
| #define I40E_PRTPM_EEE_STAT_EEE_NEG_MASK (0x1 << I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT) |
| #define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT 30 |
| #define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK (0x1 << I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT) |
| #define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT 31 |
| #define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK (0x1 << I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT) |
| #define I40E_PRTPM_EEEC 0x001E4380 |
| #define I40E_PRTPM_EEEC_TW_WAKE_MIN_SHIFT 16 |
| #define I40E_PRTPM_EEEC_TW_WAKE_MIN_MASK (0x3F << I40E_PRTPM_EEEC_TW_WAKE_MIN_SHIFT) |
| #define I40E_PRTPM_EEEC_TX_LU_LPI_DLY_SHIFT 24 |
| #define I40E_PRTPM_EEEC_TX_LU_LPI_DLY_MASK (0x3 << I40E_PRTPM_EEEC_TX_LU_LPI_DLY_SHIFT) |
| #define I40E_PRTPM_EEEC_TEEE_DLY_SHIFT 26 |
| #define I40E_PRTPM_EEEC_TEEE_DLY_MASK (0x3F << I40E_PRTPM_EEEC_TEEE_DLY_SHIFT) |
| #define I40E_PRTPM_EEEFWD 0x001E4400 |
| #define I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_SHIFT 31 |
| #define I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_MASK (0x1 << I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_SHIFT) |
| #define I40E_PRTPM_EEER 0x001E4360 |
| #define I40E_PRTPM_EEER_TW_SYSTEM_SHIFT 0 |
| #define I40E_PRTPM_EEER_TW_SYSTEM_MASK (0xFFFF << I40E_PRTPM_EEER_TW_SYSTEM_SHIFT) |
| #define I40E_PRTPM_EEER_TX_LPI_EN_SHIFT 16 |
| #define I40E_PRTPM_EEER_TX_LPI_EN_MASK (0x1 << I40E_PRTPM_EEER_TX_LPI_EN_SHIFT) |
| #define I40E_PRTPM_EEETXC 0x001E43E0 |
| #define I40E_PRTPM_EEETXC_TW_PHY_SHIFT 0 |
| #define I40E_PRTPM_EEETXC_TW_PHY_MASK (0xFFFF << I40E_PRTPM_EEETXC_TW_PHY_SHIFT) |
| #define I40E_PRTPM_GC 0x000B8140 |
| #define I40E_PRTPM_GC_EMP_LINK_ON_SHIFT 0 |
| #define I40E_PRTPM_GC_EMP_LINK_ON_MASK (0x1 << I40E_PRTPM_GC_EMP_LINK_ON_SHIFT) |
| #define I40E_PRTPM_GC_MNG_VETO_SHIFT 1 |
| #define I40E_PRTPM_GC_MNG_VETO_MASK (0x1 << I40E_PRTPM_GC_MNG_VETO_SHIFT) |
| #define I40E_PRTPM_GC_RATD_SHIFT 2 |
| #define I40E_PRTPM_GC_RATD_MASK (0x1 << I40E_PRTPM_GC_RATD_SHIFT) |
| #define I40E_PRTPM_GC_LCDMP_SHIFT 3 |
| #define I40E_PRTPM_GC_LCDMP_MASK (0x1 << I40E_PRTPM_GC_LCDMP_SHIFT) |
| #define I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT 31 |
| #define I40E_PRTPM_GC_LPLU_ASSERTED_MASK (0x1 << I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT) |
| #define I40E_PRTPM_RLPIC 0x001E43A0 |
| #define I40E_PRTPM_RLPIC_ERLPIC_SHIFT 0 |
| #define I40E_PRTPM_RLPIC_ERLPIC_MASK (0xFFFFFFFF << I40E_PRTPM_RLPIC_ERLPIC_SHIFT) |
| #define I40E_PRTPM_TLPIC 0x001E43C0 |
| #define I40E_PRTPM_TLPIC_ETLPIC_SHIFT 0 |
| #define I40E_PRTPM_TLPIC_ETLPIC_MASK (0xFFFFFFFF << I40E_PRTPM_TLPIC_ETLPIC_SHIFT) |
| #define I40E_GLRPB_DPSS 0x000AC828 |
| #define I40E_GLRPB_DPSS_DPS_TCN_SHIFT 0 |
| #define I40E_GLRPB_DPSS_DPS_TCN_MASK (0xFFFFF << I40E_GLRPB_DPSS_DPS_TCN_SHIFT) |
| #define I40E_GLRPB_GHW 0x000AC830 |
| #define I40E_GLRPB_GHW_GHW_SHIFT 0 |
| #define I40E_GLRPB_GHW_GHW_MASK (0xFFFFF << I40E_GLRPB_GHW_GHW_SHIFT) |
| #define I40E_GLRPB_GLW 0x000AC834 |
| #define I40E_GLRPB_GLW_GLW_SHIFT 0 |
| #define I40E_GLRPB_GLW_GLW_MASK (0xFFFFF << I40E_GLRPB_GLW_GLW_SHIFT) |
| #define I40E_GLRPB_PHW 0x000AC844 |
| #define I40E_GLRPB_PHW_PHW_SHIFT 0 |
| #define I40E_GLRPB_PHW_PHW_MASK (0xFFFFF << I40E_GLRPB_PHW_PHW_SHIFT) |
| #define I40E_GLRPB_PLW 0x000AC848 |
| #define I40E_GLRPB_PLW_PLW_SHIFT 0 |
| #define I40E_GLRPB_PLW_PLW_MASK (0xFFFFF << I40E_GLRPB_PLW_PLW_SHIFT) |
| #define I40E_PRTRPB_DHW(_i) (0x000AC100 + ((_i) * 32)) /* _i=0...7 */ |
| #define I40E_PRTRPB_DHW_MAX_INDEX 7 |
| #define I40E_PRTRPB_DHW_DHW_TCN_SHIFT 0 |
| #define I40E_PRTRPB_DHW_DHW_TCN_MASK (0xFFFFF << I40E_PRTRPB_DHW_DHW_TCN_SHIFT) |
| #define I40E_PRTRPB_DLW(_i) (0x000AC220 + ((_i) * 32)) /* _i=0...7 */ |
| #define I40E_PRTRPB_DLW_MAX_INDEX 7 |
| #define I40E_PRTRPB_DLW_DLW_TCN_SHIFT 0 |
| #define I40E_PRTRPB_DLW_DLW_TCN_MASK (0xFFFFF << I40E_PRTRPB_DLW_DLW_TCN_SHIFT) |
| #define I40E_PRTRPB_DPS(_i) (0x000AC320 + ((_i) * 32)) /* _i=0...7 */ |
| #define I40E_PRTRPB_DPS_MAX_INDEX 7 |
| #define I40E_PRTRPB_DPS_DPS_TCN_SHIFT 0 |
| #define I40E_PRTRPB_DPS_DPS_TCN_MASK (0xFFFFF << I40E_PRTRPB_DPS_DPS_TCN_SHIFT) |
| #define I40E_PRTRPB_SHT(_i) (0x000AC480 + ((_i) * 32)) /* _i=0...7 */ |
| #define I40E_PRTRPB_SHT_MAX_INDEX 7 |
| #define I40E_PRTRPB_SHT_SHT_TCN_SHIFT 0 |
| #define I40E_PRTRPB_SHT_SHT_TCN_MASK (0xFFFFF << I40E_PRTRPB_SHT_SHT_TCN_SHIFT) |
| #define I40E_PRTRPB_SHW 0x000AC580 |
| #define I40E_PRTRPB_SHW_SHW_SHIFT 0 |
| #define I40E_PRTRPB_SHW_SHW_MASK (0xFFFFF << I40E_PRTRPB_SHW_SHW_SHIFT) |
| #define I40E_PRTRPB_SLT(_i) (0x000AC5A0 + ((_i) * 32)) /* _i=0...7 */ |
| #define I40E_PRTRPB_SLT_MAX_INDEX 7 |
| #define I40E_PRTRPB_SLT_SLT_TCN_SHIFT 0 |
| #define I40E_PRTRPB_SLT_SLT_TCN_MASK (0xFFFFF << I40E_PRTRPB_SLT_SLT_TCN_SHIFT) |
| #define I40E_PRTRPB_SLW 0x000AC6A0 |
| #define I40E_PRTRPB_SLW_SLW_SHIFT 0 |
| #define I40E_PRTRPB_SLW_SLW_MASK (0xFFFFF << I40E_PRTRPB_SLW_SLW_SHIFT) |
| #define I40E_PRTRPB_SPS 0x000AC7C0 |
| #define I40E_PRTRPB_SPS_SPS_SHIFT 0 |
| #define I40E_PRTRPB_SPS_SPS_MASK (0xFFFFF << I40E_PRTRPB_SPS_SPS_SHIFT) |
| #define I40E_GLQF_APBVT(_i) (0x00260000 + ((_i) * 4)) /* _i=0...2047 */ |
| #define I40E_GLQF_APBVT_MAX_INDEX 2047 |
| #define I40E_GLQF_APBVT_APBVT_SHIFT 0 |
| #define I40E_GLQF_APBVT_APBVT_MASK (0xFFFFFFFF << I40E_GLQF_APBVT_APBVT_SHIFT) |
| #define I40E_GLQF_CTL 0x00269BA4 |
| #define I40E_GLQF_CTL_HTOEP_SHIFT 1 |
| #define I40E_GLQF_CTL_HTOEP_MASK (0x1 << I40E_GLQF_CTL_HTOEP_SHIFT) |
| #define I40E_GLQF_CTL_HTOEP_FCOE_SHIFT 2 |
| #define I40E_GLQF_CTL_HTOEP_FCOE_MASK (0x1 << I40E_GLQF_CTL_HTOEP_FCOE_SHIFT) |
| #define I40E_GLQF_CTL_PCNT_ALLOC_SHIFT 3 |
| #define I40E_GLQF_CTL_PCNT_ALLOC_MASK (0x7 << I40E_GLQF_CTL_PCNT_ALLOC_SHIFT) |
| #define I40E_GLQF_CTL_RSVD_SHIFT 7 |
| #define I40E_GLQF_CTL_RSVD_MASK (0x1 << I40E_GLQF_CTL_RSVD_SHIFT) |
| #define I40E_GLQF_CTL_MAXPEBLEN_SHIFT 8 |
| #define I40E_GLQF_CTL_MAXPEBLEN_MASK (0x7 << I40E_GLQF_CTL_MAXPEBLEN_SHIFT) |
| #define I40E_GLQF_CTL_MAXFCBLEN_SHIFT 11 |
| #define I40E_GLQF_CTL_MAXFCBLEN_MASK (0x7 << I40E_GLQF_CTL_MAXFCBLEN_SHIFT) |
| #define I40E_GLQF_CTL_MAXFDBLEN_SHIFT 14 |
| #define I40E_GLQF_CTL_MAXFDBLEN_MASK (0x7 << I40E_GLQF_CTL_MAXFDBLEN_SHIFT) |
| #define I40E_GLQF_CTL_FDBEST_SHIFT 17 |
| #define I40E_GLQF_CTL_FDBEST_MASK (0xFF << I40E_GLQF_CTL_FDBEST_SHIFT) |
| #define I40E_GLQF_CTL_PROGPRIO_SHIFT 25 |
| #define I40E_GLQF_CTL_PROGPRIO_MASK (0x1 << I40E_GLQF_CTL_PROGPRIO_SHIFT) |
| #define I40E_GLQF_CTL_INVALPRIO_SHIFT 26 |
| #define I40E_GLQF_CTL_INVALPRIO_MASK (0x1 << I40E_GLQF_CTL_INVALPRIO_SHIFT) |
| #define I40E_GLQF_CTL_IGNORE_IP_SHIFT 27 |
| #define I40E_GLQF_CTL_IGNORE_IP_MASK (0x1 << I40E_GLQF_CTL_IGNORE_IP_SHIFT) |
| #define I40E_GLQF_FDCNT_0 0x00269BAC |
| #define I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT 0 |
| #define I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK (0x1FFF << I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT) |
| #define I40E_GLQF_FDCNT_0_BESTCNT_SHIFT 13 |
| #define I40E_GLQF_FDCNT_0_BESTCNT_MASK (0x1FFF << I40E_GLQF_FDCNT_0_BESTCNT_SHIFT) |
| #define I40E_GLQF_HSYM(_i) (0x00269D00 + ((_i) * 4)) /* _i=0...63 */ |
| #define I40E_GLQF_HSYM_MAX_INDEX 63 |
| #define I40E_GLQF_HSYM_SYMH_ENA_SHIFT 0 |
| #define I40E_GLQF_HSYM_SYMH_ENA_MASK (0x1 << I40E_GLQF_HSYM_SYMH_ENA_SHIFT) |
| #define I40E_GLQF_PCNT(_i) (0x00266800 + ((_i) * 4)) /* _i=0...511 */ |
| #define I40E_GLQF_PCNT_MAX_INDEX 511 |
| #define I40E_GLQF_PCNT_PCNT_SHIFT 0 |
| #define I40E_GLQF_PCNT_PCNT_MASK (0xFFFFFFFF << I40E_GLQF_PCNT_PCNT_SHIFT) |
| #define I40E_GLQF_SWAP(_i, _j) (0x00267E00 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ |
| #define I40E_GLQF_SWAP_MAX_INDEX 1 |
| #define I40E_GLQF_SWAP_OFF0_SRC0_SHIFT 0 |
| #define I40E_GLQF_SWAP_OFF0_SRC0_MASK (0x3F << I40E_GLQF_SWAP_OFF0_SRC0_SHIFT) |
| #define I40E_GLQF_SWAP_OFF0_SRC1_SHIFT 6 |
| #define I40E_GLQF_SWAP_OFF0_SRC1_MASK (0x3F << I40E_GLQF_SWAP_OFF0_SRC1_SHIFT) |
| #define I40E_GLQF_SWAP_FLEN0_SHIFT 12 |
| #define I40E_GLQF_SWAP_FLEN0_MASK (0xF << I40E_GLQF_SWAP_FLEN0_SHIFT) |
| #define I40E_GLQF_SWAP_OFF1_SRC0_SHIFT 16 |
| #define I40E_GLQF_SWAP_OFF1_SRC0_MASK (0x3F << I40E_GLQF_SWAP_OFF1_SRC0_SHIFT) |
| #define I40E_GLQF_SWAP_OFF1_SRC1_SHIFT 22 |
| #define I40E_GLQF_SWAP_OFF1_SRC1_MASK (0x3F << I40E_GLQF_SWAP_OFF1_SRC1_SHIFT) |
| #define I40E_GLQF_SWAP_FLEN1_SHIFT 28 |
| #define I40E_GLQF_SWAP_FLEN1_MASK (0xF << I40E_GLQF_SWAP_FLEN1_SHIFT) |
| #define I40E_PFQF_CTL_0 0x001C0AC0 |
| #define I40E_PFQF_CTL_0_PEHSIZE_SHIFT 0 |
| #define I40E_PFQF_CTL_0_PEHSIZE_MASK (0x1F << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) |
| #define I40E_PFQF_CTL_0_PEDSIZE_SHIFT 5 |
| #define I40E_PFQF_CTL_0_PEDSIZE_MASK (0x1F << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) |
| #define I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT 10 |
| #define I40E_PFQF_CTL_0_PFFCHSIZE_MASK (0xF << I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) |
| #define I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT 14 |
| #define I40E_PFQF_CTL_0_PFFCDSIZE_MASK (0x3 << I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) |
| #define I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT 16 |
| #define I40E_PFQF_CTL_0_HASHLUTSIZE_MASK (0x1 << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) |
| #define I40E_PFQF_CTL_0_FD_ENA_SHIFT 17 |
| #define I40E_PFQF_CTL_0_FD_ENA_MASK (0x1 << I40E_PFQF_CTL_0_FD_ENA_SHIFT) |
| #define I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT 18 |
| #define I40E_PFQF_CTL_0_ETYPE_ENA_MASK (0x1 << I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT) |
| #define I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT 19 |
| #define I40E_PFQF_CTL_0_MACVLAN_ENA_MASK (0x1 << I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT) |
| #define I40E_PFQF_CTL_0_VFFCHSIZE_SHIFT 20 |
| #define I40E_PFQF_CTL_0_VFFCHSIZE_MASK (0xF << I40E_PFQF_CTL_0_VFFCHSIZE_SHIFT) |
| #define I40E_PFQF_CTL_0_VFFCDSIZE_SHIFT 24 |
| #define I40E_PFQF_CTL_0_VFFCDSIZE_MASK (0x3 << I40E_PFQF_CTL_0_VFFCDSIZE_SHIFT) |
| #define I40E_PFQF_CTL_1 0x00245D80 |
| #define I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT 0 |
| #define I40E_PFQF_CTL_1_CLEARFDTABLE_MASK (0x1 << I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT) |
| #define I40E_PFQF_FDALLOC 0x00246280 |
| #define I40E_PFQF_FDALLOC_FDALLOC_SHIFT 0 |
| #define I40E_PFQF_FDALLOC_FDALLOC_MASK (0xFF << I40E_PFQF_FDALLOC_FDALLOC_SHIFT) |
| #define I40E_PFQF_FDALLOC_FDBEST_SHIFT 8 |
| #define I40E_PFQF_FDALLOC_FDBEST_MASK (0xFF << I40E_PFQF_FDALLOC_FDBEST_SHIFT) |
| #define I40E_PFQF_FDSTAT 0x00246380 |
| #define I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT 0 |
| #define I40E_PFQF_FDSTAT_GUARANT_CNT_MASK (0x1FFF << I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT) |
| #define I40E_PFQF_FDSTAT_BEST_CNT_SHIFT 16 |
| #define I40E_PFQF_FDSTAT_BEST_CNT_MASK (0x1FFF << I40E_PFQF_FDSTAT_BEST_CNT_SHIFT) |
| #define I40E_PFQF_HENA(_i) (0x00245900 + ((_i) * 128)) /* _i=0...1 */ |
| #define I40E_PFQF_HENA_MAX_INDEX 1 |
| #define I40E_PFQF_HENA_PTYPE_ENA_SHIFT 0 |
| #define I40E_PFQF_HENA_PTYPE_ENA_MASK (0xFFFFFFFF << I40E_PFQF_HENA_PTYPE_ENA_SHIFT) |
| #define I40E_PFQF_HKEY(_i) (0x00244800 + ((_i) * 128)) /* _i=0...12 */ |
| #define I40E_PFQF_HKEY_MAX_INDEX 12 |
| #define I40E_PFQF_HKEY_KEY_0_SHIFT 0 |
| #define I40E_PFQF_HKEY_KEY_0_MASK (0xFF << I40E_PFQF_HKEY_KEY_0_SHIFT) |
| #define I40E_PFQF_HKEY_KEY_1_SHIFT 8 |
| #define I40E_PFQF_HKEY_KEY_1_MASK (0xFF << I40E_PFQF_HKEY_KEY_1_SHIFT) |
| #define I40E_PFQF_HKEY_KEY_2_SHIFT 16 |
| #define I40E_PFQF_HKEY_KEY_2_MASK (0xFF << I40E_PFQF_HKEY_KEY_2_SHIFT) |
| #define I40E_PFQF_HKEY_KEY_3_SHIFT 24 |
| #define I40E_PFQF_HKEY_KEY_3_MASK (0xFF << I40E_PFQF_HKEY_KEY_3_SHIFT) |
| #define I40E_PFQF_HLUT(_i) (0x00240000 + ((_i) * 128)) /* _i=0...127 */ |
| #define I40E_PFQF_HLUT_MAX_INDEX 127 |
| #define I40E_PFQF_HLUT_LUT0_SHIFT 0 |
| #define I40E_PFQF_HLUT_LUT0_MASK (0x3F << I40E_PFQF_HLUT_LUT0_SHIFT) |
| #define I40E_PFQF_HLUT_LUT1_SHIFT 8 |
| #define I40E_PFQF_HLUT_LUT1_MASK (0x3F << I40E_PFQF_HLUT_LUT1_SHIFT) |
| #define I40E_PFQF_HLUT_LUT2_SHIFT 16 |
| #define I40E_PFQF_HLUT_LUT2_MASK (0x3F << I40E_PFQF_HLUT_LUT2_SHIFT) |
| #define I40E_PFQF_HLUT_LUT3_SHIFT 24 |
| #define I40E_PFQF_HLUT_LUT3_MASK (0x3F << I40E_PFQF_HLUT_LUT3_SHIFT) |
| #define I40E_PFQF_HREGION(_i) (0x00245400 + ((_i) * 128)) /* _i=0...7 */ |
| #define I40E_PFQF_HREGION_MAX_INDEX 7 |
| #define I40E_PFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0 |
| #define I40E_PFQF_HREGION_OVERRIDE_ENA_0_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_0_SHIFT) |
| #define I40E_PFQF_HREGION_REGION_0_SHIFT 1 |
| #define I40E_PFQF_HREGION_REGION_0_MASK (0x7 << I40E_PFQF_HREGION_REGION_0_SHIFT) |
| #define I40E_PFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4 |
| #define I40E_PFQF_HREGION_OVERRIDE_ENA_1_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_1_SHIFT) |
| #define I40E_PFQF_HREGION_REGION_1_SHIFT 5 |
| #define I40E_PFQF_HREGION_REGION_1_MASK (0x7 << I40E_PFQF_HREGION_REGION_1_SHIFT) |
| #define I40E_PFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8 |
| #define I40E_PFQF_HREGION_OVERRIDE_ENA_2_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_2_SHIFT) |
| #define I40E_PFQF_HREGION_REGION_2_SHIFT 9 |
| #define I40E_PFQF_HREGION_REGION_2_MASK (0x7 << I40E_PFQF_HREGION_REGION_2_SHIFT) |
| #define I40E_PFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12 |
| #define I40E_PFQF_HREGION_OVERRIDE_ENA_3_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_3_SHIFT) |
| #define I40E_PFQF_HREGION_REGION_3_SHIFT 13 |
| #define I40E_PFQF_HREGION_REGION_3_MASK (0x7 << I40E_PFQF_HREGION_REGION_3_SHIFT) |
| #define I40E_PFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16 |
| #define I40E_PFQF_HREGION_OVERRIDE_ENA_4_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_4_SHIFT) |
| #define I40E_PFQF_HREGION_REGION_4_SHIFT 17 |
| #define I40E_PFQF_HREGION_REGION_4_MASK (0x7 << I40E_PFQF_HREGION_REGION_4_SHIFT) |
| #define I40E_PFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20 |
| #define I40E_PFQF_HREGION_OVERRIDE_ENA_5_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_5_SHIFT) |
| #define I40E_PFQF_HREGION_REGION_5_SHIFT 21 |
| #define I40E_PFQF_HREGION_REGION_5_MASK (0x7 << I40E_PFQF_HREGION_REGION_5_SHIFT) |
| #define I40E_PFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24 |
| #define I40E_PFQF_HREGION_OVERRIDE_ENA_6_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_6_SHIFT) |
| #define I40E_PFQF_HREGION_REGION_6_SHIFT 25 |
| #define I40E_PFQF_HREGION_REGION_6_MASK (0x7 << I40E_PFQF_HREGION_REGION_6_SHIFT) |
| #define I40E_PFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28 |
| #define I40E_PFQF_HREGION_OVERRIDE_ENA_7_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_7_SHIFT) |
| #define I40E_PFQF_HREGION_REGION_7_SHIFT 29 |
| #define I40E_PFQF_HREGION_REGION_7_MASK (0x7 << I40E_PFQF_HREGION_REGION_7_SHIFT) |
| #define I40E_PRTQF_CTL_0 0x00256E60 |
| #define I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT 0 |
| #define I40E_PRTQF_CTL_0_HSYM_ENA_MASK (0x1 << I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT) |
| #define I40E_PRTQF_FD_FLXINSET(_i) (0x00253800 + ((_i) * 32)) /* _i=0...63 */ |
| #define I40E_PRTQF_FD_FLXINSET_MAX_INDEX 63 |
| #define I40E_PRTQF_FD_FLXINSET_INSET_SHIFT 0 |
| #define I40E_PRTQF_FD_FLXINSET_INSET_MASK (0xFF << I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) |
| #define I40E_PRTQF_FD_MSK(_i, _j) (0x00252000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ |
| #define I40E_PRTQF_FD_MSK_MAX_INDEX 63 |
| #define I40E_PRTQF_FD_MSK_MASK_SHIFT 0 |
| #define I40E_PRTQF_FD_MSK_MASK_MASK (0xFFFF << I40E_PRTQF_FD_MSK_MASK_SHIFT) |
| #define I40E_PRTQF_FD_MSK_OFFSET_SHIFT 16 |
| #define I40E_PRTQF_FD_MSK_OFFSET_MASK (0x3F << I40E_PRTQF_FD_MSK_OFFSET_SHIFT) |
| #define I40E_PRTQF_FLX_PIT(_i) (0x00255200 + ((_i) * 32)) /* _i=0...8 */ |
| #define I40E_PRTQF_FLX_PIT_MAX_INDEX 8 |
| #define I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT 0 |
| #define I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK (0x1F << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) |
| #define I40E_PRTQF_FLX_PIT_FSIZE_SHIFT 5 |
| #define I40E_PRTQF_FLX_PIT_FSIZE_MASK (0x1F << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) |
| #define I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT 10 |
| #define I40E_PRTQF_FLX_PIT_DEST_OFF_MASK (0x3F << I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) |
| #define I40E_VFQF_HENA1(_i, _VF) (0x00230800 + ((_i) * 1024 + (_VF) * 4)) |
| #define I40E_VFQF_HENA1_MAX_INDEX 1 |
| #define I40E_VFQF_HENA1_PTYPE_ENA_SHIFT 0 |
| #define I40E_VFQF_HENA1_PTYPE_ENA_MASK (0xFFFFFFFF << I40E_VFQF_HENA1_PTYPE_ENA_SHIFT) |
| #define I40E_VFQF_HKEY1(_i, _VF) (0x00228000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...12, _VF=0...127 */ |
| #define I40E_VFQF_HKEY1_MAX_INDEX 12 |
| #define I40E_VFQF_HKEY1_KEY_0_SHIFT 0 |
| #define I40E_VFQF_HKEY1_KEY_0_MASK (0xFF << I40E_VFQF_HKEY1_KEY_0_SHIFT) |
| #define I40E_VFQF_HKEY1_KEY_1_SHIFT 8 |
| #define I40E_VFQF_HKEY1_KEY_1_MASK (0xFF << I40E_VFQF_HKEY1_KEY_1_SHIFT) |
| #define I40E_VFQF_HKEY1_KEY_2_SHIFT 16 |
| #define I40E_VFQF_HKEY1_KEY_2_MASK (0xFF << I40E_VFQF_HKEY1_KEY_2_SHIFT) |
| #define I40E_VFQF_HKEY1_KEY_3_SHIFT 24 |
| #define I40E_VFQF_HKEY1_KEY_3_MASK (0xFF << I40E_VFQF_HKEY1_KEY_3_SHIFT) |
| #define I40E_VFQF_HLUT1(_i, _VF) (0x00220000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ |
| #define I40E_VFQF_HLUT1_MAX_INDEX 15 |
| #define I40E_VFQF_HLUT1_LUT0_SHIFT 0 |
| #define I40E_VFQF_HLUT1_LUT0_MASK (0xF << I40E_VFQF_HLUT1_LUT0_SHIFT) |
| #define I40E_VFQF_HLUT1_LUT1_SHIFT 8 |
| #define I40E_VFQF_HLUT1_LUT1_MASK (0xF << I40E_VFQF_HLUT1_LUT1_SHIFT) |
| #define I40E_VFQF_HLUT1_LUT2_SHIFT 16 |
| #define I40E_VFQF_HLUT1_LUT2_MASK (0xF << I40E_VFQF_HLUT1_LUT2_SHIFT) |
| #define I40E_VFQF_HLUT1_LUT3_SHIFT 24 |
| #define I40E_VFQF_HLUT1_LUT3_MASK (0xF << I40E_VFQF_HLUT1_LUT3_SHIFT) |
| #define I40E_VFQF_HREGION1(_i, _VF) (0x0022E000 + ((_i) * 1024 + (_VF) * 4)) |
| #define I40E_VFQF_HREGION1_MAX_INDEX 7 |
| #define I40E_VFQF_HREGION1_OVERRIDE_ENA_0_SHIFT 0 |
| #define I40E_VFQF_HREGION1_OVERRIDE_ENA_0_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_0_SHIFT) |
| #define I40E_VFQF_HREGION1_REGION_0_SHIFT 1 |
| #define I40E_VFQF_HREGION1_REGION_0_MASK (0x7 << I40E_VFQF_HREGION1_REGION_0_SHIFT) |
| #define I40E_VFQF_HREGION1_OVERRIDE_ENA_1_SHIFT 4 |
| #define I40E_VFQF_HREGION1_OVERRIDE_ENA_1_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_1_SHIFT) |
| #define I40E_VFQF_HREGION1_REGION_1_SHIFT 5 |
| #define I40E_VFQF_HREGION1_REGION_1_MASK (0x7 << I40E_VFQF_HREGION1_REGION_1_SHIFT) |
| #define I40E_VFQF_HREGION1_OVERRIDE_ENA_2_SHIFT 8 |
| #define I40E_VFQF_HREGION1_OVERRIDE_ENA_2_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_2_SHIFT) |
| #define I40E_VFQF_HREGION1_REGION_2_SHIFT 9 |
| #define I40E_VFQF_HREGION1_REGION_2_MASK (0x7 << I40E_VFQF_HREGION1_REGION_2_SHIFT) |
| #define I40E_VFQF_HREGION1_OVERRIDE_ENA_3_SHIFT 12 |
| #define I40E_VFQF_HREGION1_OVERRIDE_ENA_3_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_3_SHIFT) |
| #define I40E_VFQF_HREGION1_REGION_3_SHIFT 13 |
| #define I40E_VFQF_HREGION1_REGION_3_MASK (0x7 << I40E_VFQF_HREGION1_REGION_3_SHIFT) |
| #define I40E_VFQF_HREGION1_OVERRIDE_ENA_4_SHIFT 16 |
| #define I40E_VFQF_HREGION1_OVERRIDE_ENA_4_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_4_SHIFT) |
| #define I40E_VFQF_HREGION1_REGION_4_SHIFT 17 |
| #define I40E_VFQF_HREGION1_REGION_4_MASK (0x7 << I40E_VFQF_HREGION1_REGION_4_SHIFT) |
| #define I40E_VFQF_HREGION1_OVERRIDE_ENA_5_SHIFT 20 |
| #define I40E_VFQF_HREGION1_OVERRIDE_ENA_5_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_5_SHIFT) |
| #define I40E_VFQF_HREGION1_REGION_5_SHIFT 21 |
| #define I40E_VFQF_HREGION1_REGION_5_MASK (0x7 << I40E_VFQF_HREGION1_REGION_5_SHIFT) |
| #define I40E_VFQF_HREGION1_OVERRIDE_ENA_6_SHIFT 24 |
| #define I40E_VFQF_HREGION1_OVERRIDE_ENA_6_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_6_SHIFT) |
| #define I40E_VFQF_HREGION1_REGION_6_SHIFT 25 |
| #define I40E_VFQF_HREGION1_REGION_6_MASK (0x7 << I40E_VFQF_HREGION1_REGION_6_SHIFT) |
| #define I40E_VFQF_HREGION1_OVERRIDE_ENA_7_SHIFT 28 |
| #define I40E_VFQF_HREGION1_OVERRIDE_ENA_7_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_7_SHIFT) |
| #define I40E_VFQF_HREGION1_REGION_7_SHIFT 29 |
| #define I40E_VFQF_HREGION1_REGION_7_MASK (0x7 << I40E_VFQF_HREGION1_REGION_7_SHIFT) |
| #define I40E_VPQF_CTL(_VF) (0x001C0000 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VPQF_CTL_MAX_INDEX 127 |
| #define I40E_VPQF_CTL_PEHSIZE_SHIFT 0 |
| #define I40E_VPQF_CTL_PEHSIZE_MASK (0x1F << I40E_VPQF_CTL_PEHSIZE_SHIFT) |
| #define I40E_VPQF_CTL_PEDSIZE_SHIFT 5 |
| #define I40E_VPQF_CTL_PEDSIZE_MASK (0x1F << I40E_VPQF_CTL_PEDSIZE_SHIFT) |
| #define I40E_VPQF_CTL_FCHSIZE_SHIFT 10 |
| #define I40E_VPQF_CTL_FCHSIZE_MASK (0xF << I40E_VPQF_CTL_FCHSIZE_SHIFT) |
| #define I40E_VPQF_CTL_FCDSIZE_SHIFT 14 |
| #define I40E_VPQF_CTL_FCDSIZE_MASK (0x3 << I40E_VPQF_CTL_FCDSIZE_SHIFT) |
| #define I40E_VSIQF_CTL(_VSI) (0x0020D800 + ((_VSI) * 4)) /* _i=0...383 */ |
| #define I40E_VSIQF_CTL_MAX_INDEX 383 |
| #define I40E_VSIQF_CTL_FCOE_ENA_SHIFT 0 |
| #define I40E_VSIQF_CTL_FCOE_ENA_MASK (0x1 << I40E_VSIQF_CTL_FCOE_ENA_SHIFT) |
| #define I40E_VSIQF_CTL_PETCP_ENA_SHIFT 1 |
| #define I40E_VSIQF_CTL_PETCP_ENA_MASK (0x1 << I40E_VSIQF_CTL_PETCP_ENA_SHIFT) |
| #define I40E_VSIQF_CTL_PEUUDP_ENA_SHIFT 2 |
| #define I40E_VSIQF_CTL_PEUUDP_ENA_MASK (0x1 << I40E_VSIQF_CTL_PEUUDP_ENA_SHIFT) |
| #define I40E_VSIQF_CTL_PEMUDP_ENA_SHIFT 3 |
| #define I40E_VSIQF_CTL_PEMUDP_ENA_MASK (0x1 << I40E_VSIQF_CTL_PEMUDP_ENA_SHIFT) |
| #define I40E_VSIQF_CTL_PEUFRAG_ENA_SHIFT 4 |
| #define I40E_VSIQF_CTL_PEUFRAG_ENA_MASK (0x1 << I40E_VSIQF_CTL_PEUFRAG_ENA_SHIFT) |
| #define I40E_VSIQF_CTL_PEMFRAG_ENA_SHIFT 5 |
| #define I40E_VSIQF_CTL_PEMFRAG_ENA_MASK (0x1 << I40E_VSIQF_CTL_PEMFRAG_ENA_SHIFT) |
| #define I40E_VSIQF_TCREGION(_i, _VSI) (0x00206000 + ((_i) * 2048 + (_VSI) * 4)) |
| #define I40E_VSIQF_TCREGION_MAX_INDEX 3 |
| #define I40E_VSIQF_TCREGION_TC_OFFSET_SHIFT 0 |
| #define I40E_VSIQF_TCREGION_TC_OFFSET_MASK (0x1FF << I40E_VSIQF_TCREGION_TC_OFFSET_SHIFT) |
| #define I40E_VSIQF_TCREGION_TC_SIZE_SHIFT 9 |
| #define I40E_VSIQF_TCREGION_TC_SIZE_MASK (0x7 << I40E_VSIQF_TCREGION_TC_SIZE_SHIFT) |
| #define I40E_VSIQF_TCREGION_TC_OFFSET2_SHIFT 16 |
| #define I40E_VSIQF_TCREGION_TC_OFFSET2_MASK (0x1FF << I40E_VSIQF_TCREGION_TC_OFFSET2_SHIFT) |
| #define I40E_VSIQF_TCREGION_TC_SIZE2_SHIFT 25 |
| #define I40E_VSIQF_TCREGION_TC_SIZE2_MASK (0x7 << I40E_VSIQF_TCREGION_TC_SIZE2_SHIFT) |
| #define I40E_GL_FCOECRC(_i) (0x00314d80 + ((_i) * 8)) /* _i=0...143 */ |
| #define I40E_GL_FCOECRC_MAX_INDEX 143 |
| #define I40E_GL_FCOECRC_FCOECRC_SHIFT 0 |
| #define I40E_GL_FCOECRC_FCOECRC_MASK (0xFFFFFFFF << I40E_GL_FCOECRC_FCOECRC_SHIFT) |
| #define I40E_GL_FCOEDDPC(_i) (0x00314480 + ((_i) * 8)) /* _i=0...143 */ |
| #define I40E_GL_FCOEDDPC_MAX_INDEX 143 |
| #define I40E_GL_FCOEDDPC_FCOEDDPC_SHIFT 0 |
| #define I40E_GL_FCOEDDPC_FCOEDDPC_MASK (0xFFFFFFFF << I40E_GL_FCOEDDPC_FCOEDDPC_SHIFT) |
| /* _i=0...143 */ |
| #define I40E_GL_FCOEDIFEC(_i) (0x00318480 + ((_i) * 8)) /* _i=0...143 */ |
| #define I40E_GL_FCOEDIFEC_MAX_INDEX 143 |
| #define I40E_GL_FCOEDIFEC_FCOEDIFRC_SHIFT 0 |
| #define I40E_GL_FCOEDIFEC_FCOEDIFRC_MASK (0xFFFFFFFF << I40E_GL_FCOEDIFEC_FCOEDIFRC_SHIFT) |
| #define I40E_GL_FCOEDIFRC(_i) (0x00318000 + ((_i) * 8)) /* _i=0...143 */ |
| #define I40E_GL_FCOEDIFRC_MAX_INDEX 143 |
| #define I40E_GL_FCOEDIFRC_FCOEDIFRC_SHIFT 0 |
| #define I40E_GL_FCOEDIFRC_FCOEDIFRC_MASK (0xFFFFFFFF << I40E_GL_FCOEDIFRC_FCOEDIFRC_SHIFT) |
| #define I40E_GL_FCOEDIFTCL(_i) (0x00354000 + ((_i) * 8)) /* _i=0...143 */ |
| #define I40E_GL_FCOEDIFTCL_MAX_INDEX 143 |
| #define I40E_GL_FCOEDIFTCL_FCOEDIFTC_SHIFT 0 |
| #define I40E_GL_FCOEDIFTCL_FCOEDIFTC_MASK (0xFFFFFFFF << I40E_GL_FCOEDIFTCL_FCOEDIFTC_SHIFT) |
| #define I40E_GL_FCOEDIXAC(_i) (0x0031c000 + ((_i) * 8)) /* _i=0...143 */ |
| #define I40E_GL_FCOEDIXAC_MAX_INDEX 143 |
| #define I40E_GL_FCOEDIXAC_FCOEDIXAC_SHIFT 0 |
| #define I40E_GL_FCOEDIXAC_FCOEDIXAC_MASK (0xFFFFFFFF << I40E_GL_FCOEDIXAC_FCOEDIXAC_SHIFT) |
| #define I40E_GL_FCOEDIXEC(_i) (0x0034c000 + ((_i) * 8)) /* _i=0...143 */ |
| #define I40E_GL_FCOEDIXEC_MAX_INDEX 143 |
| #define I40E_GL_FCOEDIXEC_FCOEDIXEC_SHIFT 0 |
| #define I40E_GL_FCOEDIXEC_FCOEDIXEC_MASK (0xFFFFFFFF << I40E_GL_FCOEDIXEC_FCOEDIXEC_SHIFT) |
| #define I40E_GL_FCOEDIXVC(_i) (0x00350000 + ((_i) * 8)) /* _i=0...143 */ |
| #define I40E_GL_FCOEDIXVC_MAX_INDEX 143 |
| #define I40E_GL_FCOEDIXVC_FCOEDIXVC_SHIFT 0 |
| #define I40E_GL_FCOEDIXVC_FCOEDIXVC_MASK (0xFFFFFFFF << I40E_GL_FCOEDIXVC_FCOEDIXVC_SHIFT) |
| #define I40E_GL_FCOEDWRCH(_i) (0x00320004 + ((_i) * 8)) /* _i=0...143 */ |
| #define I40E_GL_FCOEDWRCH_MAX_INDEX 143 |
| #define I40E_GL_FCOEDWRCH_FCOEDWRCH_SHIFT 0 |
| #define I40E_GL_FCOEDWRCH_FCOEDWRCH_MASK (0xFFFF << I40E_GL_FCOEDWRCH_FCOEDWRCH_SHIFT) |
| #define I40E_GL_FCOEDWRCL(_i) (0x00320000 + ((_i) * 8)) /* _i=0...143 */ |
| #define I40E_GL_FCOEDWRCL_MAX_INDEX 143 |
| #define I40E_GL_FCOEDWRCL_FCOEDWRCL_SHIFT 0 |
| #define I40E_GL_FCOEDWRCL_FCOEDWRCL_MASK (0xFFFFFFFF << I40E_GL_FCOEDWRCL_FCOEDWRCL_SHIFT) |
| #define I40E_GL_FCOEDWTCH(_i) (0x00348084 + ((_i) * 8)) /* _i=0...143 */ |
| #define I40E_GL_FCOEDWTCH_MAX_INDEX 143 |
| #define I40E_GL_FCOEDWTCH_FCOEDWTCH_SHIFT 0 |
| #define I40E_GL_FCOEDWTCH_FCOEDWTCH_MASK (0xFFFF << I40E_GL_FCOEDWTCH_FCOEDWTCH_SHIFT) |
| #define I40E_GL_FCOEDWTCL(_i) (0x00348080 + ((_i) * 8)) /* _i=0...143 */ |
| #define I40E_GL_FCOEDWTCL_MAX_INDEX 143 |
| #define I40E_GL_FCOEDWTCL_FCOEDWTCL_SHIFT 0 |
| #define I40E_GL_FCOEDWTCL_FCOEDWTCL_MASK (0xFFFFFFFF << I40E_GL_FCOEDWTCL_FCOEDWTCL_SHIFT) |
| #define I40E_GL_FCOELAST(_i) (0x00314000 + ((_i) * 8)) /* _i=0...143 */ |
| #define I40E_GL_FCOELAST_MAX_INDEX 143 |
| #define I40E_GL_FCOELAST_FCOELAST_SHIFT 0 |
| #define I40E_GL_FCOELAST_FCOELAST_MASK (0xFFFFFFFF << I40E_GL_FCOELAST_FCOELAST_SHIFT) |
| #define I40E_GL_FCOEPRC(_i) (0x00315200 + ((_i) * 8)) /* _i=0...143 */ |
| #define I40E_GL_FCOEPRC_MAX_INDEX 143 |
| #define I40E_GL_FCOEPRC_FCOEPRC_SHIFT 0 |
| #define I40E_GL_FCOEPRC_FCOEPRC_MASK (0xFFFFFFFF << I40E_GL_FCOEPRC_FCOEPRC_SHIFT) |
| #define I40E_GL_FCOEPTC(_i) (0x00344C00 + ((_i) * 8)) /* _i=0...143 */ |
| #define I40E_GL_FCOEPTC_MAX_INDEX 143 |
| #define I40E_GL_FCOEPTC_FCOEPTC_SHIFT 0 |
| #define I40E_GL_FCOEPTC_FCOEPTC_MASK (0xFFFFFFFF << I40E_GL_FCOEPTC_FCOEPTC_SHIFT) |
| #define I40E_GL_FCOERPDC(_i) (0x00324000 + ((_i) * 8)) /* _i=0...143 */ |
| #define I40E_GL_FCOERPDC_MAX_INDEX 143 |
| #define I40E_GL_FCOERPDC_FCOERPDC_SHIFT 0 |
| #define I40E_GL_FCOERPDC_FCOERPDC_MASK (0xFFFFFFFF << I40E_GL_FCOERPDC_FCOERPDC_SHIFT) |
| #define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_BPRCH_MAX_INDEX 3 |
| #define I40E_GLPRT_BPRCH_UPRCH_SHIFT 0 |
| #define I40E_GLPRT_BPRCH_UPRCH_MASK (0xFFFF << I40E_GLPRT_BPRCH_UPRCH_SHIFT) |
| #define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_BPRCL_MAX_INDEX 3 |
| #define I40E_GLPRT_BPRCL_UPRCH_SHIFT 0 |
| #define I40E_GLPRT_BPRCL_UPRCH_MASK (0xFFFFFFFF << I40E_GLPRT_BPRCL_UPRCH_SHIFT) |
| #define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_BPTCH_MAX_INDEX 3 |
| #define I40E_GLPRT_BPTCH_UPRCH_SHIFT 0 |
| #define I40E_GLPRT_BPTCH_UPRCH_MASK (0xFFFF << I40E_GLPRT_BPTCH_UPRCH_SHIFT) |
| #define I40E_GLPRT_BPTCL(_i) (0x00300A00 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_BPTCL_MAX_INDEX 3 |
| #define I40E_GLPRT_BPTCL_UPRCH_SHIFT 0 |
| #define I40E_GLPRT_BPTCL_UPRCH_MASK (0xFFFFFFFF << I40E_GLPRT_BPTCL_UPRCH_SHIFT) |
| #define I40E_GLPRT_CRCERRS(_i) (0x00300080 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_CRCERRS_MAX_INDEX 3 |
| #define I40E_GLPRT_CRCERRS_CRCERRS_SHIFT 0 |
| #define I40E_GLPRT_CRCERRS_CRCERRS_MASK (0xFFFFFFFF << I40E_GLPRT_CRCERRS_CRCERRS_SHIFT) |
| #define I40E_GLPRT_GORCH(_i) (0x00300004 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_GORCH_MAX_INDEX 3 |
| #define I40E_GLPRT_GORCH_GORCH_SHIFT 0 |
| #define I40E_GLPRT_GORCH_GORCH_MASK (0xFFFF << I40E_GLPRT_GORCH_GORCH_SHIFT) |
| #define I40E_GLPRT_GORCL(_i) (0x00300000 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_GORCL_MAX_INDEX 3 |
| #define I40E_GLPRT_GORCL_GORCL_SHIFT 0 |
| #define I40E_GLPRT_GORCL_GORCL_MASK (0xFFFFFFFF << I40E_GLPRT_GORCL_GORCL_SHIFT) |
| #define I40E_GLPRT_GOTCH(_i) (0x00300684 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_GOTCH_MAX_INDEX 3 |
| #define I40E_GLPRT_GOTCH_GOTCH_SHIFT 0 |
| #define I40E_GLPRT_GOTCH_GOTCH_MASK (0xFFFF << I40E_GLPRT_GOTCH_GOTCH_SHIFT) |
| #define I40E_GLPRT_GOTCL(_i) (0x00300680 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_GOTCL_MAX_INDEX 3 |
| #define I40E_GLPRT_GOTCL_GOTCL_SHIFT 0 |
| #define I40E_GLPRT_GOTCL_GOTCL_MASK (0xFFFFFFFF << I40E_GLPRT_GOTCL_GOTCL_SHIFT) |
| #define I40E_GLPRT_ILLERRC(_i) (0x003000E0 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_ILLERRC_MAX_INDEX 3 |
| #define I40E_GLPRT_ILLERRC_ILLERRC_SHIFT 0 |
| #define I40E_GLPRT_ILLERRC_ILLERRC_MASK (0xFFFFFFFF << I40E_GLPRT_ILLERRC_ILLERRC_SHIFT) |
| #define I40E_GLPRT_LDPC(_i) (0x00300620 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_LDPC_MAX_INDEX 3 |
| #define I40E_GLPRT_LDPC_LDPC_SHIFT 0 |
| #define I40E_GLPRT_LDPC_LDPC_MASK (0xFFFFFFFF << I40E_GLPRT_LDPC_LDPC_SHIFT) |
| #define I40E_GLPRT_LXOFFRXC(_i) (0x00300160 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_LXOFFRXC_MAX_INDEX 3 |
| #define I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_SHIFT 0 |
| #define I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_MASK (0xFFFFFFFF << I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_SHIFT) |
| #define I40E_GLPRT_LXOFFTXC(_i) (0x003009A0 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_LXOFFTXC_MAX_INDEX 3 |
| #define I40E_GLPRT_LXOFFTXC_LXOFFTXC_SHIFT 0 |
| #define I40E_GLPRT_LXOFFTXC_LXOFFTXC_MASK (0xFFFFFFFF << I40E_GLPRT_LXOFFTXC_LXOFFTXC_SHIFT) |
| #define I40E_GLPRT_LXONRXC(_i) (0x00300140 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_LXONRXC_MAX_INDEX 3 |
| #define I40E_GLPRT_LXONRXC_LXONRXCNT_SHIFT 0 |
| #define I40E_GLPRT_LXONRXC_LXONRXCNT_MASK (0xFFFFFFFF << I40E_GLPRT_LXONRXC_LXONRXCNT_SHIFT) |
| #define I40E_GLPRT_LXONTXC(_i) (0x00300980 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_LXONTXC_MAX_INDEX 3 |
| #define I40E_GLPRT_LXONTXC_LXONTXC_SHIFT 0 |
| #define I40E_GLPRT_LXONTXC_LXONTXC_MASK (0xFFFFFFFF << I40E_GLPRT_LXONTXC_LXONTXC_SHIFT) |
| #define I40E_GLPRT_MLFC(_i) (0x00300020 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_MLFC_MAX_INDEX 3 |
| #define I40E_GLPRT_MLFC_MLFC_SHIFT 0 |
| #define I40E_GLPRT_MLFC_MLFC_MASK (0xFFFFFFFF << I40E_GLPRT_MLFC_MLFC_SHIFT) |
| #define I40E_GLPRT_MPRCH(_i) (0x003005C4 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_MPRCH_MAX_INDEX 3 |
| #define I40E_GLPRT_MPRCH_MPRCH_SHIFT 0 |
| #define I40E_GLPRT_MPRCH_MPRCH_MASK (0xFFFF << I40E_GLPRT_MPRCH_MPRCH_SHIFT) |
| #define I40E_GLPRT_MPRCL(_i) (0x003005C0 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_MPRCL_MAX_INDEX 3 |
| #define I40E_GLPRT_MPRCL_MPRCL_SHIFT 0 |
| #define I40E_GLPRT_MPRCL_MPRCL_MASK (0xFFFFFFFF << I40E_GLPRT_MPRCL_MPRCL_SHIFT) |
| #define I40E_GLPRT_MPTCH(_i) (0x003009E4 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_MPTCH_MAX_INDEX 3 |
| #define I40E_GLPRT_MPTCH_MPTCH_SHIFT 0 |
| #define I40E_GLPRT_MPTCH_MPTCH_MASK (0xFFFF << I40E_GLPRT_MPTCH_MPTCH_SHIFT) |
| #define I40E_GLPRT_MPTCL(_i) (0x003009E0 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_MPTCL_MAX_INDEX 3 |
| #define I40E_GLPRT_MPTCL_MPTCL_SHIFT 0 |
| #define I40E_GLPRT_MPTCL_MPTCL_MASK (0xFFFFFFFF << I40E_GLPRT_MPTCL_MPTCL_SHIFT) |
| #define I40E_GLPRT_MRFC(_i) (0x00300040 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_MRFC_MAX_INDEX 3 |
| #define I40E_GLPRT_MRFC_MRFC_SHIFT 0 |
| #define I40E_GLPRT_MRFC_MRFC_MASK (0xFFFFFFFF << I40E_GLPRT_MRFC_MRFC_SHIFT) |
| #define I40E_GLPRT_PRC1023H(_i) (0x00300504 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PRC1023H_MAX_INDEX 3 |
| #define I40E_GLPRT_PRC1023H_PRC1023H_SHIFT 0 |
| #define I40E_GLPRT_PRC1023H_PRC1023H_MASK (0xFFFF << I40E_GLPRT_PRC1023H_PRC1023H_SHIFT) |
| #define I40E_GLPRT_PRC1023L(_i) (0x00300500 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PRC1023L_MAX_INDEX 3 |
| #define I40E_GLPRT_PRC1023L_PRC1023L_SHIFT 0 |
| #define I40E_GLPRT_PRC1023L_PRC1023L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC1023L_PRC1023L_SHIFT) |
| #define I40E_GLPRT_PRC127H(_i) (0x003004A4 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PRC127H_MAX_INDEX 3 |
| #define I40E_GLPRT_PRC127H_PRC127H_SHIFT 0 |
| #define I40E_GLPRT_PRC127H_PRC127H_MASK (0xFFFF << I40E_GLPRT_PRC127H_PRC127H_SHIFT) |
| #define I40E_GLPRT_PRC127L(_i) (0x003004A0 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PRC127L_MAX_INDEX 3 |
| #define I40E_GLPRT_PRC127L_PRC127L_SHIFT 0 |
| #define I40E_GLPRT_PRC127L_PRC127L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC127L_PRC127L_SHIFT) |
| #define I40E_GLPRT_PRC1522H(_i) (0x00300524 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PRC1522H_MAX_INDEX 3 |
| #define I40E_GLPRT_PRC1522H_PRC1522H_SHIFT 0 |
| #define I40E_GLPRT_PRC1522H_PRC1522H_MASK (0xFFFF << I40E_GLPRT_PRC1522H_PRC1522H_SHIFT) |
| #define I40E_GLPRT_PRC1522L(_i) (0x00300520 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PRC1522L_MAX_INDEX 3 |
| #define I40E_GLPRT_PRC1522L_PRC1522L_SHIFT 0 |
| #define I40E_GLPRT_PRC1522L_PRC1522L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC1522L_PRC1522L_SHIFT) |
| #define I40E_GLPRT_PRC255H(_i) (0x003004C4 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PRC255H_MAX_INDEX 3 |
| #define I40E_GLPRT_PRC255H_PRTPRC255H_SHIFT 0 |
| #define I40E_GLPRT_PRC255H_PRTPRC255H_MASK (0xFFFF << I40E_GLPRT_PRC255H_PRTPRC255H_SHIFT) |
| #define I40E_GLPRT_PRC255L(_i) (0x003004C0 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PRC255L_MAX_INDEX 3 |
| #define I40E_GLPRT_PRC255L_PRC255L_SHIFT 0 |
| #define I40E_GLPRT_PRC255L_PRC255L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC255L_PRC255L_SHIFT) |
| #define I40E_GLPRT_PRC511H(_i) (0x003004E4 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PRC511H_MAX_INDEX 3 |
| #define I40E_GLPRT_PRC511H_PRC511H_SHIFT 0 |
| #define I40E_GLPRT_PRC511H_PRC511H_MASK (0xFFFF << I40E_GLPRT_PRC511H_PRC511H_SHIFT) |
| #define I40E_GLPRT_PRC511L(_i) (0x003004E0 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PRC511L_MAX_INDEX 3 |
| #define I40E_GLPRT_PRC511L_PRC511L_SHIFT 0 |
| #define I40E_GLPRT_PRC511L_PRC511L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC511L_PRC511L_SHIFT) |
| #define I40E_GLPRT_PRC64H(_i) (0x00300484 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PRC64H_MAX_INDEX 3 |
| #define I40E_GLPRT_PRC64H_PRC64H_SHIFT 0 |
| #define I40E_GLPRT_PRC64H_PRC64H_MASK (0xFFFF << I40E_GLPRT_PRC64H_PRC64H_SHIFT) |
| #define I40E_GLPRT_PRC64L(_i) (0x00300480 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PRC64L_MAX_INDEX 3 |
| #define I40E_GLPRT_PRC64L_PRC64L_SHIFT 0 |
| #define I40E_GLPRT_PRC64L_PRC64L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC64L_PRC64L_SHIFT) |
| #define I40E_GLPRT_PRC9522H(_i) (0x00300544 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PRC9522H_MAX_INDEX 3 |
| #define I40E_GLPRT_PRC9522H_PRC1522H_SHIFT 0 |
| #define I40E_GLPRT_PRC9522H_PRC1522H_MASK (0xFFFF << I40E_GLPRT_PRC9522H_PRC1522H_SHIFT) |
| #define I40E_GLPRT_PRC9522L(_i) (0x00300540 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PRC9522L_MAX_INDEX 3 |
| #define I40E_GLPRT_PRC9522L_PRC1522L_SHIFT 0 |
| #define I40E_GLPRT_PRC9522L_PRC1522L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC9522L_PRC1522L_SHIFT) |
| #define I40E_GLPRT_PTC1023H(_i) (0x00300724 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PTC1023H_MAX_INDEX 3 |
| #define I40E_GLPRT_PTC1023H_PTC1023H_SHIFT 0 |
| #define I40E_GLPRT_PTC1023H_PTC1023H_MASK (0xFFFF << I40E_GLPRT_PTC1023H_PTC1023H_SHIFT) |
| #define I40E_GLPRT_PTC1023L(_i) (0x00300720 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PTC1023L_MAX_INDEX 3 |
| #define I40E_GLPRT_PTC1023L_PTC1023L_SHIFT 0 |
| #define I40E_GLPRT_PTC1023L_PTC1023L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC1023L_PTC1023L_SHIFT) |
| #define I40E_GLPRT_PTC127H(_i) (0x003006C4 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PTC127H_MAX_INDEX 3 |
| #define I40E_GLPRT_PTC127H_PTC127H_SHIFT 0 |
| #define I40E_GLPRT_PTC127H_PTC127H_MASK (0xFFFF << I40E_GLPRT_PTC127H_PTC127H_SHIFT) |
| #define I40E_GLPRT_PTC127L(_i) (0x003006C0 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PTC127L_MAX_INDEX 3 |
| #define I40E_GLPRT_PTC127L_PTC127L_SHIFT 0 |
| #define I40E_GLPRT_PTC127L_PTC127L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC127L_PTC127L_SHIFT) |
| #define I40E_GLPRT_PTC1522H(_i) (0x00300744 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PTC1522H_MAX_INDEX 3 |
| #define I40E_GLPRT_PTC1522H_PTC1522H_SHIFT 0 |
| #define I40E_GLPRT_PTC1522H_PTC1522H_MASK (0xFFFF << I40E_GLPRT_PTC1522H_PTC1522H_SHIFT) |
| #define I40E_GLPRT_PTC1522L(_i) (0x00300740 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PTC1522L_MAX_INDEX 3 |
| #define I40E_GLPRT_PTC1522L_PTC1522L_SHIFT 0 |
| #define I40E_GLPRT_PTC1522L_PTC1522L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC1522L_PTC1522L_SHIFT) |
| #define I40E_GLPRT_PTC255H(_i) (0x003006E4 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PTC255H_MAX_INDEX 3 |
| #define I40E_GLPRT_PTC255H_PTC255H_SHIFT 0 |
| #define I40E_GLPRT_PTC255H_PTC255H_MASK (0xFFFF << I40E_GLPRT_PTC255H_PTC255H_SHIFT) |
| #define I40E_GLPRT_PTC255L(_i) (0x003006E0 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PTC255L_MAX_INDEX 3 |
| #define I40E_GLPRT_PTC255L_PTC255L_SHIFT 0 |
| #define I40E_GLPRT_PTC255L_PTC255L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC255L_PTC255L_SHIFT) |
| #define I40E_GLPRT_PTC511H(_i) (0x00300704 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PTC511H_MAX_INDEX 3 |
| #define I40E_GLPRT_PTC511H_PTC511H_SHIFT 0 |
| #define I40E_GLPRT_PTC511H_PTC511H_MASK (0xFFFF << I40E_GLPRT_PTC511H_PTC511H_SHIFT) |
| #define I40E_GLPRT_PTC511L(_i) (0x00300700 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PTC511L_MAX_INDEX 3 |
| #define I40E_GLPRT_PTC511L_PTC511L_SHIFT 0 |
| #define I40E_GLPRT_PTC511L_PTC511L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC511L_PTC511L_SHIFT) |
| #define I40E_GLPRT_PTC64H(_i) (0x003006A4 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PTC64H_MAX_INDEX 3 |
| #define I40E_GLPRT_PTC64H_PTC64H_SHIFT 0 |
| #define I40E_GLPRT_PTC64H_PTC64H_MASK (0xFFFF << I40E_GLPRT_PTC64H_PTC64H_SHIFT) |
| #define I40E_GLPRT_PTC64L(_i) (0x003006A0 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PTC64L_MAX_INDEX 3 |
| #define I40E_GLPRT_PTC64L_PTC64L_SHIFT 0 |
| #define I40E_GLPRT_PTC64L_PTC64L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC64L_PTC64L_SHIFT) |
| #define I40E_GLPRT_PTC9522H(_i) (0x00300764 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PTC9522H_MAX_INDEX 3 |
| #define I40E_GLPRT_PTC9522H_PTC9522H_SHIFT 0 |
| #define I40E_GLPRT_PTC9522H_PTC9522H_MASK (0xFFFF << I40E_GLPRT_PTC9522H_PTC9522H_SHIFT) |
| #define I40E_GLPRT_PTC9522L(_i) (0x00300760 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_PTC9522L_MAX_INDEX 3 |
| #define I40E_GLPRT_PTC9522L_PTC9522L_SHIFT 0 |
| #define I40E_GLPRT_PTC9522L_PTC9522L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC9522L_PTC9522L_SHIFT) |
| #define I40E_GLPRT_PXOFFRXC(_i, _j) (0x00300280 + ((_i) * 8 + (_j) * 32)) |
| #define I40E_GLPRT_PXOFFRXC_MAX_INDEX 3 |
| #define I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_SHIFT 0 |
| #define I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_MASK (0xFFFFFFFF << I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_SHIFT) |
| #define I40E_GLPRT_PXOFFTXC(_i, _j) (0x00300880 + ((_i) * 8 + (_j) * 32)) |
| #define I40E_GLPRT_PXOFFTXC_MAX_INDEX 3 |
| #define I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_SHIFT 0 |
| #define I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_MASK (0xFFFFFFFF << I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_SHIFT) |
| #define I40E_GLPRT_PXONRXC(_i, _j) (0x00300180 + ((_i) * 8 + (_j) * 32)) |
| #define I40E_GLPRT_PXONRXC_MAX_INDEX 3 |
| #define I40E_GLPRT_PXONRXC_PRPXONRXCNT_SHIFT 0 |
| #define I40E_GLPRT_PXONRXC_PRPXONRXCNT_MASK (0xFFFFFFFF << I40E_GLPRT_PXONRXC_PRPXONRXCNT_SHIFT) |
| #define I40E_GLPRT_PXONTXC(_i, _j) (0x00300780 + ((_i) * 8 + (_j) * 32)) |
| #define I40E_GLPRT_PXONTXC_MAX_INDEX 3 |
| #define I40E_GLPRT_PXONTXC_PRPXONTXC_SHIFT 0 |
| #define I40E_GLPRT_PXONTXC_PRPXONTXC_MASK (0xFFFFFFFF << I40E_GLPRT_PXONTXC_PRPXONTXC_SHIFT) |
| #define I40E_GLPRT_RDPC(_i) (0x00300600 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_RDPC_MAX_INDEX 3 |
| #define I40E_GLPRT_RDPC_RDPC_SHIFT 0 |
| #define I40E_GLPRT_RDPC_RDPC_MASK (0xFFFFFFFF << I40E_GLPRT_RDPC_RDPC_SHIFT) |
| #define I40E_GLPRT_RFC(_i) (0x00300560 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_RFC_MAX_INDEX 3 |
| #define I40E_GLPRT_RFC_RFC_SHIFT 0 |
| #define I40E_GLPRT_RFC_RFC_MASK (0xFFFFFFFF << I40E_GLPRT_RFC_RFC_SHIFT) |
| #define I40E_GLPRT_RJC(_i) (0x00300580 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_RJC_MAX_INDEX 3 |
| #define I40E_GLPRT_RJC_RJC_SHIFT 0 |
| #define I40E_GLPRT_RJC_RJC_MASK (0xFFFFFFFF << I40E_GLPRT_RJC_RJC_SHIFT) |
| #define I40E_GLPRT_RLEC(_i) (0x003000A0 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_RLEC_MAX_INDEX 3 |
| #define I40E_GLPRT_RLEC_RLEC_SHIFT 0 |
| #define I40E_GLPRT_RLEC_RLEC_MASK (0xFFFFFFFF << I40E_GLPRT_RLEC_RLEC_SHIFT) |
| #define I40E_GLPRT_ROC(_i) (0x00300120 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_ROC_MAX_INDEX 3 |
| #define I40E_GLPRT_ROC_ROC_SHIFT 0 |
| #define I40E_GLPRT_ROC_ROC_MASK (0xFFFFFFFF << I40E_GLPRT_ROC_ROC_SHIFT) |
| #define I40E_GLPRT_RUC(_i) (0x00300100 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_RUC_MAX_INDEX 3 |
| #define I40E_GLPRT_RUC_RUC_SHIFT 0 |
| #define I40E_GLPRT_RUC_RUC_MASK (0xFFFFFFFF << I40E_GLPRT_RUC_RUC_SHIFT) |
| #define I40E_GLPRT_RUPP(_i) (0x00300660 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_RUPP_MAX_INDEX 3 |
| #define I40E_GLPRT_RUPP_RUPP_SHIFT 0 |
| #define I40E_GLPRT_RUPP_RUPP_MASK (0xFFFFFFFF << I40E_GLPRT_RUPP_RUPP_SHIFT) |
| #define I40E_GLPRT_RXON2OFFCNT(_i, _j) (0x00300380 + ((_i) * 8 + (_j) * 32)) |
| #define I40E_GLPRT_RXON2OFFCNT_MAX_INDEX 3 |
| #define I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT 0 |
| #define I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_MASK (0xFFFFFFFF << I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT) |
| #define I40E_GLPRT_STDC(_i) (0x00300640 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_STDC_MAX_INDEX 3 |
| #define I40E_GLPRT_STDC_STDC_SHIFT 0 |
| #define I40E_GLPRT_STDC_STDC_MASK (0xFFFFFFFF << I40E_GLPRT_STDC_STDC_SHIFT) |
| #define I40E_GLPRT_TDOLD(_i) (0x00300A20 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_TDOLD_MAX_INDEX 3 |
| #define I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT 0 |
| #define I40E_GLPRT_TDOLD_GLPRT_TDOLD_MASK (0xFFFFFFFF << I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT) |
| #define I40E_GLPRT_TDPC(_i) (0x00375400 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_TDPC_MAX_INDEX 3 |
| #define I40E_GLPRT_TDPC_TDPC_SHIFT 0 |
| #define I40E_GLPRT_TDPC_TDPC_MASK (0xFFFFFFFF << I40E_GLPRT_TDPC_TDPC_SHIFT) |
| #define I40E_GLPRT_UPRCH(_i) (0x003005A4 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_UPRCH_MAX_INDEX 3 |
| #define I40E_GLPRT_UPRCH_UPRCH_SHIFT 0 |
| #define I40E_GLPRT_UPRCH_UPRCH_MASK (0xFFFF << I40E_GLPRT_UPRCH_UPRCH_SHIFT) |
| #define I40E_GLPRT_UPRCL(_i) (0x003005A0 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_UPRCL_MAX_INDEX 3 |
| #define I40E_GLPRT_UPRCL_UPRCL_SHIFT 0 |
| #define I40E_GLPRT_UPRCL_UPRCL_MASK (0xFFFFFFFF << I40E_GLPRT_UPRCL_UPRCL_SHIFT) |
| #define I40E_GLPRT_UPTCH(_i) (0x003009C4 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_UPTCH_MAX_INDEX 3 |
| #define I40E_GLPRT_UPTCH_UPTCH_SHIFT 0 |
| #define I40E_GLPRT_UPTCH_UPTCH_MASK (0xFFFF << I40E_GLPRT_UPTCH_UPTCH_SHIFT) |
| #define I40E_GLPRT_UPTCL(_i) (0x003009C0 + ((_i) * 8)) /* _i=0...3 */ |
| #define I40E_GLPRT_UPTCL_MAX_INDEX 3 |
| #define I40E_GLPRT_UPTCL_VUPTCH_SHIFT 0 |
| #define I40E_GLPRT_UPTCL_VUPTCH_MASK (0xFFFFFFFF << I40E_GLPRT_UPTCL_VUPTCH_SHIFT) |
| #define I40E_GLSW_BPRCH(_i) (0x00370104 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLSW_BPRCH_MAX_INDEX 15 |
| #define I40E_GLSW_BPRCH_BPRCH_SHIFT 0 |
| #define I40E_GLSW_BPRCH_BPRCH_MASK (0xFFFF << I40E_GLSW_BPRCH_BPRCH_SHIFT) |
| #define I40E_GLSW_BPRCL(_i) (0x00370100 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLSW_BPRCL_MAX_INDEX 15 |
| #define I40E_GLSW_BPRCL_BPRCL_SHIFT 0 |
| #define I40E_GLSW_BPRCL_BPRCL_MASK (0xFFFFFFFF << I40E_GLSW_BPRCL_BPRCL_SHIFT) |
| #define I40E_GLSW_BPTCH(_i) (0x00340104 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLSW_BPTCH_MAX_INDEX 15 |
| #define I40E_GLSW_BPTCH_BPTCH_SHIFT 0 |
| #define I40E_GLSW_BPTCH_BPTCH_MASK (0xFFFF << I40E_GLSW_BPTCH_BPTCH_SHIFT) |
| #define I40E_GLSW_BPTCL(_i) (0x00340100 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLSW_BPTCL_MAX_INDEX 15 |
| #define I40E_GLSW_BPTCL_BPTCL_SHIFT 0 |
| #define I40E_GLSW_BPTCL_BPTCL_MASK (0xFFFFFFFF << I40E_GLSW_BPTCL_BPTCL_SHIFT) |
| #define I40E_GLSW_GORCH(_i) (0x0035C004 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLSW_GORCH_MAX_INDEX 15 |
| #define I40E_GLSW_GORCH_GORCH_SHIFT 0 |
| #define I40E_GLSW_GORCH_GORCH_MASK (0xFFFF << I40E_GLSW_GORCH_GORCH_SHIFT) |
| #define I40E_GLSW_GORCL(_i) (0x0035c000 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLSW_GORCL_MAX_INDEX 15 |
| #define I40E_GLSW_GORCL_GORCL_SHIFT 0 |
| #define I40E_GLSW_GORCL_GORCL_MASK (0xFFFFFFFF << I40E_GLSW_GORCL_GORCL_SHIFT) |
| #define I40E_GLSW_GOTCH(_i) (0x0032C004 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLSW_GOTCH_MAX_INDEX 15 |
| #define I40E_GLSW_GOTCH_GOTCH_SHIFT 0 |
| #define I40E_GLSW_GOTCH_GOTCH_MASK (0xFFFF << I40E_GLSW_GOTCH_GOTCH_SHIFT) |
| #define I40E_GLSW_GOTCL(_i) (0x0032c000 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLSW_GOTCL_MAX_INDEX 15 |
| #define I40E_GLSW_GOTCL_GOTCL_SHIFT 0 |
| #define I40E_GLSW_GOTCL_GOTCL_MASK (0xFFFFFFFF << I40E_GLSW_GOTCL_GOTCL_SHIFT) |
| #define I40E_GLSW_MPRCH(_i) (0x00370084 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLSW_MPRCH_MAX_INDEX 15 |
| #define I40E_GLSW_MPRCH_MPRCH_SHIFT 0 |
| #define I40E_GLSW_MPRCH_MPRCH_MASK (0xFFFF << I40E_GLSW_MPRCH_MPRCH_SHIFT) |
| #define I40E_GLSW_MPRCL(_i) (0x00370080 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLSW_MPRCL_MAX_INDEX 15 |
| #define I40E_GLSW_MPRCL_MPRCL_SHIFT 0 |
| #define I40E_GLSW_MPRCL_MPRCL_MASK (0xFFFFFFFF << I40E_GLSW_MPRCL_MPRCL_SHIFT) |
| #define I40E_GLSW_MPTCH(_i) (0x00340084 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLSW_MPTCH_MAX_INDEX 15 |
| #define I40E_GLSW_MPTCH_MPTCH_SHIFT 0 |
| #define I40E_GLSW_MPTCH_MPTCH_MASK (0xFFFF << I40E_GLSW_MPTCH_MPTCH_SHIFT) |
| #define I40E_GLSW_MPTCL(_i) (0x00340080 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLSW_MPTCL_MAX_INDEX 15 |
| #define I40E_GLSW_MPTCL_MPTCL_SHIFT 0 |
| #define I40E_GLSW_MPTCL_MPTCL_MASK (0xFFFFFFFF << I40E_GLSW_MPTCL_MPTCL_SHIFT) |
| #define I40E_GLSW_RUPP(_i) (0x00370180 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLSW_RUPP_MAX_INDEX 15 |
| #define I40E_GLSW_RUPP_RUPP_SHIFT 0 |
| #define I40E_GLSW_RUPP_RUPP_MASK (0xFFFFFFFF << I40E_GLSW_RUPP_RUPP_SHIFT) |
| #define I40E_GLSW_TDPC(_i) (0x00348000 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLSW_TDPC_MAX_INDEX 15 |
| #define I40E_GLSW_TDPC_TDPC_SHIFT 0 |
| #define I40E_GLSW_TDPC_TDPC_MASK (0xFFFFFFFF << I40E_GLSW_TDPC_TDPC_SHIFT) |
| #define I40E_GLSW_UPRCH(_i) (0x00370004 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLSW_UPRCH_MAX_INDEX 15 |
| #define I40E_GLSW_UPRCH_UPRCH_SHIFT 0 |
| #define I40E_GLSW_UPRCH_UPRCH_MASK (0xFFFF << I40E_GLSW_UPRCH_UPRCH_SHIFT) |
| #define I40E_GLSW_UPRCL(_i) (0x00370000 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLSW_UPRCL_MAX_INDEX 15 |
| #define I40E_GLSW_UPRCL_UPRCL_SHIFT 0 |
| #define I40E_GLSW_UPRCL_UPRCL_MASK (0xFFFFFFFF << I40E_GLSW_UPRCL_UPRCL_SHIFT) |
| #define I40E_GLSW_UPTCH(_i) (0x00340004 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLSW_UPTCH_MAX_INDEX 15 |
| #define I40E_GLSW_UPTCH_UPTCH_SHIFT 0 |
| #define I40E_GLSW_UPTCH_UPTCH_MASK (0xFFFF << I40E_GLSW_UPTCH_UPTCH_SHIFT) |
| #define I40E_GLSW_UPTCL(_i) (0x00340000 + ((_i) * 8)) /* _i=0...15 */ |
| #define I40E_GLSW_UPTCL_MAX_INDEX 15 |
| #define I40E_GLSW_UPTCL_UPTCL_SHIFT 0 |
| #define I40E_GLSW_UPTCL_UPTCL_MASK (0xFFFFFFFF << I40E_GLSW_UPTCL_UPTCL_SHIFT) |
| #define I40E_GLV_BPRCH(_i) (0x0036D804 + ((_i) * 8)) /* _i=0...383 */ |
| #define I40E_GLV_BPRCH_MAX_INDEX 383 |
| #define I40E_GLV_BPRCH_BPRCH_SHIFT 0 |
| #define I40E_GLV_BPRCH_BPRCH_MASK (0xFFFF << I40E_GLV_BPRCH_BPRCH_SHIFT) |
| #define I40E_GLV_BPRCL(_i) (0x0036d800 + ((_i) * 8)) /* _i=0...383 */ |
| #define I40E_GLV_BPRCL_MAX_INDEX 383 |
| #define I40E_GLV_BPRCL_BPRCL_SHIFT 0 |
| #define I40E_GLV_BPRCL_BPRCL_MASK (0xFFFFFFFF << I40E_GLV_BPRCL_BPRCL_SHIFT) |
| #define I40E_GLV_BPTCH(_i) (0x0033D804 + ((_i) * 8)) /* _i=0...383 */ |
| #define I40E_GLV_BPTCH_MAX_INDEX 383 |
| #define I40E_GLV_BPTCH_BPTCH_SHIFT 0 |
| #define I40E_GLV_BPTCH_BPTCH_MASK (0xFFFF << I40E_GLV_BPTCH_BPTCH_SHIFT) |
| #define I40E_GLV_BPTCL(_i) (0x0033d800 + ((_i) * 8)) /* _i=0...383 */ |
| #define I40E_GLV_BPTCL_MAX_INDEX 383 |
| #define I40E_GLV_BPTCL_BPTCL_SHIFT 0 |
| #define I40E_GLV_BPTCL_BPTCL_MASK (0xFFFFFFFF << I40E_GLV_BPTCL_BPTCL_SHIFT) |
| #define I40E_GLV_GORCH(_i) (0x00358004 + ((_i) * 8)) /* _i=0...383 */ |
| #define I40E_GLV_GORCH_MAX_INDEX 383 |
| #define I40E_GLV_GORCH_GORCH_SHIFT 0 |
| #define I40E_GLV_GORCH_GORCH_MASK (0xFFFF << I40E_GLV_GORCH_GORCH_SHIFT) |
| #define I40E_GLV_GORCL(_i) (0x00358000 + ((_i) * 8)) /* _i=0...383 */ |
| #define I40E_GLV_GORCL_MAX_INDEX 383 |
| #define I40E_GLV_GORCL_GORCL_SHIFT 0 |
| #define I40E_GLV_GORCL_GORCL_MASK (0xFFFFFFFF << I40E_GLV_GORCL_GORCL_SHIFT) |
| #define I40E_GLV_GOTCH(_i) (0x00328004 + ((_i) * 8)) /* _i=0...383 */ |
| #define I40E_GLV_GOTCH_MAX_INDEX 383 |
| #define I40E_GLV_GOTCH_GOTCH_SHIFT 0 |
| #define I40E_GLV_GOTCH_GOTCH_MASK (0xFFFF << I40E_GLV_GOTCH_GOTCH_SHIFT) |
| #define I40E_GLV_GOTCL(_i) (0x00328000 + ((_i) * 8)) /* _i=0...383 */ |
| #define I40E_GLV_GOTCL_MAX_INDEX 383 |
| #define I40E_GLV_GOTCL_GOTCL_SHIFT 0 |
| #define I40E_GLV_GOTCL_GOTCL_MASK (0xFFFFFFFF << I40E_GLV_GOTCL_GOTCL_SHIFT) |
| #define I40E_GLV_MPRCH(_i) (0x0036CC04 + ((_i) * 8)) /* _i=0...383 */ |
| #define I40E_GLV_MPRCH_MAX_INDEX 383 |
| #define I40E_GLV_MPRCH_MPRCH_SHIFT 0 |
| #define I40E_GLV_MPRCH_MPRCH_MASK (0xFFFF << I40E_GLV_MPRCH_MPRCH_SHIFT) |
| #define I40E_GLV_MPRCL(_i) (0x0036cc00 + ((_i) * 8)) /* _i=0...383 */ |
| #define I40E_GLV_MPRCL_MAX_INDEX 383 |
| #define I40E_GLV_MPRCL_MPRCL_SHIFT 0 |
| #define I40E_GLV_MPRCL_MPRCL_MASK (0xFFFFFFFF << I40E_GLV_MPRCL_MPRCL_SHIFT) |
| #define I40E_GLV_MPTCH(_i) (0x0033CC04 + ((_i) * 8)) /* _i=0...383 */ |
| #define I40E_GLV_MPTCH_MAX_INDEX 383 |
| #define I40E_GLV_MPTCH_MPTCH_SHIFT 0 |
| #define I40E_GLV_MPTCH_MPTCH_MASK (0xFFFF << I40E_GLV_MPTCH_MPTCH_SHIFT) |
| #define I40E_GLV_MPTCL(_i) (0x0033cc00 + ((_i) * 8)) /* _i=0...383 */ |
| #define I40E_GLV_MPTCL_MAX_INDEX 383 |
| #define I40E_GLV_MPTCL_MPTCL_SHIFT 0 |
| #define I40E_GLV_MPTCL_MPTCL_MASK (0xFFFFFFFF << I40E_GLV_MPTCL_MPTCL_SHIFT) |
| #define I40E_GLV_RDPC(_i) (0x00310000 + ((_i) * 8)) /* _i=0...383 */ |
| #define I40E_GLV_RDPC_MAX_INDEX 383 |
| #define I40E_GLV_RDPC_RDPC_SHIFT 0 |
| #define I40E_GLV_RDPC_RDPC_MASK (0xFFFFFFFF << I40E_GLV_RDPC_RDPC_SHIFT) |
| #define I40E_GLV_RUPP(_i) (0x0036E400 + ((_i) * 8)) /* _i=0...383 */ |
| #define I40E_GLV_RUPP_MAX_INDEX 383 |
| #define I40E_GLV_RUPP_RUPP_SHIFT 0 |
| #define I40E_GLV_RUPP_RUPP_MASK (0xFFFFFFFF << I40E_GLV_RUPP_RUPP_SHIFT) |
| #define I40E_GLV_TEPC(_VSI) (0x00344000 + ((_VSI) * 8)) /* _i=0...383 */ |
| #define I40E_GLV_TEPC_MAX_INDEX 383 |
| #define I40E_GLV_TEPC_TEPC_SHIFT 0 |
| #define I40E_GLV_TEPC_TEPC_MASK (0xFFFFFFFF << I40E_GLV_TEPC_TEPC_SHIFT) |
| #define I40E_GLV_UPRCH(_i) (0x0036C004 + ((_i) * 8)) /* _i=0...383 */ |
| #define I40E_GLV_UPRCH_MAX_INDEX 383 |
| #define I40E_GLV_UPRCH_UPRCH_SHIFT 0 |
| #define I40E_GLV_UPRCH_UPRCH_MASK (0xFFFF << I40E_GLV_UPRCH_UPRCH_SHIFT) |
| #define I40E_GLV_UPRCL(_i) (0x0036c000 + ((_i) * 8)) /* _i=0...383 */ |
| #define I40E_GLV_UPRCL_MAX_INDEX 383 |
| #define I40E_GLV_UPRCL_UPRCL_SHIFT 0 |
| #define I40E_GLV_UPRCL_UPRCL_MASK (0xFFFFFFFF << I40E_GLV_UPRCL_UPRCL_SHIFT) |
| #define I40E_GLV_UPTCH(_i) (0x0033C004 + ((_i) * 8)) /* _i=0...383 */ |
| #define I40E_GLV_UPTCH_MAX_INDEX 383 |
| #define I40E_GLV_UPTCH_GLVUPTCH_SHIFT 0 |
| #define I40E_GLV_UPTCH_GLVUPTCH_MASK (0xFFFF << I40E_GLV_UPTCH_GLVUPTCH_SHIFT) |
| #define I40E_GLV_UPTCL(_i) (0x0033c000 + ((_i) * 8)) /* _i=0...383 */ |
| #define I40E_GLV_UPTCL_MAX_INDEX 383 |
| #define I40E_GLV_UPTCL_UPTCL_SHIFT 0 |
| #define I40E_GLV_UPTCL_UPTCL_MASK (0xFFFFFFFF << I40E_GLV_UPTCL_UPTCL_SHIFT) |
| #define I40E_GLVEBTC_RBCH(_i, _j) (0x00364004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ |
| #define I40E_GLVEBTC_RBCH_MAX_INDEX 7 |
| #define I40E_GLVEBTC_RBCH_TCBCH_SHIFT 0 |
| #define I40E_GLVEBTC_RBCH_TCBCH_MASK (0xFFFF << I40E_GLVEBTC_RBCH_TCBCH_SHIFT) |
| #define I40E_GLVEBTC_RBCL(_i, _j) (0x00364000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ |
| #define I40E_GLVEBTC_RBCL_MAX_INDEX 7 |
| #define I40E_GLVEBTC_RBCL_TCBCL_SHIFT 0 |
| #define I40E_GLVEBTC_RBCL_TCBCL_MASK (0xFFFFFFFF << I40E_GLVEBTC_RBCL_TCBCL_SHIFT) |
| #define I40E_GLVEBTC_RPCH(_i, _j) (0x00368004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ |
| #define I40E_GLVEBTC_RPCH_MAX_INDEX 7 |
| #define I40E_GLVEBTC_RPCH_TCPCH_SHIFT 0 |
| #define I40E_GLVEBTC_RPCH_TCPCH_MASK (0xFFFF << I40E_GLVEBTC_RPCH_TCPCH_SHIFT) |
| #define I40E_GLVEBTC_RPCL(_i, _j) (0x00368000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ |
| #define I40E_GLVEBTC_RPCL_MAX_INDEX 7 |
| #define I40E_GLVEBTC_RPCL_TCPCL_SHIFT 0 |
| #define I40E_GLVEBTC_RPCL_TCPCL_MASK (0xFFFFFFFF << I40E_GLVEBTC_RPCL_TCPCL_SHIFT) |
| #define I40E_GLVEBTC_TBCH(_i, _j) (0x00334004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ |
| #define I40E_GLVEBTC_TBCH_MAX_INDEX 7 |
| #define I40E_GLVEBTC_TBCH_TCBCH_SHIFT 0 |
| #define I40E_GLVEBTC_TBCH_TCBCH_MASK (0xFFFF << I40E_GLVEBTC_TBCH_TCBCH_SHIFT) |
| #define I40E_GLVEBTC_TBCL(_i, _j) (0x00334000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ |
| #define I40E_GLVEBTC_TBCL_MAX_INDEX 7 |
| #define I40E_GLVEBTC_TBCL_TCBCL_SHIFT 0 |
| #define I40E_GLVEBTC_TBCL_TCBCL_MASK (0xFFFFFFFF << I40E_GLVEBTC_TBCL_TCBCL_SHIFT) |
| #define I40E_GLVEBTC_TPCH(_i, _j) (0x00338004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ |
| #define I40E_GLVEBTC_TPCH_MAX_INDEX 7 |
| #define I40E_GLVEBTC_TPCH_TCPCH_SHIFT 0 |
| #define I40E_GLVEBTC_TPCH_TCPCH_MASK (0xFFFF << I40E_GLVEBTC_TPCH_TCPCH_SHIFT) |
| #define I40E_GLVEBTC_TPCL(_i, _j) (0x00338000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ |
| #define I40E_GLVEBTC_TPCL_MAX_INDEX 7 |
| #define I40E_GLVEBTC_TPCL_TCPCL_SHIFT 0 |
| #define I40E_GLVEBTC_TPCL_TCPCL_MASK (0xFFFFFFFF << I40E_GLVEBTC_TPCL_TCPCL_SHIFT) |
| #define I40E_GLVEBVL_BPCH(_i) (0x00374804 + ((_i) * 8)) /* _i=0...127 */ |
| #define I40E_GLVEBVL_BPCH_MAX_INDEX 127 |
| #define I40E_GLVEBVL_BPCH_VLBPCH_SHIFT 0 |
| #define I40E_GLVEBVL_BPCH_VLBPCH_MASK (0xFFFF << I40E_GLVEBVL_BPCH_VLBPCH_SHIFT) |
| #define I40E_GLVEBVL_BPCL(_i) (0x00374800 + ((_i) * 8)) /* _i=0...127 */ |
| #define I40E_GLVEBVL_BPCL_MAX_INDEX 127 |
| #define I40E_GLVEBVL_BPCL_VLBPCL_SHIFT 0 |
| #define I40E_GLVEBVL_BPCL_VLBPCL_MASK (0xFFFFFFFF << I40E_GLVEBVL_BPCL_VLBPCL_SHIFT) |
| #define I40E_GLVEBVL_GORCH(_i) (0x00360004 + ((_i) * 8)) /* _i=0...127 */ |
| #define I40E_GLVEBVL_GORCH_MAX_INDEX 127 |
| #define I40E_GLVEBVL_GORCH_VLBCH_SHIFT 0 |
| #define I40E_GLVEBVL_GORCH_VLBCH_MASK (0xFFFF << I40E_GLVEBVL_GORCH_VLBCH_SHIFT) |
| #define I40E_GLVEBVL_GORCL(_i) (0x00360000 + ((_i) * 8)) /* _i=0...127 */ |
| #define I40E_GLVEBVL_GORCL_MAX_INDEX 127 |
| #define I40E_GLVEBVL_GORCL_VLBCL_SHIFT 0 |
| #define I40E_GLVEBVL_GORCL_VLBCL_MASK (0xFFFFFFFF << I40E_GLVEBVL_GORCL_VLBCL_SHIFT) |
| #define I40E_GLVEBVL_GOTCH(_i) (0x00330004 + ((_i) * 8)) /* _i=0...127 */ |
| #define I40E_GLVEBVL_GOTCH_MAX_INDEX 127 |
| #define I40E_GLVEBVL_GOTCH_VLBCH_SHIFT 0 |
| #define I40E_GLVEBVL_GOTCH_VLBCH_MASK (0xFFFF << I40E_GLVEBVL_GOTCH_VLBCH_SHIFT) |
| #define I40E_GLVEBVL_GOTCL(_i) (0x00330000 + ((_i) * 8)) /* _i=0...127 */ |
| #define I40E_GLVEBVL_GOTCL_MAX_INDEX 127 |
| #define I40E_GLVEBVL_GOTCL_VLBCL_SHIFT 0 |
| #define I40E_GLVEBVL_GOTCL_VLBCL_MASK (0xFFFFFFFF << I40E_GLVEBVL_GOTCL_VLBCL_SHIFT) |
| #define I40E_GLVEBVL_MPCH(_i) (0x00374404 + ((_i) * 8)) /* _i=0...127 */ |
| #define I40E_GLVEBVL_MPCH_MAX_INDEX 127 |
| #define I40E_GLVEBVL_MPCH_VLMPCH_SHIFT 0 |
| #define I40E_GLVEBVL_MPCH_VLMPCH_MASK (0xFFFF << I40E_GLVEBVL_MPCH_VLMPCH_SHIFT) |
| #define I40E_GLVEBVL_MPCL(_i) (0x00374400 + ((_i) * 8)) /* _i=0...127 */ |
| #define I40E_GLVEBVL_MPCL_MAX_INDEX 127 |
| #define I40E_GLVEBVL_MPCL_VLMPCL_SHIFT 0 |
| #define I40E_GLVEBVL_MPCL_VLMPCL_MASK (0xFFFFFFFF << I40E_GLVEBVL_MPCL_VLMPCL_SHIFT) |
| #define I40E_GLVEBVL_UPCH(_i) (0x00374004 + ((_i) * 8)) /* _i=0...127 */ |
| #define I40E_GLVEBVL_UPCH_MAX_INDEX 127 |
| #define I40E_GLVEBVL_UPCH_VLUPCH_SHIFT 0 |
| #define I40E_GLVEBVL_UPCH_VLUPCH_MASK (0xFFFF << I40E_GLVEBVL_UPCH_VLUPCH_SHIFT) |
| #define I40E_GLVEBVL_UPCL(_i) (0x00374000 + ((_i) * 8)) /* _i=0...127 */ |
| #define I40E_GLVEBVL_UPCL_MAX_INDEX 127 |
| #define I40E_GLVEBVL_UPCL_VLUPCL_SHIFT 0 |
| #define I40E_GLVEBVL_UPCL_VLUPCL_MASK (0xFFFFFFFF << I40E_GLVEBVL_UPCL_VLUPCL_SHIFT) |
| #define I40E_GL_MTG_FLU_MSK_H 0x00269F4C |
| #define I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_SHIFT 0 |
| #define I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_MASK (0xFFFF << I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_SHIFT) |
| #define I40E_GL_MTG_FLU_MSK_L 0x00269F44 |
| #define I40E_GL_MTG_FLU_MSK_L_MASK_LOW_SHIFT 0 |
| #define I40E_GL_MTG_FLU_MSK_L_MASK_LOW_MASK (0xFFFFFFFF << I40E_GL_MTG_FLU_MSK_L_MASK_LOW_SHIFT) |
| #define I40E_GL_SWR_DEF_ACT(_i) (0x0026CF00 + ((_i) * 4)) /* _i=0...25 */ |
| #define I40E_GL_SWR_DEF_ACT_MAX_INDEX 25 |
| #define I40E_GL_SWR_DEF_ACT_DEF_ACTION_SHIFT 0 |
| #define I40E_GL_SWR_DEF_ACT_DEF_ACTION_MASK (0xFFFFFFFF << I40E_GL_SWR_DEF_ACT_DEF_ACTION_SHIFT) |
| #define I40E_GL_SWR_DEF_ACT_EN 0x0026CF84 |
| #define I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_SHIFT 0 |
| #define I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_MASK (0xFFFFFFFF << I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_SHIFT) |
| #define I40E_PRT_MSCCNT 0x00256BA0 |
| #define I40E_PRT_MSCCNT_CCOUNT_SHIFT 0 |
| #define I40E_PRT_MSCCNT_CCOUNT_MASK (0x1FFFFFF << I40E_PRT_MSCCNT_CCOUNT_SHIFT) |
| #define I40E_PRT_SCSTS 0x00256C20 |
| #define I40E_PRT_SCSTS_BSCA_SHIFT 0 |
| #define I40E_PRT_SCSTS_BSCA_MASK (0x1 << I40E_PRT_SCSTS_BSCA_SHIFT) |
| #define I40E_PRT_SCSTS_BSCAP_SHIFT 1 |
| #define I40E_PRT_SCSTS_BSCAP_MASK (0x1 << I40E_PRT_SCSTS_BSCAP_SHIFT) |
| #define I40E_PRT_SCSTS_MSCA_SHIFT 2 |
| #define I40E_PRT_SCSTS_MSCA_MASK (0x1 << I40E_PRT_SCSTS_MSCA_SHIFT) |
| #define I40E_PRT_SCSTS_MSCAP_SHIFT 3 |
| #define I40E_PRT_SCSTS_MSCAP_MASK (0x1 << I40E_PRT_SCSTS_MSCAP_SHIFT) |
| #define I40E_PRT_SWT_BSCCNT 0x00256C60 |
| #define I40E_PRT_SWT_BSCCNT_CCOUNT_SHIFT 0 |
| #define I40E_PRT_SWT_BSCCNT_CCOUNT_MASK (0x1FFFFFF << I40E_PRT_SWT_BSCCNT_CCOUNT_SHIFT) |
| #define I40E_PRTTSYN_ADJ 0x001E4280 |
| #define I40E_PRTTSYN_ADJ_TSYNADJ_SHIFT 0 |
| #define I40E_PRTTSYN_ADJ_TSYNADJ_MASK (0x7FFFFFFF << I40E_PRTTSYN_ADJ_TSYNADJ_SHIFT) |
| #define I40E_PRTTSYN_ADJ_SIGN_SHIFT 31 |
| #define I40E_PRTTSYN_ADJ_SIGN_MASK (0x1 << I40E_PRTTSYN_ADJ_SIGN_SHIFT) |
| #define I40E_PRTTSYN_AUX_0(_i) (0x001E42A0 + ((_i) * 32)) /* _i=0...1 */ |
| #define I40E_PRTTSYN_AUX_0_MAX_INDEX 1 |
| #define I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT 0 |
| #define I40E_PRTTSYN_AUX_0_OUT_ENA_MASK (0x1 << I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT) |
| #define I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT 1 |
| #define I40E_PRTTSYN_AUX_0_OUTMOD_MASK (0x3 << I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT) |
| #define I40E_PRTTSYN_AUX_0_OUTLVL_SHIFT 3 |
| #define I40E_PRTTSYN_AUX_0_OUTLVL_MASK (0x1 << I40E_PRTTSYN_AUX_0_OUTLVL_SHIFT) |
| #define I40E_PRTTSYN_AUX_0_PULSEW_SHIFT 8 |
| #define I40E_PRTTSYN_AUX_0_PULSEW_MASK (0xF << I40E_PRTTSYN_AUX_0_PULSEW_SHIFT) |
| #define I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT 16 |
| #define I40E_PRTTSYN_AUX_0_EVNTLVL_MASK (0x3 << I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT) |
| #define I40E_PRTTSYN_AUX_1(_i) (0x001E42E0 + ((_i) * 32)) /* _i=0...1 */ |
| #define I40E_PRTTSYN_AUX_1_MAX_INDEX 1 |
| #define I40E_PRTTSYN_AUX_1_INSTNT_SHIFT 0 |
| #define I40E_PRTTSYN_AUX_1_INSTNT_MASK (0x1 << I40E_PRTTSYN_AUX_1_INSTNT_SHIFT) |
| #define I40E_PRTTSYN_AUX_1_SAMPLE_TIME_SHIFT 1 |
| #define I40E_PRTTSYN_AUX_1_SAMPLE_TIME_MASK (0x1 << I40E_PRTTSYN_AUX_1_SAMPLE_TIME_SHIFT) |
| #define I40E_PRTTSYN_CLKO(_i) (0x001E4240 + ((_i) * 32)) /* _i=0...1 */ |
| #define I40E_PRTTSYN_CLKO_MAX_INDEX 1 |
| #define I40E_PRTTSYN_CLKO_TSYNCLKO_SHIFT 0 |
| #define I40E_PRTTSYN_CLKO_TSYNCLKO_MASK (0xFFFFFFFF << I40E_PRTTSYN_CLKO_TSYNCLKO_SHIFT) |
| #define I40E_PRTTSYN_CTL0 0x001E4200 |
| #define I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_SHIFT 0 |
| #define I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_MASK (0x1 << I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_SHIFT) |
| #define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT 1 |
| #define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK (0x1 << I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT) |
| #define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT 2 |
| #define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_MASK (0x1 << I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT) |
| #define I40E_PRTTSYN_CTL0_TGT_INT_ENA_SHIFT 3 |
| #define I40E_PRTTSYN_CTL0_TGT_INT_ENA_MASK (0x1 << I40E_PRTTSYN_CTL0_TGT_INT_ENA_SHIFT) |
| #define I40E_PRTTSYN_CTL0_PF_ID_SHIFT 8 |
| #define I40E_PRTTSYN_CTL0_PF_ID_MASK (0xF << I40E_PRTTSYN_CTL0_PF_ID_SHIFT) |
| #define I40E_PRTTSYN_CTL0_TSYNACT_SHIFT 12 |
| #define I40E_PRTTSYN_CTL0_TSYNACT_MASK (0x3 << I40E_PRTTSYN_CTL0_TSYNACT_SHIFT) |
| #define I40E_PRTTSYN_CTL0_TSYNENA_SHIFT 31 |
| #define I40E_PRTTSYN_CTL0_TSYNENA_MASK (0x1 << I40E_PRTTSYN_CTL0_TSYNENA_SHIFT) |
| #define I40E_PRTTSYN_CTL1 0x00085020 |
| #define I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT 0 |
| #define I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK (0xFF << I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT) |
| #define I40E_PRTTSYN_CTL1_V1MESSTYPE1_SHIFT 8 |
| #define I40E_PRTTSYN_CTL1_V1MESSTYPE1_MASK (0xFF << I40E_PRTTSYN_CTL1_V1MESSTYPE1_SHIFT) |
| #define I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT 16 |
| #define I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK (0xF << I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT) |
| #define I40E_PRTTSYN_CTL1_V2MESSTYPE1_SHIFT 20 |
| #define I40E_PRTTSYN_CTL1_V2MESSTYPE1_MASK (0xF << I40E_PRTTSYN_CTL1_V2MESSTYPE1_SHIFT) |
| #define I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT 24 |
| #define I40E_PRTTSYN_CTL1_TSYNTYPE_MASK (0x3 << I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) |
| #define I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT 26 |
| #define I40E_PRTTSYN_CTL1_UDP_ENA_MASK (0x3 << I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT) |
| #define I40E_PRTTSYN_CTL1_TSYNENA_SHIFT 31 |
| #define I40E_PRTTSYN_CTL1_TSYNENA_MASK (0x1 << I40E_PRTTSYN_CTL1_TSYNENA_SHIFT) |
| #define I40E_PRTTSYN_EVNT_H(_i) (0x001E40C0 + ((_i) * 32)) /* _i=0...1 */ |
| #define I40E_PRTTSYN_EVNT_H_MAX_INDEX 1 |
| #define I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_SHIFT 0 |
| #define I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_MASK (0xFFFFFFFF << I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_SHIFT) |
| #define I40E_PRTTSYN_EVNT_L(_i) (0x001E4080 + ((_i) * 32)) /* _i=0...1 */ |
| #define I40E_PRTTSYN_EVNT_L_MAX_INDEX 1 |
| #define I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_SHIFT 0 |
| #define I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_MASK (0xFFFFFFFF << I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_SHIFT) |
| #define I40E_PRTTSYN_INC_H 0x001E4060 |
| #define I40E_PRTTSYN_INC_H_TSYNINC_H_SHIFT 0 |
| #define I40E_PRTTSYN_INC_H_TSYNINC_H_MASK (0x3F << I40E_PRTTSYN_INC_H_TSYNINC_H_SHIFT) |
| #define I40E_PRTTSYN_INC_L 0x001E4040 |
| #define I40E_PRTTSYN_INC_L_TSYNINC_L_SHIFT 0 |
| #define I40E_PRTTSYN_INC_L_TSYNINC_L_MASK (0xFFFFFFFF << I40E_PRTTSYN_INC_L_TSYNINC_L_SHIFT) |
| #define I40E_PRTTSYN_RXTIME_H(_i) (0x00085040 + ((_i) * 32)) /* _i=0...3 */ |
| #define I40E_PRTTSYN_RXTIME_H_MAX_INDEX 3 |
| #define I40E_PRTTSYN_RXTIME_H_RXTIEM_H_SHIFT 0 |
| #define I40E_PRTTSYN_RXTIME_H_RXTIEM_H_MASK (0xFFFFFFFF << I40E_PRTTSYN_RXTIME_H_RXTIEM_H_SHIFT) |
| #define I40E_PRTTSYN_RXTIME_L(_i) (0x000850C0 + ((_i) * 32)) /* _i=0...3 */ |
| #define I40E_PRTTSYN_RXTIME_L_MAX_INDEX 3 |
| #define I40E_PRTTSYN_RXTIME_L_RXTIEM_L_SHIFT 0 |
| #define I40E_PRTTSYN_RXTIME_L_RXTIEM_L_MASK (0xFFFFFFFF << I40E_PRTTSYN_RXTIME_L_RXTIEM_L_SHIFT) |
| #define I40E_PRTTSYN_STAT_0 0x001E4220 |
| #define I40E_PRTTSYN_STAT_0_EVENT0_SHIFT 0 |
| #define I40E_PRTTSYN_STAT_0_EVENT0_MASK (0x1 << I40E_PRTTSYN_STAT_0_EVENT0_SHIFT) |
| #define I40E_PRTTSYN_STAT_0_EVENT1_SHIFT 1 |
| #define I40E_PRTTSYN_STAT_0_EVENT1_MASK (0x1 << I40E_PRTTSYN_STAT_0_EVENT1_SHIFT) |
| #define I40E_PRTTSYN_STAT_0_TGT0_SHIFT 2 |
| #define I40E_PRTTSYN_STAT_0_TGT0_MASK (0x1 << I40E_PRTTSYN_STAT_0_TGT0_SHIFT) |
| #define I40E_PRTTSYN_STAT_0_TGT1_SHIFT 3 |
| #define I40E_PRTTSYN_STAT_0_TGT1_MASK (0x1 << I40E_PRTTSYN_STAT_0_TGT1_SHIFT) |
| #define I40E_PRTTSYN_STAT_0_TXTIME_SHIFT 4 |
| #define I40E_PRTTSYN_STAT_0_TXTIME_MASK (0x1 << I40E_PRTTSYN_STAT_0_TXTIME_SHIFT) |
| #define I40E_PRTTSYN_STAT_1 0x00085140 |
| #define I40E_PRTTSYN_STAT_1_RXT0_SHIFT 0 |
| #define I40E_PRTTSYN_STAT_1_RXT0_MASK (0x1 << I40E_PRTTSYN_STAT_1_RXT0_SHIFT) |
| #define I40E_PRTTSYN_STAT_1_RXT1_SHIFT 1 |
| #define I40E_PRTTSYN_STAT_1_RXT1_MASK (0x1 << I40E_PRTTSYN_STAT_1_RXT1_SHIFT) |
| #define I40E_PRTTSYN_STAT_1_RXT2_SHIFT 2 |
| #define I40E_PRTTSYN_STAT_1_RXT2_MASK (0x1 << I40E_PRTTSYN_STAT_1_RXT2_SHIFT) |
| #define I40E_PRTTSYN_STAT_1_RXT3_SHIFT 3 |
| #define I40E_PRTTSYN_STAT_1_RXT3_MASK (0x1 << I40E_PRTTSYN_STAT_1_RXT3_SHIFT) |
| #define I40E_PRTTSYN_TGT_H(_i) (0x001E4180 + ((_i) * 32)) /* _i=0...1 */ |
| #define I40E_PRTTSYN_TGT_H_MAX_INDEX 1 |
| #define I40E_PRTTSYN_TGT_H_TSYNTGTT_H_SHIFT 0 |
| #define I40E_PRTTSYN_TGT_H_TSYNTGTT_H_MASK (0xFFFFFFFF << I40E_PRTTSYN_TGT_H_TSYNTGTT_H_SHIFT) |
| #define I40E_PRTTSYN_TGT_L(_i) (0x001E4140 + ((_i) * 32)) /* _i=0...1 */ |
| #define I40E_PRTTSYN_TGT_L_MAX_INDEX 1 |
| #define I40E_PRTTSYN_TGT_L_TSYNTGTT_L_SHIFT 0 |
| #define I40E_PRTTSYN_TGT_L_TSYNTGTT_L_MASK (0xFFFFFFFF << I40E_PRTTSYN_TGT_L_TSYNTGTT_L_SHIFT) |
| #define I40E_PRTTSYN_TIME_H 0x001E4120 |
| #define I40E_PRTTSYN_TIME_H_TSYNTIME_H_SHIFT 0 |
| #define I40E_PRTTSYN_TIME_H_TSYNTIME_H_MASK (0xFFFFFFFF << I40E_PRTTSYN_TIME_H_TSYNTIME_H_SHIFT) |
| #define I40E_PRTTSYN_TIME_L 0x001E4100 |
| #define I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT 0 |
| #define I40E_PRTTSYN_TIME_L_TSYNTIME_L_MASK (0xFFFFFFFF << I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT) |
| #define I40E_PRTTSYN_TXTIME_H 0x001E41E0 |
| #define I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT 0 |
| #define I40E_PRTTSYN_TXTIME_H_TXTIEM_H_MASK (0xFFFFFFFF << I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT) |
| #define I40E_PRTTSYN_TXTIME_L 0x001E41C0 |
| #define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT 0 |
| #define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_MASK (0xFFFFFFFF << I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT) |
| #define I40E_GLSCD_QUANTA 0x000B2080 |
| #define I40E_GLSCD_QUANTA_TSCDQUANTA_SHIFT 0 |
| #define I40E_GLSCD_QUANTA_TSCDQUANTA_MASK (0x7 << I40E_GLSCD_QUANTA_TSCDQUANTA_SHIFT) |
| #define I40E_GL_MDET_RX 0x0012A510 |
| #define I40E_GL_MDET_RX_FUNCTION_SHIFT 0 |
| #define I40E_GL_MDET_RX_FUNCTION_MASK (0xFF << I40E_GL_MDET_RX_FUNCTION_SHIFT) |
| #define I40E_GL_MDET_RX_EVENT_SHIFT 8 |
| #define I40E_GL_MDET_RX_EVENT_MASK (0x1FF << I40E_GL_MDET_RX_EVENT_SHIFT) |
| #define I40E_GL_MDET_RX_QUEUE_SHIFT 17 |
| #define I40E_GL_MDET_RX_QUEUE_MASK (0x3FFF << I40E_GL_MDET_RX_QUEUE_SHIFT) |
| #define I40E_GL_MDET_RX_VALID_SHIFT 31 |
| #define I40E_GL_MDET_RX_VALID_MASK (0x1 << I40E_GL_MDET_RX_VALID_SHIFT) |
| #define I40E_GL_MDET_TX 0x000E6480 |
| #define I40E_GL_MDET_TX_FUNCTION_SHIFT 0 |
| #define I40E_GL_MDET_TX_FUNCTION_MASK (0xFF << I40E_GL_MDET_TX_FUNCTION_SHIFT) |
| #define I40E_GL_MDET_TX_EVENT_SHIFT 8 |
| #define I40E_GL_MDET_TX_EVENT_MASK (0x1FF << I40E_GL_MDET_TX_EVENT_SHIFT) |
| #define I40E_GL_MDET_TX_QUEUE_SHIFT 17 |
| #define I40E_GL_MDET_TX_QUEUE_MASK (0x3FFF << I40E_GL_MDET_TX_QUEUE_SHIFT) |
| #define I40E_GL_MDET_TX_VALID_SHIFT 31 |
| #define I40E_GL_MDET_TX_VALID_MASK (0x1 << I40E_GL_MDET_TX_VALID_SHIFT) |
| #define I40E_PF_MDET_RX 0x0012A400 |
| #define I40E_PF_MDET_RX_VALID_SHIFT 0 |
| #define I40E_PF_MDET_RX_VALID_MASK (0x1 << I40E_PF_MDET_RX_VALID_SHIFT) |
| #define I40E_PF_MDET_TX 0x000E6400 |
| #define I40E_PF_MDET_TX_VALID_SHIFT 0 |
| #define I40E_PF_MDET_TX_VALID_MASK (0x1 << I40E_PF_MDET_TX_VALID_SHIFT) |
| #define I40E_PF_VT_PFALLOC 0x001C0500 |
| #define I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT 0 |
| #define I40E_PF_VT_PFALLOC_FIRSTVF_MASK (0xFF << I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT) |
| #define I40E_PF_VT_PFALLOC_LASTVF_SHIFT 8 |
| #define I40E_PF_VT_PFALLOC_LASTVF_MASK (0xFF << I40E_PF_VT_PFALLOC_LASTVF_SHIFT) |
| #define I40E_PF_VT_PFALLOC_VALID_SHIFT 31 |
| #define I40E_PF_VT_PFALLOC_VALID_MASK (0x1 << I40E_PF_VT_PFALLOC_VALID_SHIFT) |
| #define I40E_VP_MDET_RX(_VF) (0x0012A000 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VP_MDET_RX_MAX_INDEX 127 |
| #define I40E_VP_MDET_RX_VALID_SHIFT 0 |
| #define I40E_VP_MDET_RX_VALID_MASK (0x1 << I40E_VP_MDET_RX_VALID_SHIFT) |
| #define I40E_VP_MDET_TX(_VF) (0x000E6000 + ((_VF) * 4)) /* _i=0...127 */ |
| #define I40E_VP_MDET_TX_MAX_INDEX 127 |
| #define I40E_VP_MDET_TX_VALID_SHIFT 0 |
| #define I40E_VP_MDET_TX_VALID_MASK (0x1 << I40E_VP_MDET_TX_VALID_SHIFT) |
| #define I40E_GLPM_WUMC 0x0006C800 |
| #define I40E_GLPM_WUMC_NOTCO_SHIFT 0 |
| #define I40E_GLPM_WUMC_NOTCO_MASK (0x1 << I40E_GLPM_WUMC_NOTCO_SHIFT) |
| #define I40E_GLPM_WUMC_SRST_PIN_VAL_SHIFT 1 |
| #define I40E_GLPM_WUMC_SRST_PIN_VAL_MASK (0x1 << I40E_GLPM_WUMC_SRST_PIN_VAL_SHIFT) |
| #define I40E_GLPM_WUMC_ROL_MODE_SHIFT 2 |
| #define I40E_GLPM_WUMC_ROL_MODE_MASK (0x1 << I40E_GLPM_WUMC_ROL_MODE_SHIFT) |
| #define I40E_GLPM_WUMC_RESERVED_4_SHIFT 3 |
| #define I40E_GLPM_WUMC_RESERVED_4_MASK (0x1FFF << I40E_GLPM_WUMC_RESERVED_4_SHIFT) |
| #define I40E_GLPM_WUMC_MNG_WU_PF_SHIFT 16 |
| #define I40E_GLPM_WUMC_MNG_WU_PF_MASK (0xFFFF << I40E_GLPM_WUMC_MNG_WU_PF_SHIFT) |
| #define I40E_PFPM_APM 0x000B8080 |
| #define I40E_PFPM_APM_APME_SHIFT 0 |
| #define I40E_PFPM_APM_APME_MASK (0x1 << I40E_PFPM_APM_APME_SHIFT) |
| #define I40E_PFPM_FHFT_LENGTH(_i) (0x0006A000 + ((_i) * 128)) /* _i=0...7 */ |
| #define I40E_PFPM_FHFT_LENGTH_MAX_INDEX 7 |
| #define I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT 0 |
| #define I40E_PFPM_FHFT_LENGTH_LENGTH_MASK (0xFF << I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT) |
| #define I40E_PFPM_WUC 0x0006B200 |
| #define I40E_PFPM_WUC_EN_APM_D0_SHIFT 5 |
| #define I40E_PFPM_WUC_EN_APM_D0_MASK (0x1 << I40E_PFPM_WUC_EN_APM_D0_SHIFT) |
| #define I40E_PFPM_WUFC 0x0006B400 |
| #define I40E_PFPM_WUFC_LNKC_SHIFT 0 |
| #define I40E_PFPM_WUFC_LNKC_MASK (0x1 << I40E_PFPM_WUFC_LNKC_SHIFT) |
| #define I40E_PFPM_WUFC_MAG_SHIFT 1 |
| #define I40E_PFPM_WUFC_MAG_MASK (0x1 << I40E_PFPM_WUFC_MAG_SHIFT) |
| #define I40E_PFPM_WUFC_MNG_SHIFT 3 |
| #define I40E_PFPM_WUFC_MNG_MASK (0x1 << I40E_PFPM_WUFC_MNG_SHIFT) |
| #define I40E_PFPM_WUFC_FLX0_ACT_SHIFT 4 |
| #define I40E_PFPM_WUFC_FLX0_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX0_ACT_SHIFT) |
| #define I40E_PFPM_WUFC_FLX1_ACT_SHIFT 5 |
| #define I40E_PFPM_WUFC_FLX1_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX1_ACT_SHIFT) |
| #define I40E_PFPM_WUFC_FLX2_ACT_SHIFT 6 |
| #define I40E_PFPM_WUFC_FLX2_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX2_ACT_SHIFT) |
| #define I40E_PFPM_WUFC_FLX3_ACT_SHIFT 7 |
| #define I40E_PFPM_WUFC_FLX3_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX3_ACT_SHIFT) |
| #define I40E_PFPM_WUFC_FLX4_ACT_SHIFT 8 |
| #define I40E_PFPM_WUFC_FLX4_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX4_ACT_SHIFT) |
| #define I40E_PFPM_WUFC_FLX5_ACT_SHIFT 9 |
| #define I40E_PFPM_WUFC_FLX5_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX5_ACT_SHIFT) |
| #define I40E_PFPM_WUFC_FLX6_ACT_SHIFT 10 |
| #define I40E_PFPM_WUFC_FLX6_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX6_ACT_SHIFT) |
| #define I40E_PFPM_WUFC_FLX7_ACT_SHIFT 11 |
| #define I40E_PFPM_WUFC_FLX7_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX7_ACT_SHIFT) |
| #define I40E_PFPM_WUFC_FLX0_SHIFT 16 |
| #define I40E_PFPM_WUFC_FLX0_MASK (0x1 << I40E_PFPM_WUFC_FLX0_SHIFT) |
| #define I40E_PFPM_WUFC_FLX1_SHIFT 17 |
| #define I40E_PFPM_WUFC_FLX1_MASK (0x1 << I40E_PFPM_WUFC_FLX1_SHIFT) |
| #define I40E_PFPM_WUFC_FLX2_SHIFT 18 |
| #define I40E_PFPM_WUFC_FLX2_MASK (0x1 << I40E_PFPM_WUFC_FLX2_SHIFT) |
| #define I40E_PFPM_WUFC_FLX3_SHIFT 19 |
| #define I40E_PFPM_WUFC_FLX3_MASK (0x1 << I40E_PFPM_WUFC_FLX3_SHIFT) |
| #define I40E_PFPM_WUFC_FLX4_SHIFT 20 |
| #define I40E_PFPM_WUFC_FLX4_MASK (0x1 << I40E_PFPM_WUFC_FLX4_SHIFT) |
| #define I40E_PFPM_WUFC_FLX5_SHIFT 21 |
| #define I40E_PFPM_WUFC_FLX5_MASK (0x1 << I40E_PFPM_WUFC_FLX5_SHIFT) |
| #define I40E_PFPM_WUFC_FLX6_SHIFT 22 |
| #define I40E_PFPM_WUFC_FLX6_MASK (0x1 << I40E_PFPM_WUFC_FLX6_SHIFT) |
| #define I40E_PFPM_WUFC_FLX7_SHIFT 23 |
| #define I40E_PFPM_WUFC_FLX7_MASK (0x1 << I40E_PFPM_WUFC_FLX7_SHIFT) |
| #define I40E_PFPM_WUFC_FW_RST_WK_SHIFT 31 |
| #define I40E_PFPM_WUFC_FW_RST_WK_MASK (0x1 << I40E_PFPM_WUFC_FW_RST_WK_SHIFT) |
| #define I40E_PFPM_WUS 0x0006B600 |
| #define I40E_PFPM_WUS_LNKC_SHIFT 0 |
| #define I40E_PFPM_WUS_LNKC_MASK (0x1 << I40E_PFPM_WUS_LNKC_SHIFT) |
| #define I40E_PFPM_WUS_MAG_SHIFT 1 |
| #define I40E_PFPM_WUS_MAG_MASK (0x1 << I40E_PFPM_WUS_MAG_SHIFT) |
| #define I40E_PFPM_WUS_PME_STATUS_SHIFT 2 |
| #define I40E_PFPM_WUS_PME_STATUS_MASK (0x1 << I40E_PFPM_WUS_PME_STATUS_SHIFT) |
| #define I40E_PFPM_WUS_MNG_SHIFT 3 |
| #define I40E_PFPM_WUS_MNG_MASK (0x1 << I40E_PFPM_WUS_MNG_SHIFT) |
| #define I40E_PFPM_WUS_FLX0_SHIFT 16 |
| #define I40E_PFPM_WUS_FLX0_MASK (0x1 << I40E_PFPM_WUS_FLX0_SHIFT) |
| #define I40E_PFPM_WUS_FLX1_SHIFT 17 |
| #define I40E_PFPM_WUS_FLX1_MASK (0x1 << I40E_PFPM_WUS_FLX1_SHIFT) |
| #define I40E_PFPM_WUS_FLX2_SHIFT 18 |
| #define I40E_PFPM_WUS_FLX2_MASK (0x1 << I40E_PFPM_WUS_FLX2_SHIFT) |
| #define I40E_PFPM_WUS_FLX3_SHIFT 19 |
| #define I40E_PFPM_WUS_FLX3_MASK (0x1 << I40E_PFPM_WUS_FLX3_SHIFT) |
| #define I40E_PFPM_WUS_FLX4_SHIFT 20 |
| #define I40E_PFPM_WUS_FLX4_MASK (0x1 << I40E_PFPM_WUS_FLX4_SHIFT) |
| #define I40E_PFPM_WUS_FLX5_SHIFT 21 |
| #define I40E_PFPM_WUS_FLX5_MASK (0x1 << I40E_PFPM_WUS_FLX5_SHIFT) |
| #define I40E_PFPM_WUS_FLX6_SHIFT 22 |
| #define I40E_PFPM_WUS_FLX6_MASK (0x1 << I40E_PFPM_WUS_FLX6_SHIFT) |
| #define I40E_PFPM_WUS_FLX7_SHIFT 23 |
| #define I40E_PFPM_WUS_FLX7_MASK (0x1 << I40E_PFPM_WUS_FLX7_SHIFT) |
| #define I40E_PFPM_WUS_FW_RST_WK_SHIFT 31 |
| #define I40E_PFPM_WUS_FW_RST_WK_MASK (0x1 << I40E_PFPM_WUS_FW_RST_WK_SHIFT) |
| #define I40E_PRTPM_FHFHR 0x0006C000 |
| #define I40E_PRTPM_FHFHR_UNICAST_SHIFT 0 |
| #define I40E_PRTPM_FHFHR_UNICAST_MASK (0x1 << I40E_PRTPM_FHFHR_UNICAST_SHIFT) |
| #define I40E_PRTPM_FHFHR_MULTICAST_SHIFT 1 |
| #define I40E_PRTPM_FHFHR_MULTICAST_MASK (0x1 << I40E_PRTPM_FHFHR_MULTICAST_SHIFT) |
| #define I40E_PRTPM_SAH(_i) (0x001E44C0 + ((_i) * 32)) /* _i=0...3 */ |
| #define I40E_PRTPM_SAH_MAX_INDEX 3 |
| #define I40E_PRTPM_SAH_PFPM_SAH_SHIFT 0 |
| #define I40E_PRTPM_SAH_PFPM_SAH_MASK (0xFFFF << I40E_PRTPM_SAH_PFPM_SAH_SHIFT) |
| #define I40E_PRTPM_SAH_PF_NUM_SHIFT 26 |
| #define I40E_PRTPM_SAH_PF_NUM_MASK (0xF << I40E_PRTPM_SAH_PF_NUM_SHIFT) |
| #define I40E_PRTPM_SAH_MC_MAG_EN_SHIFT 30 |
| #define I40E_PRTPM_SAH_MC_MAG_EN_MASK (0x1 << I40E_PRTPM_SAH_MC_MAG_EN_SHIFT) |
| #define I40E_PRTPM_SAH_AV_SHIFT 31 |
| #define I40E_PRTPM_SAH_AV_MASK (0x1 << I40E_PRTPM_SAH_AV_SHIFT) |
| #define I40E_PRTPM_SAL(_i) (0x001E4440 + ((_i) * 32)) /* _i=0...3 */ |
| #define I40E_PRTPM_SAL_MAX_INDEX 3 |
| #define I40E_PRTPM_SAL_PFPM_SAL_SHIFT 0 |
| #define I40E_PRTPM_SAL_PFPM_SAL_MASK (0xFFFFFFFF << I40E_PRTPM_SAL_PFPM_SAL_SHIFT) |
| #define I40E_VF_ARQBAH1 0x00006000 |
| #define I40E_VF_ARQBAH1_ARQBAH_SHIFT 0 |
| #define I40E_VF_ARQBAH1_ARQBAH_MASK (0xFFFFFFFF << I40E_VF_ARQBAH1_ARQBAH_SHIFT) |
| #define I40E_VF_ARQBAL1 0x00006C00 |
| #define I40E_VF_ARQBAL1_ARQBAL_SHIFT 0 |
| #define I40E_VF_ARQBAL1_ARQBAL_MASK (0xFFFFFFFF << I40E_VF_ARQBAL1_ARQBAL_SHIFT) |
| #define I40E_VF_ARQH1 0x00007400 |
| #define I40E_VF_ARQH1_ARQH_SHIFT 0 |
| #define I40E_VF_ARQH1_ARQH_MASK (0x3FF << I40E_VF_ARQH1_ARQH_SHIFT) |
| #define I40E_VF_ARQLEN1 0x00008000 |
| #define I40E_VF_ARQLEN1_ARQLEN_SHIFT 0 |
| #define I40E_VF_ARQLEN1_ARQLEN_MASK (0x3FF << I40E_VF_ARQLEN1_ARQLEN_SHIFT) |
| #define I40E_VF_ARQLEN1_ARQVFE_SHIFT 28 |
| #define I40E_VF_ARQLEN1_ARQVFE_MASK (0x1 << I40E_VF_ARQLEN1_ARQVFE_SHIFT) |
| #define I40E_VF_ARQLEN1_ARQOVFL_SHIFT 29 |
| #define I40E_VF_ARQLEN1_ARQOVFL_MASK (0x1 << I40E_VF_ARQLEN1_ARQOVFL_SHIFT) |
| #define I40E_VF_ARQLEN1_ARQCRIT_SHIFT 30 |
| #define I40E_VF_ARQLEN1_ARQCRIT_MASK (0x1 << I40E_VF_ARQLEN1_ARQCRIT_SHIFT) |
| #define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31 |
| #define I40E_VF_ARQLEN1_ARQENABLE_MASK (0x1 << I40E_VF_ARQLEN1_ARQENABLE_SHIFT) |
| #define I40E_VF_ARQT1 0x00007000 |
| #define I40E_VF_ARQT1_ARQT_SHIFT 0 |
| #define I40E_VF_ARQT1_ARQT_MASK (0x3FF << I40E_VF_ARQT1_ARQT_SHIFT) |
| #define I40E_VF_ATQBAH1 0x00007800 |
| #define I40E_VF_ATQBAH1_ATQBAH_SHIFT 0 |
| #define I40E_VF_ATQBAH1_ATQBAH_MASK (0xFFFFFFFF << I40E_VF_ATQBAH1_ATQBAH_SHIFT) |
| #define I40E_VF_ATQBAL1 0x00007C00 |
| #define I40E_VF_ATQBAL1_ATQBAL_SHIFT 0 |
| #define I40E_VF_ATQBAL1_ATQBAL_MASK (0xFFFFFFFF << I40E_VF_ATQBAL1_ATQBAL_SHIFT) |
| #define I40E_VF_ATQH1 0x00006400 |
| #define I40E_VF_ATQH1_ATQH_SHIFT 0 |
| #define I40E_VF_ATQH1_ATQH_MASK (0x3FF << I40E_VF_ATQH1_ATQH_SHIFT) |
| #define I40E_VF_ATQLEN1 0x00006800 |
| #define I40E_VF_ATQLEN1_ATQLEN_SHIFT 0 |
| #define I40E_VF_ATQLEN1_ATQLEN_MASK (0x3FF << I40E_VF_ATQLEN1_ATQLEN_SHIFT) |
| #define I40E_VF_ATQLEN1_ATQVFE_SHIFT 28 |
| #define I40E_VF_ATQLEN1_ATQVFE_MASK (0x1 << I40E_VF_ATQLEN1_ATQVFE_SHIFT) |
| #define I40E_VF_ATQLEN1_ATQOVFL_SHIFT 29 |
| #define I40E_VF_ATQLEN1_ATQOVFL_MASK (0x1 << I40E_VF_ATQLEN1_ATQOVFL_SHIFT) |
| #define I40E_VF_ATQLEN1_ATQCRIT_SHIFT 30 |
| #define I40E_VF_ATQLEN1_ATQCRIT_MASK (0x1 << I40E_VF_ATQLEN1_ATQCRIT_SHIFT) |
| #define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31 |
| #define I40E_VF_ATQLEN1_ATQENABLE_MASK (0x1 << I40E_VF_ATQLEN1_ATQENABLE_SHIFT) |
| #define I40E_VF_ATQT1 0x00008400 |
| #define I40E_VF_ATQT1_ATQT_SHIFT 0 |
| #define I40E_VF_ATQT1_ATQT_MASK (0x3FF << I40E_VF_ATQT1_ATQT_SHIFT) |
| #define I40E_VFGEN_RSTAT 0x00008800 |
| #define I40E_VFGEN_RSTAT_VFR_STATE_SHIFT 0 |
| #define I40E_VFGEN_RSTAT_VFR_STATE_MASK (0x3 << I40E_VFGEN_RSTAT_VFR_STATE_SHIFT) |
| #define I40E_VFINT_DYN_CTL01 0x00005C00 |
| #define I40E_VFINT_DYN_CTL01_INTENA_SHIFT 0 |
| #define I40E_VFINT_DYN_CTL01_INTENA_MASK (0x1 << I40E_VFINT_DYN_CTL01_INTENA_SHIFT) |
| #define I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT 1 |
| #define I40E_VFINT_DYN_CTL01_CLEARPBA_MASK (0x1 << I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT) |
| #define I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT 2 |
| #define I40E_VFINT_DYN_CTL01_SWINT_TRIG_MASK (0x1 << I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT) |
| #define I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT 3 |
| #define I40E_VFINT_DYN_CTL01_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
| #define I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT 5 |
| #define I40E_VFINT_DYN_CTL01_INTERVAL_MASK (0xFFF << I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT) |
| #define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT 24 |
| #define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_MASK (0x1 << I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT) |
| #define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT 25 |
| #define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT) |
| #define I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT 31 |
| #define I40E_VFINT_DYN_CTL01_INTENA_MSK_MASK (0x1 << I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT) |
| #define I40E_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) |
| #define I40E_VFINT_DYN_CTLN1_MAX_INDEX 15 |
| #define I40E_VFINT_DYN_CTLN1_INTENA_SHIFT 0 |
| #define I40E_VFINT_DYN_CTLN1_INTENA_MASK (0x1 << I40E_VFINT_DYN_CTLN1_INTENA_SHIFT) |
| #define I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT 1 |
| #define I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK (0x1 << I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT) |
| #define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2 |
| #define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK (0x1 << I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT) |
| #define I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT 3 |
| #define I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
| #define I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT 5 |
| #define I40E_VFINT_DYN_CTLN1_INTERVAL_MASK (0xFFF << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT) |
| #define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24 |
| #define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK (0x1 << I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT) |
| #define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT 25 |
| #define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT) |
| #define I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT 31 |
| #define I40E_VFINT_DYN_CTLN1_INTENA_MSK_MASK (0x1 << I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT) |
| #define I40E_VFINT_ICR0_ENA1 0x00005000 |
| #define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT 25 |
| #define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK (0x1 << I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT) |
| #define I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT 30 |
| #define I40E_VFINT_ICR0_ENA1_ADMINQ_MASK (0x1 << I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT) |
| #define I40E_VFINT_ICR0_ENA1_RSVD_SHIFT 31 |
| #define I40E_VFINT_ICR0_ENA1_RSVD_MASK (0x1 << I40E_VFINT_ICR0_ENA1_RSVD_SHIFT) |
| #define I40E_VFINT_ICR01 0x00004800 |
| #define I40E_VFINT_ICR01_INTEVENT_SHIFT 0 |
| #define I40E_VFINT_ICR01_INTEVENT_MASK (0x1 << I40E_VFINT_ICR01_INTEVENT_SHIFT) |
| #define I40E_VFINT_ICR01_QUEUE_0_SHIFT 1 |
| #define I40E_VFINT_ICR01_QUEUE_0_MASK (0x1 << I40E_VFINT_ICR01_QUEUE_0_SHIFT) |
| #define I40E_VFINT_ICR01_QUEUE_1_SHIFT 2 |
| #define I40E_VFINT_ICR01_QUEUE_1_MASK (0x1 << I40E_VFINT_ICR01_QUEUE_1_SHIFT) |
| #define I40E_VFINT_ICR01_QUEUE_2_SHIFT 3 |
| #define I40E_VFINT_ICR01_QUEUE_2_MASK (0x1 << I40E_VFINT_ICR01_QUEUE_2_SHIFT) |
| #define I40E_VFINT_ICR01_QUEUE_3_SHIFT 4 |
| #define I40E_VFINT_ICR01_QUEUE_3_MASK (0x1 << I40E_VFINT_ICR01_QUEUE_3_SHIFT) |
| #define I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT 25 |
| #define I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK (0x1 << I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT) |
| #define I40E_VFINT_ICR01_ADMINQ_SHIFT 30 |
| #define I40E_VFINT_ICR01_ADMINQ_MASK (0x1 << I40E_VFINT_ICR01_ADMINQ_SHIFT) |
| #define I40E_VFINT_ICR01_SWINT_SHIFT 31 |
| #define I40E_VFINT_ICR01_SWINT_MASK (0x1 << I40E_VFINT_ICR01_SWINT_SHIFT) |
| #define I40E_VFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ |
| #define I40E_VFINT_ITR01_MAX_INDEX 2 |
| #define I40E_VFINT_ITR01_INTERVAL_SHIFT 0 |
| #define I40E_VFINT_ITR01_INTERVAL_MASK (0xFFF << I40E_VFINT_ITR01_INTERVAL_SHIFT) |
| #define I40E_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) |
| #define I40E_VFINT_ITRN1_MAX_INDEX 2 |
| #define I40E_VFINT_ITRN1_INTERVAL_SHIFT 0 |
| #define I40E_VFINT_ITRN1_INTERVAL_MASK (0xFFF << I40E_VFINT_ITRN1_INTERVAL_SHIFT) |
| #define I40E_VFINT_STAT_CTL01 0x00005400 |
| #define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2 |
| #define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_MASK (0x3 << I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT) |
| #define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ |
| #define I40E_QRX_TAIL1_MAX_INDEX 15 |
| #define I40E_QRX_TAIL1_TAIL_SHIFT 0 |
| #define I40E_QRX_TAIL1_TAIL_MASK (0x1FFF << I40E_QRX_TAIL1_TAIL_SHIFT) |
| #define I40E_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ |
| #define I40E_QTX_TAIL1_MAX_INDEX 15 |
| #define I40E_QTX_TAIL1_TAIL_SHIFT 0 |
| #define I40E_QTX_TAIL1_TAIL_MASK (0x1FFF << I40E_QTX_TAIL1_TAIL_SHIFT) |
| #define I40E_VFMSIX_PBA 0x00002000 |
| #define I40E_VFMSIX_PBA_PENBIT_SHIFT 0 |
| #define I40E_VFMSIX_PBA_PENBIT_MASK (0xFFFFFFFF << I40E_VFMSIX_PBA_PENBIT_SHIFT) |
| #define I40E_VFMSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...16 */ |
| #define I40E_VFMSIX_TADD_MAX_INDEX 16 |
| #define I40E_VFMSIX_TADD_MSIXTADD10_SHIFT 0 |
| #define I40E_VFMSIX_TADD_MSIXTADD10_MASK (0x3 << I40E_VFMSIX_TADD_MSIXTADD10_SHIFT) |
| #define I40E_VFMSIX_TADD_MSIXTADD_SHIFT 2 |
| #define I40E_VFMSIX_TADD_MSIXTADD_MASK (0x3FFFFFFF << I40E_VFMSIX_TADD_MSIXTADD_SHIFT) |
| #define I40E_VFMSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...16 */ |
| #define I40E_VFMSIX_TMSG_MAX_INDEX 16 |
| #define I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT 0 |
| #define I40E_VFMSIX_TMSG_MSIXTMSG_MASK (0xFFFFFFFF << I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT) |
| #define I40E_VFMSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...16 */ |
| #define I40E_VFMSIX_TUADD_MAX_INDEX 16 |
| #define I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT 0 |
| #define I40E_VFMSIX_TUADD_MSIXTUADD_MASK (0xFFFFFFFF << I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT) |
| #define I40E_VFMSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...16 */ |
| #define I40E_VFMSIX_TVCTRL_MAX_INDEX 16 |
| #define I40E_VFMSIX_TVCTRL_MASK_SHIFT 0 |
| #define I40E_VFMSIX_TVCTRL_MASK_MASK (0x1 << I40E_VFMSIX_TVCTRL_MASK_SHIFT) |
| #define I40E_VFCM_PE_ERRDATA 0x0000DC00 |
| #define I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0 |
| #define I40E_VFCM_PE_ERRDATA_ERROR_CODE_MASK (0xF << I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT) |
| #define I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT 4 |
| #define I40E_VFCM_PE_ERRDATA_Q_TYPE_MASK (0x7 << I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT) |
| #define I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT 8 |
| #define I40E_VFCM_PE_ERRDATA_Q_NUM_MASK (0x3FFFF << I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT) |
| #define I40E_VFCM_PE_ERRINFO 0x0000D800 |
| #define I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0 |
| #define I40E_VFCM_PE_ERRINFO_ERROR_VALID_MASK (0x1 << I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT) |
| #define I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT 4 |
| #define I40E_VFCM_PE_ERRINFO_ERROR_INST_MASK (0x7 << I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT) |
| #define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8 |
| #define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK (0xFF << I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT) |
| #define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16 |
| #define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK (0xFF << I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT) |
| #define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24 |
| #define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK (0xFF << I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT) |
| #define I40E_VFPE_AEQALLOC1 0x0000A400 |
| #define I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT 0 |
| #define I40E_VFPE_AEQALLOC1_AECOUNT_MASK (0xFFFFFFFF << I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT) |
| #define I40E_VFPE_CCQPHIGH1 0x00009800 |
| #define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT 0 |
| #define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_MASK (0xFFFFFFFF << I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT) |
| #define I40E_VFPE_CCQPLOW1 0x0000AC00 |
| #define I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT 0 |
| #define I40E_VFPE_CCQPLOW1_PECCQPLOW_MASK (0xFFFFFFFF << I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT) |
| #define I40E_VFPE_CCQPSTATUS1 0x0000B800 |
| #define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT 0 |
| #define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_MASK (0x1 << I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT) |
| #define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT 31 |
| #define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_MASK (0x1 << I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT) |
| #define I40E_VFPE_CQACK1 0x0000B000 |
| #define I40E_VFPE_CQACK1_PECQID_SHIFT 0 |
| #define I40E_VFPE_CQACK1_PECQID_MASK (0x1FFFF << I40E_VFPE_CQACK1_PECQID_SHIFT) |
| #define I40E_VFPE_CQARM1 0x0000B400 |
| #define I40E_VFPE_CQARM1_PECQID_SHIFT 0 |
| #define I40E_VFPE_CQARM1_PECQID_MASK (0x1FFFF << I40E_VFPE_CQARM1_PECQID_SHIFT) |
| #define I40E_VFPE_CQPDB1 0x0000BC00 |
| #define I40E_VFPE_CQPDB1_WQHEAD_SHIFT 0 |
| #define I40E_VFPE_CQPDB1_WQHEAD_MASK (0x7FF << I40E_VFPE_CQPDB1_WQHEAD_SHIFT) |
| #define I40E_VFPE_CQPERRCODES1 0x00009C00 |
| #define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT 0 |
| #define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_MASK (0xFFFF << I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT) |
| #define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT 16 |
| #define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_MASK (0xFFFF << I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT) |
| #define I40E_VFPE_CQPTAIL1 0x0000A000 |
| #define I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT 0 |
| #define I40E_VFPE_CQPTAIL1_WQTAIL_MASK (0x7FF << I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT) |
| #define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT 31 |
| #define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_MASK (0x1 << I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT) |
| #define I40E_VFPE_IPCONFIG01 0x00008C00 |
| #define I40E_VFPE_IPCONFIG01_PEIPID_SHIFT 0 |
| #define I40E_VFPE_IPCONFIG01_PEIPID_MASK (0xFFFF << I40E_VFPE_IPCONFIG01_PEIPID_SHIFT) |
| #define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT 16 |
| #define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_MASK (0x1 << I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT) |
| #define I40E_VFPE_MRTEIDXMASK1 0x00009000 |
| #define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT 0 |
| #define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_MASK (0x1F << I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT) |
| #define I40E_VFPE_RCVUNEXPECTEDERROR1 0x00009400 |
| #define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT 0 |
| #define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_MASK (0xFFFFFF << I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT) |
| #define I40E_VFPE_TCPNOWTIMER1 0x0000A800 |
| #define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT 0 |
| #define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_MASK (0xFFFFFFFF << I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT) |
| #define I40E_VFPE_WQEALLOC1 0x0000C000 |
| #define I40E_VFPE_WQEALLOC1_PEQPID_SHIFT 0 |
| #define I40E_VFPE_WQEALLOC1_PEQPID_MASK (0x3FFFF << I40E_VFPE_WQEALLOC1_PEQPID_SHIFT) |
| #define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT 20 |
| #define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_MASK (0xFFF << I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT) |
| #define I40E_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ |
| #define I40E_VFQF_HENA_MAX_INDEX 1 |
| #define I40E_VFQF_HENA_PTYPE_ENA_SHIFT 0 |
| #define I40E_VFQF_HENA_PTYPE_ENA_MASK (0xFFFFFFFF << I40E_VFQF_HENA_PTYPE_ENA_SHIFT) |
| #define I40E_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ |
| #define I40E_VFQF_HKEY_MAX_INDEX 12 |
| #define I40E_VFQF_HKEY_KEY_0_SHIFT 0 |
| #define I40E_VFQF_HKEY_KEY_0_MASK (0xFF << I40E_VFQF_HKEY_KEY_0_SHIFT) |
| #define I40E_VFQF_HKEY_KEY_1_SHIFT 8 |
| #define I40E_VFQF_HKEY_KEY_1_MASK (0xFF << I40E_VFQF_HKEY_KEY_1_SHIFT) |
| #define I40E_VFQF_HKEY_KEY_2_SHIFT 16 |
| #define I40E_VFQF_HKEY_KEY_2_MASK (0xFF << I40E_VFQF_HKEY_KEY_2_SHIFT) |
| #define I40E_VFQF_HKEY_KEY_3_SHIFT 24 |
| #define I40E_VFQF_HKEY_KEY_3_MASK (0xFF << I40E_VFQF_HKEY_KEY_3_SHIFT) |
| #define I40E_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ |
| #define I40E_VFQF_HLUT_MAX_INDEX 15 |
| #define I40E_VFQF_HLUT_LUT0_SHIFT 0 |
| #define I40E_VFQF_HLUT_LUT0_MASK (0xF << I40E_VFQF_HLUT_LUT0_SHIFT) |
| #define I40E_VFQF_HLUT_LUT1_SHIFT 8 |
| #define I40E_VFQF_HLUT_LUT1_MASK (0xF << I40E_VFQF_HLUT_LUT1_SHIFT) |
| #define I40E_VFQF_HLUT_LUT2_SHIFT 16 |
| #define I40E_VFQF_HLUT_LUT2_MASK (0xF << I40E_VFQF_HLUT_LUT2_SHIFT) |
| #define I40E_VFQF_HLUT_LUT3_SHIFT 24 |
| #define I40E_VFQF_HLUT_LUT3_MASK (0xF << I40E_VFQF_HLUT_LUT3_SHIFT) |
| #define I40E_VFQF_HREGION(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...7 */ |
| #define I40E_VFQF_HREGION_MAX_INDEX 7 |
| #define I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0 |
| #define I40E_VFQF_HREGION_OVERRIDE_ENA_0_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT) |
| #define I40E_VFQF_HREGION_REGION_0_SHIFT 1 |
| #define I40E_VFQF_HREGION_REGION_0_MASK (0x7 << I40E_VFQF_HREGION_REGION_0_SHIFT) |
| #define I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4 |
| #define I40E_VFQF_HREGION_OVERRIDE_ENA_1_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT) |
| #define I40E_VFQF_HREGION_REGION_1_SHIFT 5 |
| #define I40E_VFQF_HREGION_REGION_1_MASK (0x7 << I40E_VFQF_HREGION_REGION_1_SHIFT) |
| #define I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8 |
| #define I40E_VFQF_HREGION_OVERRIDE_ENA_2_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT) |
| #define I40E_VFQF_HREGION_REGION_2_SHIFT 9 |
| #define I40E_VFQF_HREGION_REGION_2_MASK (0x7 << I40E_VFQF_HREGION_REGION_2_SHIFT) |
| #define I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12 |
| #define I40E_VFQF_HREGION_OVERRIDE_ENA_3_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT) |
| #define I40E_VFQF_HREGION_REGION_3_SHIFT 13 |
| #define I40E_VFQF_HREGION_REGION_3_MASK (0x7 << I40E_VFQF_HREGION_REGION_3_SHIFT) |
| #define I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16 |
| #define I40E_VFQF_HREGION_OVERRIDE_ENA_4_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT) |
| #define I40E_VFQF_HREGION_REGION_4_SHIFT 17 |
| #define I40E_VFQF_HREGION_REGION_4_MASK (0x7 << I40E_VFQF_HREGION_REGION_4_SHIFT) |
| #define I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20 |
| #define I40E_VFQF_HREGION_OVERRIDE_ENA_5_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT) |
| #define I40E_VFQF_HREGION_REGION_5_SHIFT 21 |
| #define I40E_VFQF_HREGION_REGION_5_MASK (0x7 << I40E_VFQF_HREGION_REGION_5_SHIFT) |
| #define I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24 |
| #define I40E_VFQF_HREGION_OVERRIDE_ENA_6_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT) |
| #define I40E_VFQF_HREGION_REGION_6_SHIFT 25 |
| #define I40E_VFQF_HREGION_REGION_6_MASK (0x7 << I40E_VFQF_HREGION_REGION_6_SHIFT) |
| #define I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28 |
| #define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT) |
| #define I40E_VFQF_HREGION_REGION_7_SHIFT 29 |
| #define I40E_VFQF_HREGION_REGION_7_MASK (0x7 << I40E_VFQF_HREGION_REGION_7_SHIFT) |
| #define I40E_RCU_PST_FOC_ACCESS_STATUS 0x00270110 |
| #define I40E_RCU_PST_FOC_ACCESS_STATUS_WR_ACCESS_CNT_SHIFT 0 |
| #define I40E_RCU_PST_FOC_ACCESS_STATUS_WR_ACCESS_CNT_MASK (0xFF << I40E_RCU_PST_FOC_ACCESS_STATUS_WR_ACCESS_CNT_SHIFT) |
| #define I40E_RCU_PST_FOC_ACCESS_STATUS_RD_ACCESS_CNT_SHIFT 8 |
| #define I40E_RCU_PST_FOC_ACCESS_STATUS_RD_ACCESS_CNT_MASK (0xFF << I40E_RCU_PST_FOC_ACCESS_STATUS_RD_ACCESS_CNT_SHIFT) |
| #define I40E_RCU_PST_FOC_ACCESS_STATUS_ERR_CNT_SHIFT 16 |
| #define I40E_RCU_PST_FOC_ACCESS_STATUS_ERR_CNT_MASK (0xFF << I40E_RCU_PST_FOC_ACCESS_STATUS_ERR_CNT_SHIFT) |
| #define I40E_RCU_PST_FOC_ACCESS_STATUS_LAST_ERR_CODE_SHIFT 24 |
| #define I40E_RCU_PST_FOC_ACCESS_STATUS_LAST_ERR_CODE_MASK (0x7 << I40E_RCU_PST_FOC_ACCESS_STATUS_LAST_ERR_CODE_SHIFT) |
| #endif |
