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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * arch/sh/mm/cache-sh7705.c
3 *
4 * Copyright (C) 1999, 2000 Niibe Yutaka
5 * Copyright (C) 2004 Alex Song
Paul Mundt26b7a782006-12-28 10:31:48 +09006 * Copyright (C) 2006 Paul Mundt
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
Linus Torvalds1da177e2005-04-16 15:20:36 -070011 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070012#include <linux/init.h>
13#include <linux/mman.h>
14#include <linux/mm.h>
15#include <linux/threads.h>
16#include <asm/addrspace.h>
17#include <asm/page.h>
18#include <asm/pgtable.h>
19#include <asm/processor.h>
20#include <asm/cache.h>
21#include <asm/io.h>
22#include <asm/uaccess.h>
23#include <asm/pgalloc.h>
24#include <asm/mmu_context.h>
25#include <asm/cacheflush.h>
26
Paul Mundt0f08f332006-09-27 17:03:56 +090027/*
28 * The 32KB cache on the SH7705 suffers from the same synonym problem
29 * as SH4 CPUs
30 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070031static inline void cache_wback_all(void)
32{
33 unsigned long ways, waysize, addrstart;
34
Paul Mundt11c19652006-12-25 10:19:56 +090035 ways = current_cpu_data.dcache.ways;
36 waysize = current_cpu_data.dcache.sets;
37 waysize <<= current_cpu_data.dcache.entry_shift;
Linus Torvalds1da177e2005-04-16 15:20:36 -070038
39 addrstart = CACHE_OC_ADDRESS_ARRAY;
40
41 do {
42 unsigned long addr;
43
44 for (addr = addrstart;
45 addr < addrstart + waysize;
Paul Mundt11c19652006-12-25 10:19:56 +090046 addr += current_cpu_data.dcache.linesz) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070047 unsigned long data;
48 int v = SH_CACHE_UPDATED | SH_CACHE_VALID;
49
50 data = ctrl_inl(addr);
51
52 if ((data & v) == v)
53 ctrl_outl(data & ~v, addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -070054 }
55
Paul Mundt11c19652006-12-25 10:19:56 +090056 addrstart += current_cpu_data.dcache.way_incr;
Linus Torvalds1da177e2005-04-16 15:20:36 -070057 } while (--ways);
58}
59
60/*
61 * Write back the range of D-cache, and purge the I-cache.
62 *
63 * Called from kernel/module.c:sys_init_module and routine for a.out format.
64 */
65void flush_icache_range(unsigned long start, unsigned long end)
66{
67 __flush_wback_region((void *)start, end - start);
68}
69
Linus Torvalds1da177e2005-04-16 15:20:36 -070070/*
71 * Writeback&Invalidate the D-cache of the page
72 */
73static void __flush_dcache_page(unsigned long phys)
74{
75 unsigned long ways, waysize, addrstart;
76 unsigned long flags;
77
78 phys |= SH_CACHE_VALID;
79
80 /*
81 * Here, phys is the physical address of the page. We check all the
82 * tags in the cache for those with the same page number as this page
83 * (by masking off the lowest 2 bits of the 19-bit tag; these bits are
84 * derived from the offset within in the 4k page). Matching valid
85 * entries are invalidated.
86 *
87 * Since 2 bits of the cache index are derived from the virtual page
88 * number, knowing this would reduce the number of cache entries to be
89 * searched by a factor of 4. However this function exists to deal with
90 * potential cache aliasing, therefore the optimisation is probably not
91 * possible.
92 */
93 local_irq_save(flags);
94 jump_to_P2();
95
Paul Mundt11c19652006-12-25 10:19:56 +090096 ways = current_cpu_data.dcache.ways;
97 waysize = current_cpu_data.dcache.sets;
98 waysize <<= current_cpu_data.dcache.entry_shift;
Linus Torvalds1da177e2005-04-16 15:20:36 -070099
100 addrstart = CACHE_OC_ADDRESS_ARRAY;
101
102 do {
103 unsigned long addr;
104
105 for (addr = addrstart;
106 addr < addrstart + waysize;
Paul Mundt11c19652006-12-25 10:19:56 +0900107 addr += current_cpu_data.dcache.linesz) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700108 unsigned long data;
109
110 data = ctrl_inl(addr) & (0x1ffffC00 | SH_CACHE_VALID);
111 if (data == phys) {
112 data &= ~(SH_CACHE_VALID | SH_CACHE_UPDATED);
113 ctrl_outl(data, addr);
114 }
115 }
116
Paul Mundt11c19652006-12-25 10:19:56 +0900117 addrstart += current_cpu_data.dcache.way_incr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118 } while (--ways);
119
120 back_to_P1();
121 local_irq_restore(flags);
122}
123
Linus Torvalds1da177e2005-04-16 15:20:36 -0700124/*
125 * Write back & invalidate the D-cache of the page.
126 * (To avoid "alias" issues)
127 */
128void flush_dcache_page(struct page *page)
129{
Paul Mundt26b7a782006-12-28 10:31:48 +0900130 struct address_space *mapping = page_mapping(page);
131
132 if (mapping && !mapping_mapped(mapping))
133 set_bit(PG_dcache_dirty, &page->flags);
134 else
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135 __flush_dcache_page(PHYSADDR(page_address(page)));
136}
137
138void flush_cache_all(void)
139{
140 unsigned long flags;
141
142 local_irq_save(flags);
143 jump_to_P2();
144
145 cache_wback_all();
146 back_to_P1();
147 local_irq_restore(flags);
148}
149
150void flush_cache_mm(struct mm_struct *mm)
151{
152 /* Is there any good way? */
153 /* XXX: possibly call flush_cache_range for each vm area */
154 flush_cache_all();
155}
156
157/*
158 * Write back and invalidate D-caches.
159 *
160 * START, END: Virtual Address (U0 address)
161 *
162 * NOTE: We need to flush the _physical_ page entry.
163 * Flushing the cache lines for U0 only isn't enough.
164 * We need to flush for P1 too, which may contain aliases.
165 */
166void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
167 unsigned long end)
168{
169
170 /*
171 * We could call flush_cache_page for the pages of these range,
172 * but it's not efficient (scan the caches all the time...).
173 *
174 * We can't use A-bit magic, as there's the case we don't have
175 * valid entry on TLB.
176 */
177 flush_cache_all();
178}
179
180/*
181 * Write back and invalidate I/D-caches for the page.
182 *
183 * ADDRESS: Virtual Address (U0 address)
184 */
Paul Mundt0f08f332006-09-27 17:03:56 +0900185void flush_cache_page(struct vm_area_struct *vma, unsigned long address,
186 unsigned long pfn)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700187{
188 __flush_dcache_page(pfn << PAGE_SHIFT);
189}
190
191/*
192 * This is called when a page-cache page is about to be mapped into a
193 * user process' address space. It offers an opportunity for a
194 * port to ensure d-cache/i-cache coherency if necessary.
195 *
196 * Not entirely sure why this is necessary on SH3 with 32K cache but
197 * without it we get occasional "Memory fault" when loading a program.
198 */
199void flush_icache_page(struct vm_area_struct *vma, struct page *page)
200{
201 __flush_purge_region(page_address(page), PAGE_SIZE);
202}