Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
Jesse Barnes | d765898 | 2009-06-05 14:41:29 +0000 | [diff] [blame] | 28 | #include <linux/acpi.h> |
| 29 | #include <linux/pnp.h> |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 30 | #include "linux/string.h" |
| 31 | #include "linux/bitops.h" |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 32 | #include "drmP.h" |
| 33 | #include "drm.h" |
| 34 | #include "i915_drm.h" |
| 35 | #include "i915_drv.h" |
| 36 | |
| 37 | /** @file i915_gem_tiling.c |
| 38 | * |
| 39 | * Support for managing tiling state of buffer objects. |
| 40 | * |
| 41 | * The idea behind tiling is to increase cache hit rates by rearranging |
| 42 | * pixel data so that a group of pixel accesses are in the same cacheline. |
| 43 | * Performance improvement from doing this on the back/depth buffer are on |
| 44 | * the order of 30%. |
| 45 | * |
| 46 | * Intel architectures make this somewhat more complicated, though, by |
| 47 | * adjustments made to addressing of data when the memory is in interleaved |
| 48 | * mode (matched pairs of DIMMS) to improve memory bandwidth. |
| 49 | * For interleaved memory, the CPU sends every sequential 64 bytes |
| 50 | * to an alternate memory channel so it can get the bandwidth from both. |
| 51 | * |
| 52 | * The GPU also rearranges its accesses for increased bandwidth to interleaved |
| 53 | * memory, and it matches what the CPU does for non-tiled. However, when tiled |
| 54 | * it does it a little differently, since one walks addresses not just in the |
| 55 | * X direction but also Y. So, along with alternating channels when bit |
| 56 | * 6 of the address flips, it also alternates when other bits flip -- Bits 9 |
| 57 | * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines) |
| 58 | * are common to both the 915 and 965-class hardware. |
| 59 | * |
| 60 | * The CPU also sometimes XORs in higher bits as well, to improve |
| 61 | * bandwidth doing strided access like we do so frequently in graphics. This |
| 62 | * is called "Channel XOR Randomization" in the MCH documentation. The result |
| 63 | * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address |
| 64 | * decode. |
| 65 | * |
| 66 | * All of this bit 6 XORing has an effect on our memory management, |
| 67 | * as we need to make sure that the 3d driver can correctly address object |
| 68 | * contents. |
| 69 | * |
| 70 | * If we don't have interleaved memory, all tiling is safe and no swizzling is |
| 71 | * required. |
| 72 | * |
| 73 | * When bit 17 is XORed in, we simply refuse to tile at all. Bit |
| 74 | * 17 is not just a page offset, so as we page an objet out and back in, |
| 75 | * individual pages in it will have different bit 17 addresses, resulting in |
| 76 | * each 64 bytes being swapped with its neighbor! |
| 77 | * |
| 78 | * Otherwise, if interleaved, we have to tell the 3d driver what the address |
| 79 | * swizzling it needs to do is, since it's writing with the CPU to the pages |
| 80 | * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the |
| 81 | * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling |
| 82 | * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order |
| 83 | * to match what the GPU expects. |
| 84 | */ |
| 85 | |
Jesse Barnes | d765898 | 2009-06-05 14:41:29 +0000 | [diff] [blame] | 86 | #define MCHBAR_I915 0x44 |
| 87 | #define MCHBAR_I965 0x48 |
| 88 | #define MCHBAR_SIZE (4*4096) |
| 89 | |
| 90 | #define DEVEN_REG 0x54 |
| 91 | #define DEVEN_MCHBAR_EN (1 << 28) |
| 92 | |
| 93 | /* Allocate space for the MCH regs if needed, return nonzero on error */ |
| 94 | static int |
| 95 | intel_alloc_mchbar_resource(struct drm_device *dev) |
| 96 | { |
| 97 | struct pci_dev *bridge_dev; |
| 98 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 99 | int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; |
| 100 | u32 temp_lo, temp_hi = 0; |
| 101 | u64 mchbar_addr; |
| 102 | int ret = 0; |
| 103 | |
| 104 | bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); |
| 105 | if (!bridge_dev) { |
| 106 | DRM_DEBUG("no bridge dev?!\n"); |
| 107 | ret = -ENODEV; |
| 108 | goto out; |
| 109 | } |
| 110 | |
| 111 | if (IS_I965G(dev)) |
| 112 | pci_read_config_dword(bridge_dev, reg + 4, &temp_hi); |
| 113 | pci_read_config_dword(bridge_dev, reg, &temp_lo); |
| 114 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; |
| 115 | |
| 116 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ |
| 117 | if (mchbar_addr && |
| 118 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) { |
| 119 | ret = 0; |
| 120 | goto out_put; |
| 121 | } |
| 122 | |
| 123 | /* Get some space for it */ |
| 124 | ret = pci_bus_alloc_resource(bridge_dev->bus, &dev_priv->mch_res, |
| 125 | MCHBAR_SIZE, MCHBAR_SIZE, |
| 126 | PCIBIOS_MIN_MEM, |
| 127 | 0, pcibios_align_resource, |
| 128 | bridge_dev); |
| 129 | if (ret) { |
| 130 | DRM_DEBUG("failed bus alloc: %d\n", ret); |
| 131 | dev_priv->mch_res.start = 0; |
| 132 | goto out_put; |
| 133 | } |
| 134 | |
| 135 | if (IS_I965G(dev)) |
| 136 | pci_write_config_dword(bridge_dev, reg + 4, |
| 137 | upper_32_bits(dev_priv->mch_res.start)); |
| 138 | |
| 139 | pci_write_config_dword(bridge_dev, reg, |
| 140 | lower_32_bits(dev_priv->mch_res.start)); |
| 141 | out_put: |
| 142 | pci_dev_put(bridge_dev); |
| 143 | out: |
| 144 | return ret; |
| 145 | } |
| 146 | |
| 147 | /* Setup MCHBAR if possible, return true if we should disable it again */ |
| 148 | static bool |
| 149 | intel_setup_mchbar(struct drm_device *dev) |
| 150 | { |
| 151 | struct pci_dev *bridge_dev; |
| 152 | int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; |
| 153 | u32 temp; |
| 154 | bool need_disable = false, enabled; |
| 155 | |
| 156 | bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); |
| 157 | if (!bridge_dev) { |
| 158 | DRM_DEBUG("no bridge dev?!\n"); |
| 159 | goto out; |
| 160 | } |
| 161 | |
| 162 | if (IS_I915G(dev) || IS_I915GM(dev)) { |
| 163 | pci_read_config_dword(bridge_dev, DEVEN_REG, &temp); |
| 164 | enabled = !!(temp & DEVEN_MCHBAR_EN); |
| 165 | } else { |
| 166 | pci_read_config_dword(bridge_dev, mchbar_reg, &temp); |
| 167 | enabled = temp & 1; |
| 168 | } |
| 169 | |
| 170 | /* If it's already enabled, don't have to do anything */ |
| 171 | if (enabled) |
| 172 | goto out_put; |
| 173 | |
| 174 | if (intel_alloc_mchbar_resource(dev)) |
| 175 | goto out_put; |
| 176 | |
| 177 | need_disable = true; |
| 178 | |
| 179 | /* Space is allocated or reserved, so enable it. */ |
| 180 | if (IS_I915G(dev) || IS_I915GM(dev)) { |
| 181 | pci_write_config_dword(bridge_dev, DEVEN_REG, |
| 182 | temp | DEVEN_MCHBAR_EN); |
| 183 | } else { |
| 184 | pci_read_config_dword(bridge_dev, mchbar_reg, &temp); |
| 185 | pci_write_config_dword(bridge_dev, mchbar_reg, temp | 1); |
| 186 | } |
| 187 | out_put: |
| 188 | pci_dev_put(bridge_dev); |
| 189 | out: |
| 190 | return need_disable; |
| 191 | } |
| 192 | |
| 193 | static void |
| 194 | intel_teardown_mchbar(struct drm_device *dev, bool disable) |
| 195 | { |
| 196 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 197 | struct pci_dev *bridge_dev; |
| 198 | int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; |
| 199 | u32 temp; |
| 200 | |
| 201 | bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); |
| 202 | if (!bridge_dev) { |
| 203 | DRM_DEBUG("no bridge dev?!\n"); |
| 204 | return; |
| 205 | } |
| 206 | |
| 207 | if (disable) { |
| 208 | if (IS_I915G(dev) || IS_I915GM(dev)) { |
| 209 | pci_read_config_dword(bridge_dev, DEVEN_REG, &temp); |
| 210 | temp &= ~DEVEN_MCHBAR_EN; |
| 211 | pci_write_config_dword(bridge_dev, DEVEN_REG, temp); |
| 212 | } else { |
| 213 | pci_read_config_dword(bridge_dev, mchbar_reg, &temp); |
| 214 | temp &= ~1; |
| 215 | pci_write_config_dword(bridge_dev, mchbar_reg, temp); |
| 216 | } |
| 217 | } |
| 218 | |
| 219 | if (dev_priv->mch_res.start) |
| 220 | release_resource(&dev_priv->mch_res); |
| 221 | } |
| 222 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 223 | /** |
| 224 | * Detects bit 6 swizzling of address lookup between IGD access and CPU |
| 225 | * access through main memory. |
| 226 | */ |
| 227 | void |
| 228 | i915_gem_detect_bit_6_swizzle(struct drm_device *dev) |
| 229 | { |
| 230 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 231 | uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; |
| 232 | uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; |
Jesse Barnes | d765898 | 2009-06-05 14:41:29 +0000 | [diff] [blame] | 233 | bool need_disable; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 234 | |
| 235 | if (!IS_I9XX(dev)) { |
| 236 | /* As far as we know, the 865 doesn't have these bit 6 |
| 237 | * swizzling issues. |
| 238 | */ |
| 239 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; |
| 240 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; |
Eric Anholt | 568d9a8 | 2009-03-12 16:27:11 -0700 | [diff] [blame] | 241 | } else if (IS_MOBILE(dev)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 242 | uint32_t dcc; |
| 243 | |
Jesse Barnes | d765898 | 2009-06-05 14:41:29 +0000 | [diff] [blame] | 244 | /* Try to make sure MCHBAR is enabled before poking at it */ |
| 245 | need_disable = intel_setup_mchbar(dev); |
| 246 | |
Eric Anholt | 568d9a8 | 2009-03-12 16:27:11 -0700 | [diff] [blame] | 247 | /* On mobile 9xx chipsets, channel interleave by the CPU is |
| 248 | * determined by DCC. For single-channel, neither the CPU |
| 249 | * nor the GPU do swizzling. For dual channel interleaved, |
| 250 | * the GPU's interleave is bit 9 and 10 for X tiled, and bit |
| 251 | * 9 for Y tiled. The CPU's interleave is independent, and |
| 252 | * can be based on either bit 11 (haven't seen this yet) or |
| 253 | * bit 17 (common). |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 254 | */ |
| 255 | dcc = I915_READ(DCC); |
| 256 | switch (dcc & DCC_ADDRESSING_MODE_MASK) { |
| 257 | case DCC_ADDRESSING_MODE_SINGLE_CHANNEL: |
| 258 | case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC: |
| 259 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; |
| 260 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; |
| 261 | break; |
| 262 | case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED: |
Eric Anholt | 568d9a8 | 2009-03-12 16:27:11 -0700 | [diff] [blame] | 263 | if (dcc & DCC_CHANNEL_XOR_DISABLE) { |
| 264 | /* This is the base swizzling by the GPU for |
| 265 | * tiled buffers. |
| 266 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 267 | swizzle_x = I915_BIT_6_SWIZZLE_9_10; |
| 268 | swizzle_y = I915_BIT_6_SWIZZLE_9; |
Eric Anholt | 568d9a8 | 2009-03-12 16:27:11 -0700 | [diff] [blame] | 269 | } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) { |
| 270 | /* Bit 11 swizzling by the CPU in addition. */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 271 | swizzle_x = I915_BIT_6_SWIZZLE_9_10_11; |
| 272 | swizzle_y = I915_BIT_6_SWIZZLE_9_11; |
| 273 | } else { |
Eric Anholt | 568d9a8 | 2009-03-12 16:27:11 -0700 | [diff] [blame] | 274 | /* Bit 17 swizzling by the CPU in addition. */ |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 275 | swizzle_x = I915_BIT_6_SWIZZLE_9_10_17; |
| 276 | swizzle_y = I915_BIT_6_SWIZZLE_9_17; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 277 | } |
| 278 | break; |
| 279 | } |
| 280 | if (dcc == 0xffffffff) { |
| 281 | DRM_ERROR("Couldn't read from MCHBAR. " |
| 282 | "Disabling tiling.\n"); |
| 283 | swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; |
| 284 | swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; |
| 285 | } |
Jesse Barnes | d765898 | 2009-06-05 14:41:29 +0000 | [diff] [blame] | 286 | |
| 287 | intel_teardown_mchbar(dev, need_disable); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 288 | } else { |
| 289 | /* The 965, G33, and newer, have a very flexible memory |
| 290 | * configuration. It will enable dual-channel mode |
| 291 | * (interleaving) on as much memory as it can, and the GPU |
| 292 | * will additionally sometimes enable different bit 6 |
| 293 | * swizzling for tiled objects from the CPU. |
| 294 | * |
| 295 | * Here's what I found on the G965: |
| 296 | * slot fill memory size swizzling |
| 297 | * 0A 0B 1A 1B 1-ch 2-ch |
| 298 | * 512 0 0 0 512 0 O |
| 299 | * 512 0 512 0 16 1008 X |
| 300 | * 512 0 0 512 16 1008 X |
| 301 | * 0 512 0 512 16 1008 X |
| 302 | * 1024 1024 1024 0 2048 1024 O |
| 303 | * |
| 304 | * We could probably detect this based on either the DRB |
| 305 | * matching, which was the case for the swizzling required in |
| 306 | * the table above, or from the 1-ch value being less than |
| 307 | * the minimum size of a rank. |
| 308 | */ |
| 309 | if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) { |
| 310 | swizzle_x = I915_BIT_6_SWIZZLE_NONE; |
| 311 | swizzle_y = I915_BIT_6_SWIZZLE_NONE; |
| 312 | } else { |
| 313 | swizzle_x = I915_BIT_6_SWIZZLE_9_10; |
| 314 | swizzle_y = I915_BIT_6_SWIZZLE_9; |
| 315 | } |
| 316 | } |
| 317 | |
Zhenyu Wang | 2cce0d8 | 2009-06-05 15:38:41 +0800 | [diff] [blame] | 318 | /* FIXME: check with memory config on IGDNG */ |
| 319 | if (IS_IGDNG(dev)) { |
| 320 | DRM_ERROR("disable tiling on IGDNG...\n"); |
| 321 | swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; |
| 322 | swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; |
| 323 | } |
| 324 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 325 | dev_priv->mm.bit_6_swizzle_x = swizzle_x; |
| 326 | dev_priv->mm.bit_6_swizzle_y = swizzle_y; |
| 327 | } |
| 328 | |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 329 | |
| 330 | /** |
| 331 | * Returns the size of the fence for a tiled object of the given size. |
| 332 | */ |
| 333 | static int |
| 334 | i915_get_fence_size(struct drm_device *dev, int size) |
| 335 | { |
| 336 | int i; |
| 337 | int start; |
| 338 | |
| 339 | if (IS_I965G(dev)) { |
| 340 | /* The 965 can have fences at any page boundary. */ |
| 341 | return ALIGN(size, 4096); |
| 342 | } else { |
| 343 | /* Align the size to a power of two greater than the smallest |
| 344 | * fence size. |
| 345 | */ |
| 346 | if (IS_I9XX(dev)) |
| 347 | start = 1024 * 1024; |
| 348 | else |
| 349 | start = 512 * 1024; |
| 350 | |
| 351 | for (i = start; i < size; i <<= 1) |
| 352 | ; |
| 353 | |
| 354 | return i; |
| 355 | } |
| 356 | } |
| 357 | |
| 358 | /* Check pitch constriants for all chips & tiling formats */ |
| 359 | static bool |
| 360 | i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) |
| 361 | { |
| 362 | int tile_width; |
| 363 | |
| 364 | /* Linear is always fine */ |
| 365 | if (tiling_mode == I915_TILING_NONE) |
| 366 | return true; |
| 367 | |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 368 | if (!IS_I9XX(dev) || |
| 369 | (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))) |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 370 | tile_width = 128; |
| 371 | else |
| 372 | tile_width = 512; |
| 373 | |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 374 | /* check maximum stride & object size */ |
| 375 | if (IS_I965G(dev)) { |
| 376 | /* i965 stores the end address of the gtt mapping in the fence |
| 377 | * reg, so dont bother to check the size */ |
| 378 | if (stride / 128 > I965_FENCE_MAX_PITCH_VAL) |
| 379 | return false; |
| 380 | } else if (IS_I9XX(dev)) { |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 381 | uint32_t pitch_val = ffs(stride / tile_width) - 1; |
| 382 | |
| 383 | /* XXX: For Y tiling, FENCE_MAX_PITCH_VAL is actually 6 (8KB) |
| 384 | * instead of 4 (2KB) on 945s. |
| 385 | */ |
| 386 | if (pitch_val > I915_FENCE_MAX_PITCH_VAL || |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 387 | size > (I830_FENCE_MAX_SIZE_VAL << 20)) |
| 388 | return false; |
| 389 | } else { |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 390 | uint32_t pitch_val = ffs(stride / tile_width) - 1; |
| 391 | |
| 392 | if (pitch_val > I830_FENCE_MAX_PITCH_VAL || |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 393 | size > (I830_FENCE_MAX_SIZE_VAL << 19)) |
| 394 | return false; |
| 395 | } |
| 396 | |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 397 | /* 965+ just needs multiples of tile width */ |
| 398 | if (IS_I965G(dev)) { |
| 399 | if (stride & (tile_width - 1)) |
| 400 | return false; |
| 401 | return true; |
| 402 | } |
| 403 | |
| 404 | /* Pre-965 needs power of two tile widths */ |
| 405 | if (stride < tile_width) |
| 406 | return false; |
| 407 | |
| 408 | if (stride & (stride - 1)) |
| 409 | return false; |
| 410 | |
| 411 | /* We don't handle the aperture area covered by the fence being bigger |
| 412 | * than the object size. |
| 413 | */ |
| 414 | if (i915_get_fence_size(dev, size) != size) |
| 415 | return false; |
| 416 | |
| 417 | return true; |
| 418 | } |
| 419 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 420 | /** |
| 421 | * Sets the tiling mode of an object, returning the required swizzling of |
| 422 | * bit 6 of addresses in the object. |
| 423 | */ |
| 424 | int |
| 425 | i915_gem_set_tiling(struct drm_device *dev, void *data, |
| 426 | struct drm_file *file_priv) |
| 427 | { |
| 428 | struct drm_i915_gem_set_tiling *args = data; |
| 429 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 430 | struct drm_gem_object *obj; |
| 431 | struct drm_i915_gem_object *obj_priv; |
| 432 | |
| 433 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 434 | if (obj == NULL) |
| 435 | return -EINVAL; |
| 436 | obj_priv = obj->driver_private; |
| 437 | |
Chris Wilson | 72daad4 | 2009-01-30 21:10:22 +0000 | [diff] [blame] | 438 | if (!i915_tiling_ok(dev, args->stride, obj->size, args->tiling_mode)) { |
| 439 | drm_gem_object_unreference(obj); |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 440 | return -EINVAL; |
Chris Wilson | 72daad4 | 2009-01-30 21:10:22 +0000 | [diff] [blame] | 441 | } |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 442 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 443 | mutex_lock(&dev->struct_mutex); |
| 444 | |
| 445 | if (args->tiling_mode == I915_TILING_NONE) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 446 | args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; |
| 447 | } else { |
| 448 | if (args->tiling_mode == I915_TILING_X) |
| 449 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x; |
| 450 | else |
| 451 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 452 | |
| 453 | /* Hide bit 17 swizzling from the user. This prevents old Mesa |
| 454 | * from aborting the application on sw fallbacks to bit 17, |
| 455 | * and we use the pread/pwrite bit17 paths to swizzle for it. |
| 456 | * If there was a user that was relying on the swizzle |
| 457 | * information for drm_intel_bo_map()ed reads/writes this would |
| 458 | * break it, but we don't have any of those. |
| 459 | */ |
| 460 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17) |
| 461 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9; |
| 462 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17) |
| 463 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10; |
| 464 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 465 | /* If we can't handle the swizzling, make it untiled. */ |
| 466 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) { |
| 467 | args->tiling_mode = I915_TILING_NONE; |
| 468 | args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; |
| 469 | } |
| 470 | } |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 471 | if (args->tiling_mode != obj_priv->tiling_mode) { |
| 472 | int ret; |
| 473 | |
| 474 | /* Unbind the object, as switching tiling means we're |
| 475 | * switching the cache organization due to fencing, probably. |
| 476 | */ |
| 477 | ret = i915_gem_object_unbind(obj); |
| 478 | if (ret != 0) { |
| 479 | WARN(ret != -ERESTARTSYS, |
| 480 | "failed to unbind object for tiling switch"); |
| 481 | args->tiling_mode = obj_priv->tiling_mode; |
| 482 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 72daad4 | 2009-01-30 21:10:22 +0000 | [diff] [blame] | 483 | drm_gem_object_unreference(obj); |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 484 | |
| 485 | return ret; |
| 486 | } |
| 487 | obj_priv->tiling_mode = args->tiling_mode; |
| 488 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 489 | obj_priv->stride = args->stride; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 490 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 491 | drm_gem_object_unreference(obj); |
Chris Wilson | d687310 | 2009-02-08 19:07:51 +0000 | [diff] [blame] | 492 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 493 | |
| 494 | return 0; |
| 495 | } |
| 496 | |
| 497 | /** |
| 498 | * Returns the current tiling mode and required bit 6 swizzling for the object. |
| 499 | */ |
| 500 | int |
| 501 | i915_gem_get_tiling(struct drm_device *dev, void *data, |
| 502 | struct drm_file *file_priv) |
| 503 | { |
| 504 | struct drm_i915_gem_get_tiling *args = data; |
| 505 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 506 | struct drm_gem_object *obj; |
| 507 | struct drm_i915_gem_object *obj_priv; |
| 508 | |
| 509 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 510 | if (obj == NULL) |
| 511 | return -EINVAL; |
| 512 | obj_priv = obj->driver_private; |
| 513 | |
| 514 | mutex_lock(&dev->struct_mutex); |
| 515 | |
| 516 | args->tiling_mode = obj_priv->tiling_mode; |
| 517 | switch (obj_priv->tiling_mode) { |
| 518 | case I915_TILING_X: |
| 519 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x; |
| 520 | break; |
| 521 | case I915_TILING_Y: |
| 522 | args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y; |
| 523 | break; |
| 524 | case I915_TILING_NONE: |
| 525 | args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; |
| 526 | break; |
| 527 | default: |
| 528 | DRM_ERROR("unknown tiling mode\n"); |
| 529 | } |
| 530 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 531 | /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */ |
| 532 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17) |
| 533 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9; |
| 534 | if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17) |
| 535 | args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10; |
| 536 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 537 | drm_gem_object_unreference(obj); |
Chris Wilson | d687310 | 2009-02-08 19:07:51 +0000 | [diff] [blame] | 538 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 539 | |
| 540 | return 0; |
| 541 | } |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 542 | |
| 543 | /** |
| 544 | * Swap every 64 bytes of this page around, to account for it having a new |
| 545 | * bit 17 of its physical address and therefore being interpreted differently |
| 546 | * by the GPU. |
| 547 | */ |
| 548 | static int |
| 549 | i915_gem_swizzle_page(struct page *page) |
| 550 | { |
| 551 | char *vaddr; |
| 552 | int i; |
| 553 | char temp[64]; |
| 554 | |
| 555 | vaddr = kmap(page); |
| 556 | if (vaddr == NULL) |
| 557 | return -ENOMEM; |
| 558 | |
| 559 | for (i = 0; i < PAGE_SIZE; i += 128) { |
| 560 | memcpy(temp, &vaddr[i], 64); |
| 561 | memcpy(&vaddr[i], &vaddr[i + 64], 64); |
| 562 | memcpy(&vaddr[i + 64], temp, 64); |
| 563 | } |
| 564 | |
| 565 | kunmap(page); |
| 566 | |
| 567 | return 0; |
| 568 | } |
| 569 | |
| 570 | void |
| 571 | i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj) |
| 572 | { |
| 573 | struct drm_device *dev = obj->dev; |
| 574 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 575 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 576 | int page_count = obj->size >> PAGE_SHIFT; |
| 577 | int i; |
| 578 | |
| 579 | if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17) |
| 580 | return; |
| 581 | |
| 582 | if (obj_priv->bit_17 == NULL) |
| 583 | return; |
| 584 | |
| 585 | for (i = 0; i < page_count; i++) { |
| 586 | char new_bit_17 = page_to_phys(obj_priv->pages[i]) >> 17; |
| 587 | if ((new_bit_17 & 0x1) != |
| 588 | (test_bit(i, obj_priv->bit_17) != 0)) { |
| 589 | int ret = i915_gem_swizzle_page(obj_priv->pages[i]); |
| 590 | if (ret != 0) { |
| 591 | DRM_ERROR("Failed to swizzle page\n"); |
| 592 | return; |
| 593 | } |
| 594 | set_page_dirty(obj_priv->pages[i]); |
| 595 | } |
| 596 | } |
| 597 | } |
| 598 | |
| 599 | void |
| 600 | i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj) |
| 601 | { |
| 602 | struct drm_device *dev = obj->dev; |
| 603 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 604 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 605 | int page_count = obj->size >> PAGE_SHIFT; |
| 606 | int i; |
| 607 | |
| 608 | if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17) |
| 609 | return; |
| 610 | |
| 611 | if (obj_priv->bit_17 == NULL) { |
| 612 | obj_priv->bit_17 = kmalloc(BITS_TO_LONGS(page_count) * |
| 613 | sizeof(long), GFP_KERNEL); |
| 614 | if (obj_priv->bit_17 == NULL) { |
| 615 | DRM_ERROR("Failed to allocate memory for bit 17 " |
| 616 | "record\n"); |
| 617 | return; |
| 618 | } |
| 619 | } |
| 620 | |
| 621 | for (i = 0; i < page_count; i++) { |
| 622 | if (page_to_phys(obj_priv->pages[i]) & (1 << 17)) |
| 623 | __set_bit(i, obj_priv->bit_17); |
| 624 | else |
| 625 | __clear_bit(i, obj_priv->bit_17); |
| 626 | } |
| 627 | } |