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Laurent Pinchartac991dc2013-12-11 15:05:12 +01001/*
2 * Copyright 2013 Ideas On Board SPRL
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
11#define __DT_BINDINGS_CLOCK_R8A7790_H__
12
13/* CPG */
14#define R8A7790_CLK_MAIN 0
15#define R8A7790_CLK_PLL0 1
16#define R8A7790_CLK_PLL1 2
17#define R8A7790_CLK_PLL3 3
18#define R8A7790_CLK_LB 4
19#define R8A7790_CLK_QSPI 5
20#define R8A7790_CLK_SDH 6
21#define R8A7790_CLK_SD0 7
22#define R8A7790_CLK_SD1 8
23#define R8A7790_CLK_Z 9
24
Laurent Pinchart9d909512013-12-19 16:51:01 +010025/* MSTP0 */
26#define R8A7790_CLK_MSIOF0 0
27
Laurent Pinchartac991dc2013-12-11 15:05:12 +010028/* MSTP1 */
29#define R8A7790_CLK_TMU1 11
30#define R8A7790_CLK_TMU3 21
31#define R8A7790_CLK_TMU2 22
32#define R8A7790_CLK_CMT0 24
33#define R8A7790_CLK_TMU0 25
34#define R8A7790_CLK_VSP1_DU1 27
35#define R8A7790_CLK_VSP1_DU0 28
Laurent Pinchart79ea9932014-04-02 16:31:46 +020036#define R8A7790_CLK_VSP1_R 30
37#define R8A7790_CLK_VSP1_S 31
Laurent Pinchartac991dc2013-12-11 15:05:12 +010038
39/* MSTP2 */
40#define R8A7790_CLK_SCIFA2 2
41#define R8A7790_CLK_SCIFA1 3
42#define R8A7790_CLK_SCIFA0 4
Laurent Pinchart9d909512013-12-19 16:51:01 +010043#define R8A7790_CLK_MSIOF2 5
Laurent Pinchartac991dc2013-12-11 15:05:12 +010044#define R8A7790_CLK_SCIFB0 6
45#define R8A7790_CLK_SCIFB1 7
Laurent Pinchart9d909512013-12-19 16:51:01 +010046#define R8A7790_CLK_MSIOF1 8
47#define R8A7790_CLK_MSIOF3 15
Laurent Pinchartac991dc2013-12-11 15:05:12 +010048#define R8A7790_CLK_SCIFB2 16
Simon Hormanb998da02014-02-06 09:25:01 +090049#define R8A7790_CLK_SYS_DMAC1 18
50#define R8A7790_CLK_SYS_DMAC0 19
Laurent Pinchartac991dc2013-12-11 15:05:12 +010051
52/* MSTP3 */
Wolfram Sang01d968e2014-03-11 22:24:36 +010053#define R8A7790_CLK_IIC2 0
Laurent Pinchartac991dc2013-12-11 15:05:12 +010054#define R8A7790_CLK_TPU0 4
55#define R8A7790_CLK_MMCIF1 5
56#define R8A7790_CLK_SDHI3 11
57#define R8A7790_CLK_SDHI2 12
58#define R8A7790_CLK_SDHI1 13
59#define R8A7790_CLK_SDHI0 14
60#define R8A7790_CLK_MMCIF0 15
Wolfram Sang01d968e2014-03-11 22:24:36 +010061#define R8A7790_CLK_IIC0 18
62#define R8A7790_CLK_IIC1 23
Laurent Pinchartac991dc2013-12-11 15:05:12 +010063#define R8A7790_CLK_SSUSB 28
64#define R8A7790_CLK_CMT1 29
65#define R8A7790_CLK_USBDMAC0 30
66#define R8A7790_CLK_USBDMAC1 31
67
68/* MSTP5 */
69#define R8A7790_CLK_THERMAL 22
70#define R8A7790_CLK_PWM 23
71
72/* MSTP7 */
73#define R8A7790_CLK_EHCI 3
74#define R8A7790_CLK_HSUSB 4
75#define R8A7790_CLK_HSCIF1 16
76#define R8A7790_CLK_HSCIF0 17
77#define R8A7790_CLK_SCIF1 20
78#define R8A7790_CLK_SCIF0 21
79#define R8A7790_CLK_DU2 22
80#define R8A7790_CLK_DU1 23
81#define R8A7790_CLK_DU0 24
82#define R8A7790_CLK_LVDS1 25
83#define R8A7790_CLK_LVDS0 26
84
85/* MSTP8 */
86#define R8A7790_CLK_VIN3 8
87#define R8A7790_CLK_VIN2 9
88#define R8A7790_CLK_VIN1 10
89#define R8A7790_CLK_VIN0 11
90#define R8A7790_CLK_ETHER 13
91#define R8A7790_CLK_SATA1 14
92#define R8A7790_CLK_SATA0 15
93
94/* MSTP9 */
95#define R8A7790_CLK_GPIO5 7
96#define R8A7790_CLK_GPIO4 8
97#define R8A7790_CLK_GPIO3 9
98#define R8A7790_CLK_GPIO2 10
99#define R8A7790_CLK_GPIO1 11
100#define R8A7790_CLK_GPIO0 12
101#define R8A7790_CLK_RCAN1 15
102#define R8A7790_CLK_RCAN0 16
Laurent Pinchart91b56ca2013-12-19 16:51:03 +0100103#define R8A7790_CLK_QSPI_MOD 17
Laurent Pinchartac991dc2013-12-11 15:05:12 +0100104#define R8A7790_CLK_IICDVFS 26
105#define R8A7790_CLK_I2C3 28
106#define R8A7790_CLK_I2C2 29
107#define R8A7790_CLK_I2C1 30
108#define R8A7790_CLK_I2C0 31
109
Laurent Pinchartac991dc2013-12-11 15:05:12 +0100110#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */